aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5p64x0
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-s5p64x0')
-rw-r--r--arch/arm/mach-s5p64x0/Makefile4
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c6
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c6
-rw-r--r--arch/arm/mach-s5p64x0/gpiolib.c (renamed from arch/arm/mach-s5p64x0/gpio.c)221
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h57
5 files changed, 222 insertions, 72 deletions
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 2655829e6bf8..ae6bf6feba89 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -12,9 +12,9 @@ obj- :=
12 12
13# Core support for S5P64X0 system 13# Core support for S5P64X0 system
14 14
15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o 15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o 16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o
17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o gpio.o 17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o 18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
19 19
20# machine support 20# machine support
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 409c5fc3670d..40137c6f0488 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -419,7 +419,7 @@ static struct clksrc_sources clkset_audio = {
419static struct clksrc_clk clksrcs[] = { 419static struct clksrc_clk clksrcs[] = {
420 { 420 {
421 .clk = { 421 .clk = {
422 .name = "mmc_bus", 422 .name = "sclk_mmc",
423 .id = 0, 423 .id = 0,
424 .ctrlbit = (1 << 24), 424 .ctrlbit = (1 << 24),
425 .enable = s5p64x0_sclk_ctrl, 425 .enable = s5p64x0_sclk_ctrl,
@@ -429,7 +429,7 @@ static struct clksrc_clk clksrcs[] = {
429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, 429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
430 }, { 430 }, {
431 .clk = { 431 .clk = {
432 .name = "mmc_bus", 432 .name = "sclk_mmc",
433 .id = 1, 433 .id = 1,
434 .ctrlbit = (1 << 25), 434 .ctrlbit = (1 << 25),
435 .enable = s5p64x0_sclk_ctrl, 435 .enable = s5p64x0_sclk_ctrl,
@@ -439,7 +439,7 @@ static struct clksrc_clk clksrcs[] = {
439 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, 439 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
440 }, { 440 }, {
441 .clk = { 441 .clk = {
442 .name = "mmc_bus", 442 .name = "sclk_mmc",
443 .id = 2, 443 .id = 2,
444 .ctrlbit = (1 << 26), 444 .ctrlbit = (1 << 26),
445 .enable = s5p64x0_sclk_ctrl, 445 .enable = s5p64x0_sclk_ctrl,
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d8b20ee8cc8c..3f5ac93c455e 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -231,6 +231,12 @@ static struct clk init_clocks_disable[] = {
231 .enable = s5p64x0_pclk_ctrl, 231 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 5), 232 .ctrlbit = (1 << 5),
233 }, { 233 }, {
234 .name = "rtc",
235 .id = -1,
236 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 6),
239 }, {
234 .name = "adc", 240 .name = "adc",
235 .id = -1, 241 .id = -1,
236 .parent = &clk_pclk_low.clk, 242 .parent = &clk_pclk_low.clk,
diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpiolib.c
index 39159dd5a29a..e7fb3b004e77 100644
--- a/arch/arm/mach-s5p64x0/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5p64x0/gpio.c 1/* linux/arch/arm/mach-s5p64x0/gpiolib.c
2 * 2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
@@ -17,13 +17,12 @@
17 17
18#include <mach/map.h> 18#include <mach/map.h>
19#include <mach/regs-gpio.h> 19#include <mach/regs-gpio.h>
20#include <mach/regs-clock.h>
20 21
21#include <plat/gpio-core.h> 22#include <plat/gpio-core.h>
22#include <plat/gpio-cfg.h> 23#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h> 24#include <plat/gpio-cfg-helpers.h>
24 25
25/* To be implemented S5P6450 GPIO */
26
27/* 26/*
28 * S5P6440 GPIO bank summary: 27 * S5P6440 GPIO bank summary:
29 * 28 *
@@ -40,6 +39,25 @@
40 * P 8 2Bit Yes 8 39 * P 8 2Bit Yes 8
41 * R 15 4Bit[2] Yes 8 40 * R 15 4Bit[2] Yes 8
42 * 41 *
42 * S5P6450 GPIO bank summary:
43 *
44 * Bank GPIOs Style SlpCon ExtInt Group
45 * A 6 4Bit Yes 1
46 * B 7 4Bit Yes 1
47 * C 8 4Bit Yes 2
48 * D 8 4Bit Yes None
49 * F 2 2Bit Yes None
50 * G 14 4Bit[2] Yes 5
51 * H 10 4Bit[2] Yes 6
52 * I 16 2Bit Yes None
53 * J 12 2Bit Yes None
54 * K 5 4Bit Yes None
55 * N 16 2Bit No IRQ_EINT
56 * P 11 2Bit Yes 8
57 * Q 14 2Bit Yes None
58 * R 15 4Bit[2] Yes None
59 * S 8 2Bit Yes None
60 *
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources 61 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1 62 * [2] BANK has two control registers, GPxCON0 and GPxCON1
45 */ 63 */
@@ -190,7 +208,7 @@ static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
190 208
191static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { 209static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
192 { 210 {
193 .base = S5P6440_GPA_BASE, 211 .base = S5P64X0_GPA_BASE,
194 .config = &s5p64x0_gpio_cfgs[1], 212 .config = &s5p64x0_gpio_cfgs[1],
195 .chip = { 213 .chip = {
196 .base = S5P6440_GPA(0), 214 .base = S5P6440_GPA(0),
@@ -198,7 +216,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
198 .label = "GPA", 216 .label = "GPA",
199 }, 217 },
200 }, { 218 }, {
201 .base = S5P6440_GPB_BASE, 219 .base = S5P64X0_GPB_BASE,
202 .config = &s5p64x0_gpio_cfgs[1], 220 .config = &s5p64x0_gpio_cfgs[1],
203 .chip = { 221 .chip = {
204 .base = S5P6440_GPB(0), 222 .base = S5P6440_GPB(0),
@@ -206,7 +224,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
206 .label = "GPB", 224 .label = "GPB",
207 }, 225 },
208 }, { 226 }, {
209 .base = S5P6440_GPC_BASE, 227 .base = S5P64X0_GPC_BASE,
210 .config = &s5p64x0_gpio_cfgs[1], 228 .config = &s5p64x0_gpio_cfgs[1],
211 .chip = { 229 .chip = {
212 .base = S5P6440_GPC(0), 230 .base = S5P6440_GPC(0),
@@ -214,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
214 .label = "GPC", 232 .label = "GPC",
215 }, 233 },
216 }, { 234 }, {
217 .base = S5P6440_GPG_BASE, 235 .base = S5P64X0_GPG_BASE,
218 .config = &s5p64x0_gpio_cfgs[1], 236 .config = &s5p64x0_gpio_cfgs[1],
219 .chip = { 237 .chip = {
220 .base = S5P6440_GPG(0), 238 .base = S5P6440_GPG(0),
@@ -226,7 +244,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
226 244
227static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { 245static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
228 { 246 {
229 .base = S5P6440_GPH_BASE + 0x4, 247 .base = S5P64X0_GPH_BASE + 0x4,
230 .config = &s5p64x0_gpio_cfgs[1], 248 .config = &s5p64x0_gpio_cfgs[1],
231 .chip = { 249 .chip = {
232 .base = S5P6440_GPH(0), 250 .base = S5P6440_GPH(0),
@@ -238,7 +256,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
238 256
239static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { 257static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
240 { 258 {
241 .base = S5P6440_GPR_BASE + 0x4, 259 .base = S5P64X0_GPR_BASE + 0x4,
242 .config = &s5p64x0_gpio_cfgs[2], 260 .config = &s5p64x0_gpio_cfgs[2],
243 .chip = { 261 .chip = {
244 .base = S5P6440_GPR(0), 262 .base = S5P6440_GPR(0),
@@ -250,7 +268,7 @@ static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
250 268
251static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { 269static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
252 { 270 {
253 .base = S5P6440_GPF_BASE, 271 .base = S5P64X0_GPF_BASE,
254 .config = &s5p64x0_gpio_cfgs[5], 272 .config = &s5p64x0_gpio_cfgs[5],
255 .chip = { 273 .chip = {
256 .base = S5P6440_GPF(0), 274 .base = S5P6440_GPF(0),
@@ -258,7 +276,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
258 .label = "GPF", 276 .label = "GPF",
259 }, 277 },
260 }, { 278 }, {
261 .base = S5P6440_GPI_BASE, 279 .base = S5P64X0_GPI_BASE,
262 .config = &s5p64x0_gpio_cfgs[3], 280 .config = &s5p64x0_gpio_cfgs[3],
263 .chip = { 281 .chip = {
264 .base = S5P6440_GPI(0), 282 .base = S5P6440_GPI(0),
@@ -266,7 +284,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
266 .label = "GPI", 284 .label = "GPI",
267 }, 285 },
268 }, { 286 }, {
269 .base = S5P6440_GPJ_BASE, 287 .base = S5P64X0_GPJ_BASE,
270 .config = &s5p64x0_gpio_cfgs[3], 288 .config = &s5p64x0_gpio_cfgs[3],
271 .chip = { 289 .chip = {
272 .base = S5P6440_GPJ(0), 290 .base = S5P6440_GPJ(0),
@@ -274,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
274 .label = "GPJ", 292 .label = "GPJ",
275 }, 293 },
276 }, { 294 }, {
277 .base = S5P6440_GPN_BASE, 295 .base = S5P64X0_GPN_BASE,
278 .config = &s5p64x0_gpio_cfgs[4], 296 .config = &s5p64x0_gpio_cfgs[4],
279 .chip = { 297 .chip = {
280 .base = S5P6440_GPN(0), 298 .base = S5P6440_GPN(0),
@@ -282,7 +300,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
282 .label = "GPN", 300 .label = "GPN",
283 }, 301 },
284 }, { 302 }, {
285 .base = S5P6440_GPP_BASE, 303 .base = S5P64X0_GPP_BASE,
286 .config = &s5p64x0_gpio_cfgs[5], 304 .config = &s5p64x0_gpio_cfgs[5],
287 .chip = { 305 .chip = {
288 .base = S5P6440_GPP(0), 306 .base = S5P6440_GPP(0),
@@ -292,6 +310,142 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
292 }, 310 },
293}; 311};
294 312
313static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
314 {
315 .base = S5P64X0_GPA_BASE,
316 .config = &s5p64x0_gpio_cfgs[1],
317 .chip = {
318 .base = S5P6450_GPA(0),
319 .ngpio = S5P6450_GPIO_A_NR,
320 .label = "GPA",
321 },
322 }, {
323 .base = S5P64X0_GPB_BASE,
324 .config = &s5p64x0_gpio_cfgs[1],
325 .chip = {
326 .base = S5P6450_GPB(0),
327 .ngpio = S5P6450_GPIO_B_NR,
328 .label = "GPB",
329 },
330 }, {
331 .base = S5P64X0_GPC_BASE,
332 .config = &s5p64x0_gpio_cfgs[1],
333 .chip = {
334 .base = S5P6450_GPC(0),
335 .ngpio = S5P6450_GPIO_C_NR,
336 .label = "GPC",
337 },
338 }, {
339 .base = S5P6450_GPD_BASE,
340 .config = &s5p64x0_gpio_cfgs[1],
341 .chip = {
342 .base = S5P6450_GPD(0),
343 .ngpio = S5P6450_GPIO_D_NR,
344 .label = "GPD",
345 },
346 }, {
347 .base = S5P6450_GPK_BASE,
348 .config = &s5p64x0_gpio_cfgs[1],
349 .chip = {
350 .base = S5P6450_GPK(0),
351 .ngpio = S5P6450_GPIO_K_NR,
352 .label = "GPK",
353 },
354 },
355};
356
357static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
358 {
359 .base = S5P64X0_GPG_BASE + 0x4,
360 .config = &s5p64x0_gpio_cfgs[1],
361 .chip = {
362 .base = S5P6450_GPG(0),
363 .ngpio = S5P6450_GPIO_G_NR,
364 .label = "GPG",
365 },
366 }, {
367 .base = S5P64X0_GPH_BASE + 0x4,
368 .config = &s5p64x0_gpio_cfgs[1],
369 .chip = {
370 .base = S5P6450_GPH(0),
371 .ngpio = S5P6450_GPIO_H_NR,
372 .label = "GPH",
373 },
374 },
375};
376
377static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
378 {
379 .base = S5P64X0_GPR_BASE + 0x4,
380 .config = &s5p64x0_gpio_cfgs[2],
381 .chip = {
382 .base = S5P6450_GPR(0),
383 .ngpio = S5P6450_GPIO_R_NR,
384 .label = "GPR",
385 },
386 },
387};
388
389static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
390 {
391 .base = S5P64X0_GPF_BASE,
392 .config = &s5p64x0_gpio_cfgs[5],
393 .chip = {
394 .base = S5P6450_GPF(0),
395 .ngpio = S5P6450_GPIO_F_NR,
396 .label = "GPF",
397 },
398 }, {
399 .base = S5P64X0_GPI_BASE,
400 .config = &s5p64x0_gpio_cfgs[3],
401 .chip = {
402 .base = S5P6450_GPI(0),
403 .ngpio = S5P6450_GPIO_I_NR,
404 .label = "GPI",
405 },
406 }, {
407 .base = S5P64X0_GPJ_BASE,
408 .config = &s5p64x0_gpio_cfgs[3],
409 .chip = {
410 .base = S5P6450_GPJ(0),
411 .ngpio = S5P6450_GPIO_J_NR,
412 .label = "GPJ",
413 },
414 }, {
415 .base = S5P64X0_GPN_BASE,
416 .config = &s5p64x0_gpio_cfgs[4],
417 .chip = {
418 .base = S5P6450_GPN(0),
419 .ngpio = S5P6450_GPIO_N_NR,
420 .label = "GPN",
421 },
422 }, {
423 .base = S5P64X0_GPP_BASE,
424 .config = &s5p64x0_gpio_cfgs[5],
425 .chip = {
426 .base = S5P6450_GPP(0),
427 .ngpio = S5P6450_GPIO_P_NR,
428 .label = "GPP",
429 },
430 }, {
431 .base = S5P6450_GPQ_BASE,
432 .config = &s5p64x0_gpio_cfgs[4],
433 .chip = {
434 .base = S5P6450_GPQ(0),
435 .ngpio = S5P6450_GPIO_Q_NR,
436 .label = "GPQ",
437 },
438 }, {
439 .base = S5P6450_GPS_BASE,
440 .config = &s5p64x0_gpio_cfgs[5],
441 .chip = {
442 .base = S5P6450_GPS(0),
443 .ngpio = S5P6450_GPIO_S_NR,
444 .label = "GPS",
445 },
446 },
447};
448
295void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) 449void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
296{ 450{
297 for (; nr_chips > 0; nr_chips--, chipcfg++) { 451 for (; nr_chips > 0; nr_chips--, chipcfg++) {
@@ -317,26 +471,41 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
317 } 471 }
318} 472}
319 473
320static int __init s5p6440_gpiolib_init(void) 474static int __init s5p64x0_gpiolib_init(void)
321{ 475{
322 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; 476 unsigned int chipid;
323 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); 477
478 chipid = __raw_readl(S5P64X0_SYS_ID);
324 479
325 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, 480 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
326 ARRAY_SIZE(s5p64x0_gpio_cfgs)); 481 ARRAY_SIZE(s5p64x0_gpio_cfgs));
327 482
328 for (; nr_chips > 0; nr_chips--, chips++) 483 if ((chipid & 0xff000) == 0x50000) {
329 s3c_gpiolib_add(chips); 484 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
485 ARRAY_SIZE(s5p6450_gpio_2bit));
486
487 samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
488 ARRAY_SIZE(s5p6450_gpio_4bit));
330 489
331 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, 490 samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
332 ARRAY_SIZE(s5p6440_gpio_4bit)); 491 ARRAY_SIZE(s5p6450_gpio_4bit2));
333 492
334 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, 493 s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
335 ARRAY_SIZE(s5p6440_gpio_4bit2)); 494 ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
495 } else {
496 samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
497 ARRAY_SIZE(s5p6440_gpio_2bit));
336 498
337 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, 499 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
338 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); 500 ARRAY_SIZE(s5p6440_gpio_4bit));
501
502 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
503 ARRAY_SIZE(s5p6440_gpio_4bit2));
504
505 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
506 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
507 }
339 508
340 return 0; 509 return 0;
341} 510}
342arch_initcall(s5p6440_gpiolib_init); 511core_initcall(s5p64x0_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 85f448e20a8b..0953ef6b1c77 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -15,48 +15,23 @@
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18/* Will be implemented S5P6442 GPIOlib */
19
20/* Base addresses for each of the banks */ 18/* Base addresses for each of the banks */
21 19
22#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) 20#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000)
23#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) 21#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020)
24#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) 22#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040)
25#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0) 23#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0)
26#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0) 24#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0)
27#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0) 25#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0)
28#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100) 26#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100)
29#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120) 27#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120)
30#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) 28#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830)
31#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) 29#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160)
32#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) 30#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290)
33 31
34#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) 32#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060)
35#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) 33#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140)
36#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) 34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
37#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920) 35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
38#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
39
40/* for LCD */
41
42#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
43#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
44
45/*
46 * These set of macros are not really useful for the
47 * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
48 */
49
50#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
51#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
52#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
53
54/*
55 * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
56 */
57
58#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
59#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
60#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
61 36
62#endif /* __ASM_ARCH_REGS_GPIO_H */ 37#endif /* __ASM_ARCH_REGS_GPIO_H */