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-rw-r--r--arch/arm/mach-s5p64x0/include/mach/debug-macro.S32
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/gpio.h132
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h148
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h96
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/pm-core.h119
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-clock.h98
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h68
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-irq.h18
10 files changed, 0 insertions, 755 deletions
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
deleted file mode 100644
index 8759e7882bcb..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <linux/serial_s3c.h>
14#include <plat/map-base.h>
15#include <plat/map-s5p.h>
16
17 .macro addruart, rp, rv, tmp
18 mov \rp, #0xE0000000
19 orr \rp, \rp, #0x00100000
20 ldr \rp, [\rp, #0x118 ]
21 and \rp, \rp, #0xff000
22 teq \rp, #0x50000 @@ S5P6450
23 ldreq \rp, =0xEC800000
24 movne \rp, #0xEC000000 @@ S5P6440
25 ldrne \rv, = S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
deleted file mode 100644
index 5a622af461d7..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
deleted file mode 100644
index 06cd3c9b16ac..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/gpio.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16/* GPIO bank sizes */
17
18#define S5P6440_GPIO_A_NR (6)
19#define S5P6440_GPIO_B_NR (7)
20#define S5P6440_GPIO_C_NR (8)
21#define S5P6440_GPIO_F_NR (16)
22#define S5P6440_GPIO_G_NR (7)
23#define S5P6440_GPIO_H_NR (10)
24#define S5P6440_GPIO_I_NR (16)
25#define S5P6440_GPIO_J_NR (12)
26#define S5P6440_GPIO_N_NR (16)
27#define S5P6440_GPIO_P_NR (8)
28#define S5P6440_GPIO_R_NR (15)
29
30#define S5P6450_GPIO_A_NR (6)
31#define S5P6450_GPIO_B_NR (7)
32#define S5P6450_GPIO_C_NR (8)
33#define S5P6450_GPIO_D_NR (8)
34#define S5P6450_GPIO_F_NR (16)
35#define S5P6450_GPIO_G_NR (14)
36#define S5P6450_GPIO_H_NR (10)
37#define S5P6450_GPIO_I_NR (16)
38#define S5P6450_GPIO_J_NR (12)
39#define S5P6450_GPIO_K_NR (5)
40#define S5P6450_GPIO_N_NR (16)
41#define S5P6450_GPIO_P_NR (11)
42#define S5P6450_GPIO_Q_NR (14)
43#define S5P6450_GPIO_R_NR (15)
44#define S5P6450_GPIO_S_NR (8)
45
46/* GPIO bank numbers */
47
48/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
49 * space for debugging purposes so that any accidental
50 * change from one gpio bank to another can be caught.
51*/
52
53#define S5P64X0_GPIO_NEXT(__gpio) \
54 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
55
56enum s5p6440_gpio_number {
57 S5P6440_GPIO_A_START = 0,
58 S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
59 S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
60 S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
61 S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
62 S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
63 S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
64 S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
65 S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
66 S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
67 S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
68};
69
70enum s5p6450_gpio_number {
71 S5P6450_GPIO_A_START = 0,
72 S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
73 S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
74 S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
75 S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
76 S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
77 S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
78 S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
79 S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
80 S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
81 S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
82 S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
83 S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
84 S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
85 S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
86};
87
88/* GPIO number definitions */
89
90#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
91#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
92#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
93#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
94#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
95#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
96#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
97#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
98#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
99#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
100#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
101
102#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
103#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
104#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
105#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
106#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
107#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
108#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
109#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
110#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
111#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
112#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
113#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
114#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
115#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
116#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
117
118/* the end of the S5P64X0 specific gpios */
119
120#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
121#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
122
123#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
124 S5P6440_GPIO_END : S5P6450_GPIO_END)
125
126#define S3C_GPIO_END S5P64X0_GPIO_END
127
128/* define the number of gpios we need to the one after the last GPIO range */
129
130#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
131
132#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
deleted file mode 100644
index d3e87996dd9a..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
deleted file mode 100644
index 53982db9d259..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
2 *
3 * Copyright 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
24#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
25#define IRQ_IIC1 S5P_IRQ_VIC0(5)
26#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
27#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
28
29#define IRQ_2D S5P_IRQ_VIC0(11)
30#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
31#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
32#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
33#define IRQ_WDT S5P_IRQ_VIC0(26)
34#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
35#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
36#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
37#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
38#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
39
40/* VIC1 */
41
42#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
43#define IRQ_PCM0 S5P_IRQ_VIC1(2)
44#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
45#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
46#define IRQ_UART0 S5P_IRQ_VIC1(5)
47#define IRQ_UART1 S5P_IRQ_VIC1(6)
48#define IRQ_UART2 S5P_IRQ_VIC1(7)
49#define IRQ_UART3 S5P_IRQ_VIC1(8)
50#define IRQ_DMA0 S5P_IRQ_VIC1(9)
51#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
52#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
53#define IRQ_NFC S5P_IRQ_VIC1(13)
54#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
55#define IRQ_SPI0 S5P_IRQ_VIC1(16)
56#define IRQ_SPI1 S5P_IRQ_VIC1(17)
57#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
58#define IRQ_IIC S5P_IRQ_VIC1(18)
59#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
60#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
61#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
62#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
63#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
64#define IRQ_OTG S5P_IRQ_VIC1(26)
65#define IRQ_DSI S5P_IRQ_VIC1(27)
66#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
67#define IRQ_TSI S5P_IRQ_VIC1(29)
68#define IRQ_PENDN S5P_IRQ_VIC1(30)
69#define IRQ_TC IRQ_PENDN
70#define IRQ_ADC S5P_IRQ_VIC1(31)
71
72/* UART interrupts, S5P6450 has 5 UARTs */
73#define IRQ_S5P_UART_BASE4 (96)
74#define IRQ_S5P_UART_BASE5 (100)
75
76#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
77#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
78#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
79
80#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
81#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
82#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
83
84/* S3C compatibilty defines */
85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
87
88#define IRQ_I2S0 IRQ_I2SV40
89
90#define IRQ_LCD_FIFO IRQ_DISPCON0
91#define IRQ_LCD_VSYNC IRQ_DISPCON1
92#define IRQ_LCD_SYSTEM IRQ_DISPCON2
93
94/* S5P6450 EINT feature will be added */
95
96/*
97 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
98 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
99 * after the pair of VICs.
100 */
101
102#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
103
104#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
105
106#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
107/*
108 * S5P6440 has 0-15 external interrupts in group 0. Only these can be used
109 * to wake up from sleep. If request is beyond this range, by mistake, a large
110 * return value for an irq number should be indication of something amiss.
111 */
112#define S5P_EINT_BASE2 (0xf0000000)
113
114/*
115 * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
116 * that they are sourced from the GPIO pins but with a different scheme for
117 * priority and source indication.
118 *
119 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
120 * interrupts, but for historical reasons they are kept apart from these
121 * next interrupts.
122 *
123 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
124 * machine specific support files.
125 */
126
127/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
128#define IRQ_EINT_GROUP1_NR (15)
129#define IRQ_EINT_GROUP2_NR (8)
130#define IRQ_EINT_GROUP5_NR (7)
131#define IRQ_EINT_GROUP6_NR (10)
132/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
133#define IRQ_EINT_GROUP8_NR (11)
134
135#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
136#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
137#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
138#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
139#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
140#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143
144/* Set the default NR_IRQS */
145
146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
147
148#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
deleted file mode 100644
index 50a6e96d6389..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P64X0_PA_SDRAM 0x20000000
20
21#define S5P64X0_PA_CHIPID 0xE0000000
22
23#define S5P64X0_PA_SYSCON 0xE0100000
24
25#define S5P64X0_PA_GPIO 0xE0308000
26
27#define S5P64X0_PA_VIC0 0xE4000000
28#define S5P64X0_PA_VIC1 0xE4100000
29
30#define S5P64X0_PA_SROMC 0xE7000000
31
32#define S5P64X0_PA_PDMA 0xE9000000
33
34#define S5P64X0_PA_TIMER 0xEA000000
35#define S5P64X0_PA_RTC 0xEA100000
36#define S5P64X0_PA_WDT 0xEA200000
37
38#define S5P6440_PA_IIC0 0xEC104000
39#define S5P6440_PA_IIC1 0xEC20F000
40#define S5P6450_PA_IIC0 0xEC100000
41#define S5P6450_PA_IIC1 0xEC200000
42
43#define S5P64X0_PA_SPI0 0xEC400000
44#define S5P64X0_PA_SPI1 0xEC500000
45
46#define S5P64X0_PA_HSOTG 0xED100000
47
48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
49
50#define S5P64X0_PA_FB 0xEE000000
51
52#define S5P64X0_PA_I2S 0xF2000000
53#define S5P6450_PA_I2S1 0xF2800000
54#define S5P6450_PA_I2S2 0xF2900000
55
56#define S5P64X0_PA_PCM 0xF2100000
57
58#define S5P64X0_PA_ADC 0xF3000000
59
60/* Compatibiltiy Defines */
61
62#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
63#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
64#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
65#define S3C_PA_IIC S5P6440_PA_IIC0
66#define S3C_PA_IIC1 S5P6440_PA_IIC1
67#define S3C_PA_RTC S5P64X0_PA_RTC
68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB
70#define S3C_PA_SPI0 S5P64X0_PA_SPI0
71#define S3C_PA_SPI1 S5P64X0_PA_SPI1
72
73#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
74#define S5P_PA_SROMC S5P64X0_PA_SROMC
75#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
76#define S5P_PA_TIMER S5P64X0_PA_TIMER
77
78#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
79#define SAMSUNG_PA_TIMER S5P64X0_PA_TIMER
80
81/* UART */
82
83#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
84#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
85
86#define S5P_PA_UART0 S5P6450_PA_UART(0)
87#define S5P_PA_UART1 S5P6450_PA_UART(1)
88#define S5P_PA_UART2 S5P6450_PA_UART(2)
89#define S5P_PA_UART3 S5P6450_PA_UART(3)
90#define S5P_PA_UART4 S5P6450_PA_UART(4)
91#define S5P_PA_UART5 S5P6450_PA_UART(5)
92
93#define S5P_SZ_UART SZ_256
94#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
95
96#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
deleted file mode 100644
index 1e0eb65b2b82..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
7 *
8 * Based on PM core support for S3C64XX by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/serial_s3c.h>
16
17#include <mach/regs-gpio.h>
18
19static inline void s3c_pm_debug_init_uart(void)
20{
21 u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
22
23 /*
24 * As a note, since the S5P64X0 UARTs generally have multiple
25 * clock sources, we simply enable PCLK at the moment and hope
26 * that the resume settings for the UART are suitable for the
27 * use with PCLK.
28 */
29 tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
30 tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
31 tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
32 tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
33
34 __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
35 udelay(10);
36}
37
38static inline void s3c_pm_arch_prepare_irqs(void)
39{
40 /* VIC should have already been taken care of */
41
42 /* clear any pending EINT0 interrupts */
43 __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
44}
45
46static inline void s3c_pm_arch_stop_clocks(void) { }
47static inline void s3c_pm_arch_show_resume_irqs(void) { }
48
49/*
50 * make these defines, we currently do not have any need to change
51 * the IRQ wake controls depending on the CPU we are running on
52 */
53#define s3c_irqwake_eintallow ((1 << 16) - 1)
54#define s3c_irqwake_intallow (~0)
55
56static inline void s3c_pm_arch_update_uart(void __iomem *regs,
57 struct pm_uart_save *save)
58{
59 u32 ucon = __raw_readl(regs + S3C2410_UCON);
60 u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
61 u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
62 u32 new_ucon;
63 u32 delta;
64
65 /*
66 * S5P64X0 UART blocks only support level interrupts, so ensure that
67 * when we restore unused UART blocks we force the level interrupt
68 * settings.
69 */
70 save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
71
72 /*
73 * We have a constraint on changing the clock type of the UART
74 * between UCLKx and PCLK, so ensure that when we restore UCON
75 * that the CLK field is correctly modified if the bootloader
76 * has changed anything.
77 */
78 if (ucon_clk != save_clk) {
79 new_ucon = save->ucon;
80 delta = ucon_clk ^ save_clk;
81
82 /*
83 * change from UCLKx => wrong PCLK,
84 * either UCLK can be tested for by a bit-test
85 * with UCLK0
86 */
87 if (ucon_clk & S3C6400_UCON_UCLK0 &&
88 !(save_clk & S3C6400_UCON_UCLK0) &&
89 delta & S3C6400_UCON_PCLK2) {
90 new_ucon &= ~S3C6400_UCON_UCLK0;
91 } else if (delta == S3C6400_UCON_PCLK2) {
92 /*
93 * as a precaution, don't change from
94 * PCLK2 => PCLK or vice-versa
95 */
96 new_ucon ^= S3C6400_UCON_PCLK2;
97 }
98
99 S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
100 ucon, new_ucon, save->ucon);
101 save->ucon = new_ucon;
102 }
103}
104
105static inline void s3c_pm_restored_gpios(void)
106{
107 /* ensure sleep mode has been cleared from the system */
108 __raw_writel(0, S5P64X0_SLPEN);
109}
110
111static inline void samsung_pm_saved_gpios(void)
112{
113 /*
114 * turn on the sleep mode and keep it there, as it seems that during
115 * suspend the xCON registers get re-set and thus you can end up with
116 * problems between going to sleep and resuming.
117 */
118 __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
119}
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
deleted file mode 100644
index bd91112c813c..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
21#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
22#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
23#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
24
25#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
26
27#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
28#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
29#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
30
31#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
32#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
33#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
34#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
35
36#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
37
38#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
39#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
40
41#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
42#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
43
44#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
45#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
46
47#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
48#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
49
50#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
51#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
52#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
53#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
54
55#define S5P64X0_OTHERS S5P_CLKREG(0x900)
56#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
57
58#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
59
60#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
61#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
62
63/* HCLK GATE Registers */
64#define S5P64X0_CLK_GATE_HCLK1_FIMGVG (1 << 2)
65#define S5P64X0_CLK_GATE_SCLK1_FIMGVG (1 << 2)
66
67/* PCLK GATE Registers */
68#define S5P64X0_CLK_GATE_PCLK_UART3 (1 << 4)
69#define S5P64X0_CLK_GATE_PCLK_UART2 (1 << 3)
70#define S5P64X0_CLK_GATE_PCLK_UART1 (1 << 2)
71#define S5P64X0_CLK_GATE_PCLK_UART0 (1 << 1)
72
73#define S5P64X0_PWR_CFG_MMC1_DISABLE (1 << 15)
74#define S5P64X0_PWR_CFG_MMC0_DISABLE (1 << 14)
75#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE (1 << 11)
76#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE (1 << 10)
77#define S5P64X0_PWR_CFG_WFI_MASK (3 << 5)
78#define S5P64X0_PWR_CFG_WFI_SLEEP (3 << 5)
79
80#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
81
82#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
83
84#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
85#define S5P64X0_OTHERS_RET_UART (1 << 26)
86#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
87#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
88#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
89
90/* Compatibility defines */
91
92#define ARM_CLK_DIV S5P64X0_CLK_DIV0
93#define ARM_DIV_RATIO_SHIFT 0
94#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
95
96#define S5P_EPLL_CON S5P64X0_EPLL_CON
97
98#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
deleted file mode 100644
index cfdfa4fdadf2..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18/* Base addresses for each of the banks */
19
20#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000)
21#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020)
22#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040)
23#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0)
24#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0)
25#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0)
26#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100)
27#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120)
28#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830)
29#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160)
30#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290)
31
32#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060)
33#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140)
34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
36
37#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
38#define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0)
39#define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0)
40#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
41
42#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
43#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
44#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
45#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
46
47#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
48#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
49#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
50
51/* External interrupt control registers for group0 */
52
53#define EINT0CON0_OFFSET (0x900)
54#define EINT0FLTCON0_OFFSET (0x910)
55#define EINT0FLTCON1_OFFSET (0x914)
56#define EINT0MASK_OFFSET (0x920)
57#define EINT0PEND_OFFSET (0x924)
58
59#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
60#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
61#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
62#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
63#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
64
65#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
66#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
67
68#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
deleted file mode 100644
index d60397d1ff40..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <mach/map.h>
17
18#endif /* __ASM_ARCH_REGS_IRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 12:25:54 -0500