diff options
Diffstat (limited to 'arch/arm/mach-s5p64x0/dma.c')
-rw-r--r-- | arch/arm/mach-s5p64x0/dma.c | 269 |
1 files changed, 181 insertions, 88 deletions
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c index 0e5b3e63e5b3..442dd4ad12da 100644 --- a/arch/arm/mach-s5p64x0/dma.c +++ b/arch/arm/mach-s5p64x0/dma.c | |||
@@ -21,115 +21,208 @@ | |||
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | 21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
22 | */ | 22 | */ |
23 | 23 | ||
24 | #include <linux/platform_device.h> | ||
25 | #include <linux/dma-mapping.h> | 24 | #include <linux/dma-mapping.h> |
25 | #include <linux/amba/bus.h> | ||
26 | #include <linux/amba/pl330.h> | ||
27 | |||
28 | #include <asm/irq.h> | ||
26 | 29 | ||
27 | #include <mach/map.h> | 30 | #include <mach/map.h> |
28 | #include <mach/irqs.h> | 31 | #include <mach/irqs.h> |
29 | #include <mach/regs-clock.h> | 32 | #include <mach/regs-clock.h> |
33 | #include <mach/dma.h> | ||
30 | 34 | ||
31 | #include <plat/cpu.h> | 35 | #include <plat/cpu.h> |
32 | #include <plat/devs.h> | 36 | #include <plat/devs.h> |
33 | #include <plat/s3c-pl330-pdata.h> | 37 | #include <plat/irqs.h> |
34 | 38 | ||
35 | static u64 dma_dmamask = DMA_BIT_MASK(32); | 39 | static u64 dma_dmamask = DMA_BIT_MASK(32); |
36 | 40 | ||
37 | static struct resource s5p64x0_pdma_resource[] = { | 41 | struct dma_pl330_peri s5p6440_pdma_peri[22] = { |
38 | [0] = { | 42 | { |
39 | .start = S5P64X0_PA_PDMA, | 43 | .peri_id = (u8)DMACH_UART0_RX, |
40 | .end = S5P64X0_PA_PDMA + SZ_4K, | 44 | .rqtype = DEVTOMEM, |
41 | .flags = IORESOURCE_MEM, | 45 | }, { |
42 | }, | 46 | .peri_id = (u8)DMACH_UART0_TX, |
43 | [1] = { | 47 | .rqtype = MEMTODEV, |
44 | .start = IRQ_DMA0, | 48 | }, { |
45 | .end = IRQ_DMA0, | 49 | .peri_id = (u8)DMACH_UART1_RX, |
46 | .flags = IORESOURCE_IRQ, | 50 | .rqtype = DEVTOMEM, |
51 | }, { | ||
52 | .peri_id = (u8)DMACH_UART1_TX, | ||
53 | .rqtype = MEMTODEV, | ||
54 | }, { | ||
55 | .peri_id = (u8)DMACH_UART2_RX, | ||
56 | .rqtype = DEVTOMEM, | ||
57 | }, { | ||
58 | .peri_id = (u8)DMACH_UART2_TX, | ||
59 | .rqtype = MEMTODEV, | ||
60 | }, { | ||
61 | .peri_id = (u8)DMACH_UART3_RX, | ||
62 | .rqtype = DEVTOMEM, | ||
63 | }, { | ||
64 | .peri_id = (u8)DMACH_UART3_TX, | ||
65 | .rqtype = MEMTODEV, | ||
66 | }, { | ||
67 | .peri_id = DMACH_MAX, | ||
68 | }, { | ||
69 | .peri_id = DMACH_MAX, | ||
70 | }, { | ||
71 | .peri_id = (u8)DMACH_PCM0_TX, | ||
72 | .rqtype = MEMTODEV, | ||
73 | }, { | ||
74 | .peri_id = (u8)DMACH_PCM0_RX, | ||
75 | .rqtype = DEVTOMEM, | ||
76 | }, { | ||
77 | .peri_id = (u8)DMACH_I2S0_TX, | ||
78 | .rqtype = MEMTODEV, | ||
79 | }, { | ||
80 | .peri_id = (u8)DMACH_I2S0_RX, | ||
81 | .rqtype = DEVTOMEM, | ||
82 | }, { | ||
83 | .peri_id = (u8)DMACH_SPI0_TX, | ||
84 | .rqtype = MEMTODEV, | ||
85 | }, { | ||
86 | .peri_id = (u8)DMACH_SPI0_RX, | ||
87 | .rqtype = DEVTOMEM, | ||
88 | }, { | ||
89 | .peri_id = (u8)DMACH_MAX, | ||
90 | }, { | ||
91 | .peri_id = (u8)DMACH_MAX, | ||
92 | }, { | ||
93 | .peri_id = (u8)DMACH_MAX, | ||
94 | }, { | ||
95 | .peri_id = (u8)DMACH_MAX, | ||
96 | }, { | ||
97 | .peri_id = (u8)DMACH_SPI1_TX, | ||
98 | .rqtype = MEMTODEV, | ||
99 | }, { | ||
100 | .peri_id = (u8)DMACH_SPI1_RX, | ||
101 | .rqtype = DEVTOMEM, | ||
47 | }, | 102 | }, |
48 | }; | 103 | }; |
49 | 104 | ||
50 | static struct s3c_pl330_platdata s5p6440_pdma_pdata = { | 105 | struct dma_pl330_platdata s5p6440_pdma_pdata = { |
51 | .peri = { | 106 | .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), |
52 | [0] = DMACH_UART0_RX, | 107 | .peri = s5p6440_pdma_peri, |
53 | [1] = DMACH_UART0_TX, | ||
54 | [2] = DMACH_UART1_RX, | ||
55 | [3] = DMACH_UART1_TX, | ||
56 | [4] = DMACH_UART2_RX, | ||
57 | [5] = DMACH_UART2_TX, | ||
58 | [6] = DMACH_UART3_RX, | ||
59 | [7] = DMACH_UART3_TX, | ||
60 | [8] = DMACH_MAX, | ||
61 | [9] = DMACH_MAX, | ||
62 | [10] = DMACH_PCM0_TX, | ||
63 | [11] = DMACH_PCM0_RX, | ||
64 | [12] = DMACH_I2S0_TX, | ||
65 | [13] = DMACH_I2S0_RX, | ||
66 | [14] = DMACH_SPI0_TX, | ||
67 | [15] = DMACH_SPI0_RX, | ||
68 | [16] = DMACH_MAX, | ||
69 | [17] = DMACH_MAX, | ||
70 | [18] = DMACH_MAX, | ||
71 | [19] = DMACH_MAX, | ||
72 | [20] = DMACH_SPI1_TX, | ||
73 | [21] = DMACH_SPI1_RX, | ||
74 | [22] = DMACH_MAX, | ||
75 | [23] = DMACH_MAX, | ||
76 | [24] = DMACH_MAX, | ||
77 | [25] = DMACH_MAX, | ||
78 | [26] = DMACH_MAX, | ||
79 | [27] = DMACH_MAX, | ||
80 | [28] = DMACH_MAX, | ||
81 | [29] = DMACH_PWM, | ||
82 | [30] = DMACH_MAX, | ||
83 | [31] = DMACH_MAX, | ||
84 | }, | ||
85 | }; | 108 | }; |
86 | 109 | ||
87 | static struct s3c_pl330_platdata s5p6450_pdma_pdata = { | 110 | struct dma_pl330_peri s5p6450_pdma_peri[32] = { |
88 | .peri = { | 111 | { |
89 | [0] = DMACH_UART0_RX, | 112 | .peri_id = (u8)DMACH_UART0_RX, |
90 | [1] = DMACH_UART0_TX, | 113 | .rqtype = DEVTOMEM, |
91 | [2] = DMACH_UART1_RX, | 114 | }, { |
92 | [3] = DMACH_UART1_TX, | 115 | .peri_id = (u8)DMACH_UART0_TX, |
93 | [4] = DMACH_UART2_RX, | 116 | .rqtype = MEMTODEV, |
94 | [5] = DMACH_UART2_TX, | 117 | }, { |
95 | [6] = DMACH_UART3_RX, | 118 | .peri_id = (u8)DMACH_UART1_RX, |
96 | [7] = DMACH_UART3_TX, | 119 | .rqtype = DEVTOMEM, |
97 | [8] = DMACH_UART4_RX, | 120 | }, { |
98 | [9] = DMACH_UART4_TX, | 121 | .peri_id = (u8)DMACH_UART1_TX, |
99 | [10] = DMACH_PCM0_TX, | 122 | .rqtype = MEMTODEV, |
100 | [11] = DMACH_PCM0_RX, | 123 | }, { |
101 | [12] = DMACH_I2S0_TX, | 124 | .peri_id = (u8)DMACH_UART2_RX, |
102 | [13] = DMACH_I2S0_RX, | 125 | .rqtype = DEVTOMEM, |
103 | [14] = DMACH_SPI0_TX, | 126 | }, { |
104 | [15] = DMACH_SPI0_RX, | 127 | .peri_id = (u8)DMACH_UART2_TX, |
105 | [16] = DMACH_PCM1_TX, | 128 | .rqtype = MEMTODEV, |
106 | [17] = DMACH_PCM1_RX, | 129 | }, { |
107 | [18] = DMACH_PCM2_TX, | 130 | .peri_id = (u8)DMACH_UART3_RX, |
108 | [19] = DMACH_PCM2_RX, | 131 | .rqtype = DEVTOMEM, |
109 | [20] = DMACH_SPI1_TX, | 132 | }, { |
110 | [21] = DMACH_SPI1_RX, | 133 | .peri_id = (u8)DMACH_UART3_TX, |
111 | [22] = DMACH_USI_TX, | 134 | .rqtype = MEMTODEV, |
112 | [23] = DMACH_USI_RX, | 135 | }, { |
113 | [24] = DMACH_MAX, | 136 | .peri_id = (u8)DMACH_UART4_RX, |
114 | [25] = DMACH_I2S1_TX, | 137 | .rqtype = DEVTOMEM, |
115 | [26] = DMACH_I2S1_RX, | 138 | }, { |
116 | [27] = DMACH_I2S2_TX, | 139 | .peri_id = (u8)DMACH_UART4_TX, |
117 | [28] = DMACH_I2S2_RX, | 140 | .rqtype = MEMTODEV, |
118 | [29] = DMACH_PWM, | 141 | }, { |
119 | [30] = DMACH_UART5_RX, | 142 | .peri_id = (u8)DMACH_PCM0_TX, |
120 | [31] = DMACH_UART5_TX, | 143 | .rqtype = MEMTODEV, |
144 | }, { | ||
145 | .peri_id = (u8)DMACH_PCM0_RX, | ||
146 | .rqtype = DEVTOMEM, | ||
147 | }, { | ||
148 | .peri_id = (u8)DMACH_I2S0_TX, | ||
149 | .rqtype = MEMTODEV, | ||
150 | }, { | ||
151 | .peri_id = (u8)DMACH_I2S0_RX, | ||
152 | .rqtype = DEVTOMEM, | ||
153 | }, { | ||
154 | .peri_id = (u8)DMACH_SPI0_TX, | ||
155 | .rqtype = MEMTODEV, | ||
156 | }, { | ||
157 | .peri_id = (u8)DMACH_SPI0_RX, | ||
158 | .rqtype = DEVTOMEM, | ||
159 | }, { | ||
160 | .peri_id = (u8)DMACH_PCM1_TX, | ||
161 | .rqtype = MEMTODEV, | ||
162 | }, { | ||
163 | .peri_id = (u8)DMACH_PCM1_RX, | ||
164 | .rqtype = DEVTOMEM, | ||
165 | }, { | ||
166 | .peri_id = (u8)DMACH_PCM2_TX, | ||
167 | .rqtype = MEMTODEV, | ||
168 | }, { | ||
169 | .peri_id = (u8)DMACH_PCM2_RX, | ||
170 | .rqtype = DEVTOMEM, | ||
171 | }, { | ||
172 | .peri_id = (u8)DMACH_SPI1_TX, | ||
173 | .rqtype = MEMTODEV, | ||
174 | }, { | ||
175 | .peri_id = (u8)DMACH_SPI1_RX, | ||
176 | .rqtype = DEVTOMEM, | ||
177 | }, { | ||
178 | .peri_id = (u8)DMACH_USI_TX, | ||
179 | .rqtype = MEMTODEV, | ||
180 | }, { | ||
181 | .peri_id = (u8)DMACH_USI_RX, | ||
182 | .rqtype = DEVTOMEM, | ||
183 | }, { | ||
184 | .peri_id = (u8)DMACH_MAX, | ||
185 | }, { | ||
186 | .peri_id = (u8)DMACH_I2S1_TX, | ||
187 | .rqtype = MEMTODEV, | ||
188 | }, { | ||
189 | .peri_id = (u8)DMACH_I2S1_RX, | ||
190 | .rqtype = DEVTOMEM, | ||
191 | }, { | ||
192 | .peri_id = (u8)DMACH_I2S2_TX, | ||
193 | .rqtype = MEMTODEV, | ||
194 | }, { | ||
195 | .peri_id = (u8)DMACH_I2S2_RX, | ||
196 | .rqtype = DEVTOMEM, | ||
197 | }, { | ||
198 | .peri_id = (u8)DMACH_PWM, | ||
199 | }, { | ||
200 | .peri_id = (u8)DMACH_UART5_RX, | ||
201 | .rqtype = DEVTOMEM, | ||
202 | }, { | ||
203 | .peri_id = (u8)DMACH_UART5_TX, | ||
204 | .rqtype = MEMTODEV, | ||
121 | }, | 205 | }, |
122 | }; | 206 | }; |
123 | 207 | ||
124 | static struct platform_device s5p64x0_device_pdma = { | 208 | struct dma_pl330_platdata s5p6450_pdma_pdata = { |
125 | .name = "s3c-pl330", | 209 | .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), |
126 | .id = -1, | 210 | .peri = s5p6450_pdma_peri, |
127 | .num_resources = ARRAY_SIZE(s5p64x0_pdma_resource), | 211 | }; |
128 | .resource = s5p64x0_pdma_resource, | 212 | |
129 | .dev = { | 213 | struct amba_device s5p64x0_device_pdma = { |
214 | .dev = { | ||
215 | .init_name = "dma-pl330", | ||
130 | .dma_mask = &dma_dmamask, | 216 | .dma_mask = &dma_dmamask, |
131 | .coherent_dma_mask = DMA_BIT_MASK(32), | 217 | .coherent_dma_mask = DMA_BIT_MASK(32), |
132 | }, | 218 | }, |
219 | .res = { | ||
220 | .start = S5P64X0_PA_PDMA, | ||
221 | .end = S5P64X0_PA_PDMA + SZ_4K, | ||
222 | .flags = IORESOURCE_MEM, | ||
223 | }, | ||
224 | .irq = {IRQ_DMA0, NO_IRQ}, | ||
225 | .periphid = 0x00041330, | ||
133 | }; | 226 | }; |
134 | 227 | ||
135 | static int __init s5p64x0_dma_init(void) | 228 | static int __init s5p64x0_dma_init(void) |
@@ -139,7 +232,7 @@ static int __init s5p64x0_dma_init(void) | |||
139 | else | 232 | else |
140 | s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; | 233 | s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; |
141 | 234 | ||
142 | platform_device_register(&s5p64x0_device_pdma); | 235 | amba_device_register(&s5p64x0_device_pdma, &iomem_resource); |
143 | 236 | ||
144 | return 0; | 237 | return 0; |
145 | } | 238 | } |