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-rw-r--r--arch/arm/mach-s5p64x0/cpu.c224
1 files changed, 0 insertions, 224 deletions
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
deleted file mode 100644
index f6e24f3ef760..000000000000
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/cpu.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23#include <linux/dma-mapping.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28#include <asm/proc-fns.h>
29#include <asm/irq.h>
30
31#include <mach/hardware.h>
32#include <mach/map.h>
33#include <mach/regs-clock.h>
34
35#include <plat/regs-serial.h>
36#include <plat/cpu.h>
37#include <plat/devs.h>
38#include <plat/clock.h>
39#include <plat/s5p6440.h>
40#include <plat/s5p6450.h>
41#include <plat/adc-core.h>
42#include <plat/fb-core.h>
43#include <plat/sdhci.h>
44
45/* Initial IO mappings */
46
47static struct map_desc s5p64x0_iodesc[] __initdata = {
48 {
49 .virtual = (unsigned long)S5P_VA_GPIO,
50 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
51 .length = SZ_4K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = (unsigned long)VA_VIC0,
55 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
56 .length = SZ_16K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (unsigned long)VA_VIC1,
60 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
61 .length = SZ_16K,
62 .type = MT_DEVICE,
63 },
64};
65
66static struct map_desc s5p6440_iodesc[] __initdata = {
67 {
68 .virtual = (unsigned long)S3C_VA_UART,
69 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
70 .length = SZ_4K,
71 .type = MT_DEVICE,
72 },
73};
74
75static struct map_desc s5p6450_iodesc[] __initdata = {
76 {
77 .virtual = (unsigned long)S3C_VA_UART,
78 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
79 .length = SZ_512K,
80 .type = MT_DEVICE,
81 }, {
82 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
83 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
84 .length = SZ_4K,
85 .type = MT_DEVICE,
86 },
87};
88
89static void s5p64x0_idle(void)
90{
91 unsigned long val;
92
93 if (!need_resched()) {
94 val = __raw_readl(S5P64X0_PWR_CFG);
95 val &= ~(0x3 << 5);
96 val |= (0x1 << 5);
97 __raw_writel(val, S5P64X0_PWR_CFG);
98
99 cpu_do_idle();
100 }
101 local_irq_enable();
102}
103
104/*
105 * s5p64x0_map_io
106 *
107 * register the standard CPU IO areas
108 */
109
110void __init s5p6440_map_io(void)
111{
112 /* initialize any device information early */
113 s3c_adc_setname("s3c64xx-adc");
114 s3c_fb_setname("s5p64x0-fb");
115
116 s5p64x0_default_sdhci0();
117 s5p64x0_default_sdhci1();
118 s5p6440_default_sdhci2();
119
120 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
121 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
122 init_consistent_dma_size(SZ_8M);
123}
124
125void __init s5p6450_map_io(void)
126{
127 /* initialize any device information early */
128 s3c_adc_setname("s3c64xx-adc");
129 s3c_fb_setname("s5p64x0-fb");
130
131 s5p64x0_default_sdhci0();
132 s5p64x0_default_sdhci1();
133 s5p6450_default_sdhci2();
134
135 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
136 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
137 init_consistent_dma_size(SZ_8M);
138}
139
140/*
141 * s5p64x0_init_clocks
142 *
143 * register and setup the CPU clocks
144 */
145
146void __init s5p6440_init_clocks(int xtal)
147{
148 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
149
150 s3c24xx_register_baseclocks(xtal);
151 s5p_register_clocks(xtal);
152 s5p6440_register_clocks();
153 s5p6440_setup_clocks();
154}
155
156void __init s5p6450_init_clocks(int xtal)
157{
158 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
159
160 s3c24xx_register_baseclocks(xtal);
161 s5p_register_clocks(xtal);
162 s5p6450_register_clocks();
163 s5p6450_setup_clocks();
164}
165
166/*
167 * s5p64x0_init_irq
168 *
169 * register the CPU interrupts
170 */
171
172void __init s5p6440_init_irq(void)
173{
174 /* S5P6440 supports 2 VIC */
175 u32 vic[2];
176
177 /*
178 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
179 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
180 */
181 vic[0] = 0xff800ae7;
182 vic[1] = 0xffbf23e5;
183
184 s5p_init_irq(vic, ARRAY_SIZE(vic));
185}
186
187void __init s5p6450_init_irq(void)
188{
189 /* S5P6450 supports only 2 VIC */
190 u32 vic[2];
191
192 /*
193 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
194 * VIC1 is missing IRQ VIC1[12, 14, 23]
195 */
196 vic[0] = 0xff9f1fff;
197 vic[1] = 0xff7fafff;
198
199 s5p_init_irq(vic, ARRAY_SIZE(vic));
200}
201
202struct sysdev_class s5p64x0_sysclass = {
203 .name = "s5p64x0-core",
204};
205
206static struct sys_device s5p64x0_sysdev = {
207 .cls = &s5p64x0_sysclass,
208};
209
210static int __init s5p64x0_core_init(void)
211{
212 return sysdev_class_register(&s5p64x0_sysclass);
213}
214core_initcall(s5p64x0_core_init);
215
216int __init s5p64x0_init(void)
217{
218 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
219
220 /* set idle function */
221 pm_idle = s5p64x0_idle;
222
223 return sysdev_register(&s5p64x0_sysdev);
224}
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