diff options
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock-s5p6440.c')
-rw-r--r-- | arch/arm/mach-s5p64x0/clock-s5p6440.c | 22 |
1 files changed, 6 insertions, 16 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 409c5fc3670d..9f12c2ebf416 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c | |||
@@ -133,7 +133,7 @@ static struct clksrc_clk clk_pclk_low = { | |||
133 | * recommended to keep the following clocks disabled until the driver requests | 133 | * recommended to keep the following clocks disabled until the driver requests |
134 | * for enabling the clock. | 134 | * for enabling the clock. |
135 | */ | 135 | */ |
136 | static struct clk init_clocks_disable[] = { | 136 | static struct clk init_clocks_off[] = { |
137 | { | 137 | { |
138 | .name = "nand", | 138 | .name = "nand", |
139 | .id = -1, | 139 | .id = -1, |
@@ -419,7 +419,7 @@ static struct clksrc_sources clkset_audio = { | |||
419 | static struct clksrc_clk clksrcs[] = { | 419 | static struct clksrc_clk clksrcs[] = { |
420 | { | 420 | { |
421 | .clk = { | 421 | .clk = { |
422 | .name = "mmc_bus", | 422 | .name = "sclk_mmc", |
423 | .id = 0, | 423 | .id = 0, |
424 | .ctrlbit = (1 << 24), | 424 | .ctrlbit = (1 << 24), |
425 | .enable = s5p64x0_sclk_ctrl, | 425 | .enable = s5p64x0_sclk_ctrl, |
@@ -429,7 +429,7 @@ static struct clksrc_clk clksrcs[] = { | |||
429 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, | 429 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, |
430 | }, { | 430 | }, { |
431 | .clk = { | 431 | .clk = { |
432 | .name = "mmc_bus", | 432 | .name = "sclk_mmc", |
433 | .id = 1, | 433 | .id = 1, |
434 | .ctrlbit = (1 << 25), | 434 | .ctrlbit = (1 << 25), |
435 | .enable = s5p64x0_sclk_ctrl, | 435 | .enable = s5p64x0_sclk_ctrl, |
@@ -439,7 +439,7 @@ static struct clksrc_clk clksrcs[] = { | |||
439 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, | 439 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, |
440 | }, { | 440 | }, { |
441 | .clk = { | 441 | .clk = { |
442 | .name = "mmc_bus", | 442 | .name = "sclk_mmc", |
443 | .id = 2, | 443 | .id = 2, |
444 | .ctrlbit = (1 << 26), | 444 | .ctrlbit = (1 << 26), |
445 | .enable = s5p64x0_sclk_ctrl, | 445 | .enable = s5p64x0_sclk_ctrl, |
@@ -602,8 +602,6 @@ static struct clk *clks[] __initdata = { | |||
602 | 602 | ||
603 | void __init s5p6440_register_clocks(void) | 603 | void __init s5p6440_register_clocks(void) |
604 | { | 604 | { |
605 | struct clk *clkp; | ||
606 | int ret; | ||
607 | int ptr; | 605 | int ptr; |
608 | 606 | ||
609 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | 607 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
@@ -614,16 +612,8 @@ void __init s5p6440_register_clocks(void) | |||
614 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | 612 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
615 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | 613 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
616 | 614 | ||
617 | clkp = init_clocks_disable; | 615 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
618 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | 616 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
619 | |||
620 | ret = s3c24xx_register_clock(clkp); | ||
621 | if (ret < 0) { | ||
622 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
623 | clkp->name, ret); | ||
624 | } | ||
625 | (clkp->enable)(clkp, 0); | ||
626 | } | ||
627 | 617 | ||
628 | s3c_pwmclk_init(); | 618 | s3c_pwmclk_init(); |
629 | } | 619 | } |