diff options
Diffstat (limited to 'arch/arm/mach-s5p6442/include/mach/regs-clock.h')
| -rw-r--r-- | arch/arm/mach-s5p6442/include/mach/regs-clock.h | 104 |
1 files changed, 0 insertions, 104 deletions
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h deleted file mode 100644 index 00828a336991..000000000000 --- a/arch/arm/mach-s5p6442/include/mach/regs-clock.h +++ /dev/null | |||
| @@ -1,104 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6442 - Clock register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | ||
| 14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | ||
| 15 | |||
| 16 | #include <mach/map.h> | ||
| 17 | |||
| 18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | ||
| 19 | |||
| 20 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | ||
| 21 | #define S5P_MPLL_LOCK S5P_CLKREG(0x08) | ||
| 22 | #define S5P_EPLL_LOCK S5P_CLKREG(0x10) | ||
| 23 | #define S5P_VPLL_LOCK S5P_CLKREG(0x20) | ||
| 24 | |||
| 25 | #define S5P_APLL_CON S5P_CLKREG(0x100) | ||
| 26 | #define S5P_MPLL_CON S5P_CLKREG(0x108) | ||
| 27 | #define S5P_EPLL_CON S5P_CLKREG(0x110) | ||
| 28 | #define S5P_VPLL_CON S5P_CLKREG(0x120) | ||
| 29 | |||
| 30 | #define S5P_CLK_SRC0 S5P_CLKREG(0x200) | ||
| 31 | #define S5P_CLK_SRC1 S5P_CLKREG(0x204) | ||
| 32 | #define S5P_CLK_SRC2 S5P_CLKREG(0x208) | ||
| 33 | #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) | ||
| 34 | #define S5P_CLK_SRC4 S5P_CLKREG(0x210) | ||
| 35 | #define S5P_CLK_SRC5 S5P_CLKREG(0x214) | ||
| 36 | #define S5P_CLK_SRC6 S5P_CLKREG(0x218) | ||
| 37 | |||
| 38 | #define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) | ||
| 39 | #define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) | ||
| 40 | |||
| 41 | #define S5P_CLK_DIV0 S5P_CLKREG(0x300) | ||
| 42 | #define S5P_CLK_DIV1 S5P_CLKREG(0x304) | ||
| 43 | #define S5P_CLK_DIV2 S5P_CLKREG(0x308) | ||
| 44 | #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) | ||
| 45 | #define S5P_CLK_DIV4 S5P_CLKREG(0x310) | ||
| 46 | #define S5P_CLK_DIV5 S5P_CLKREG(0x314) | ||
| 47 | #define S5P_CLK_DIV6 S5P_CLKREG(0x318) | ||
| 48 | |||
| 49 | #define S5P_CLKGATE_IP0 S5P_CLKREG(0x460) | ||
| 50 | #define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) | ||
| 51 | |||
| 52 | /* CLK_OUT */ | ||
| 53 | #define S5P_CLK_OUT_SHIFT (12) | ||
| 54 | #define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT) | ||
| 55 | #define S5P_CLK_OUT S5P_CLKREG(0x500) | ||
| 56 | |||
| 57 | #define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000) | ||
| 58 | #define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004) | ||
| 59 | |||
| 60 | #define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100) | ||
| 61 | #define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104) | ||
| 62 | |||
| 63 | #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) | ||
| 64 | |||
| 65 | /* Register Bit definition */ | ||
| 66 | #define S5P_EPLL_EN (1<<31) | ||
| 67 | #define S5P_EPLL_MASK 0xffffffff | ||
| 68 | #define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | ||
| 69 | |||
| 70 | /* CLKDIV0 */ | ||
| 71 | #define S5P_CLKDIV0_APLL_SHIFT (0) | ||
| 72 | #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) | ||
| 73 | #define S5P_CLKDIV0_A2M_SHIFT (4) | ||
| 74 | #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) | ||
| 75 | #define S5P_CLKDIV0_D0CLK_SHIFT (16) | ||
| 76 | #define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT) | ||
| 77 | #define S5P_CLKDIV0_P0CLK_SHIFT (20) | ||
| 78 | #define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT) | ||
| 79 | #define S5P_CLKDIV0_D1CLK_SHIFT (24) | ||
| 80 | #define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT) | ||
| 81 | #define S5P_CLKDIV0_P1CLK_SHIFT (28) | ||
| 82 | #define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT) | ||
| 83 | |||
| 84 | /* Clock MUX status Registers */ | ||
| 85 | #define S5P_CLK_MUX_STAT0_APLL_SHIFT (0) | ||
| 86 | #define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT) | ||
| 87 | #define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4) | ||
| 88 | #define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT) | ||
| 89 | #define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8) | ||
| 90 | #define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT) | ||
| 91 | #define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12) | ||
| 92 | #define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT) | ||
| 93 | #define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16) | ||
| 94 | #define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT) | ||
| 95 | #define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20) | ||
| 96 | #define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT) | ||
| 97 | #define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24) | ||
| 98 | #define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT) | ||
| 99 | #define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24) | ||
| 100 | #define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT) | ||
| 101 | #define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28) | ||
| 102 | #define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT) | ||
| 103 | |||
| 104 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | ||