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-rw-r--r--arch/arm/mach-s5p6440/Kconfig33
-rw-r--r--arch/arm/mach-s5p6440/Makefile25
-rw-r--r--arch/arm/mach-s5p6440/Makefile.boot2
-rw-r--r--arch/arm/mach-s5p6440/clock.c846
-rw-r--r--arch/arm/mach-s5p6440/cpu.c116
-rw-r--r--arch/arm/mach-s5p6440/dev-audio.c127
-rw-r--r--arch/arm/mach-s5p6440/dev-spi.c176
-rw-r--r--arch/arm/mach-s5p6440/dma.c105
-rw-r--r--arch/arm/mach-s5p6440/gpio.c344
-rw-r--r--arch/arm/mach-s5p6440/include/mach/debug-macro.S37
-rw-r--r--arch/arm/mach-s5p6440/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5p6440/include/mach/entry-macro.S16
-rw-r--r--arch/arm/mach-s5p6440/include/mach/gpio.h80
-rw-r--r--arch/arm/mach-s5p6440/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5p6440/include/mach/io.h18
-rw-r--r--arch/arm/mach-s5p6440/include/mach/irqs.h118
-rw-r--r--arch/arm/mach-s5p6440/include/mach/map.h86
-rw-r--r--arch/arm/mach-s5p6440/include/mach/memory.h19
-rw-r--r--arch/arm/mach-s5p6440/include/mach/pwm-clock.h70
-rw-r--r--arch/arm/mach-s5p6440/include/mach/regs-clock.h130
-rw-r--r--arch/arm/mach-s5p6440/include/mach/regs-gpio.h54
-rw-r--r--arch/arm/mach-s5p6440/include/mach/regs-irq.h19
-rw-r--r--arch/arm/mach-s5p6440/include/mach/spi-clocks.h17
-rw-r--r--arch/arm/mach-s5p6440/include/mach/system.h23
-rw-r--r--arch/arm/mach-s5p6440/include/mach/tick.h24
-rw-r--r--arch/arm/mach-s5p6440/include/mach/timex.h24
-rw-r--r--arch/arm/mach-s5p6440/include/mach/uncompress.h24
-rw-r--r--arch/arm/mach-s5p6440/include/mach/vmalloc.h17
-rw-r--r--arch/arm/mach-s5p6440/init.c52
-rw-r--r--arch/arm/mach-s5p6440/mach-smdk6440.c146
-rw-r--r--arch/arm/mach-s5p6440/setup-i2c0.c30
-rw-r--r--arch/arm/mach-s5p6440/setup-i2c1.c30
32 files changed, 0 insertions, 2852 deletions
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
deleted file mode 100644
index 6a4af7f57584..000000000000
--- a/arch/arm/mach-s5p6440/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
1# arch/arm/mach-s5p6440/Kconfig
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8if ARCH_S5P6440
9
10config CPU_S5P6440
11 bool
12 select S3C_PL330_DMA
13 help
14 Enable S5P6440 CPU support
15
16config S5P6440_SETUP_I2C1
17 bool
18 help
19 Common setup code for i2c bus 1.
20
21config MACH_SMDK6440
22 bool "SMDK6440"
23 select CPU_S5P6440
24 select S3C_DEV_I2C1
25 select S3C_DEV_RTC
26 select S3C_DEV_WDT
27 select SAMSUNG_DEV_ADC
28 select SAMSUNG_DEV_TS
29 select S5P6440_SETUP_I2C1
30 help
31 Machine support for the Samsung SMDK6440
32
33endif
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
deleted file mode 100644
index c3fe4d3662a9..000000000000
--- a/arch/arm/mach-s5p6440/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
1# arch/arm/mach-s5p6440/Makefile
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5P6440 system
14
15obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o
16obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o
17
18# machine support
19
20obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
21
22# device support
23obj-y += dev-audio.o
24obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
25obj-$(CONFIG_S5P6440_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p6440/Makefile.boot
deleted file mode 100644
index ff90aa13bd67..000000000000
--- a/arch/arm/mach-s5p6440/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
deleted file mode 100644
index ca6e48dce777..000000000000
--- a/arch/arm/mach-s5p6440/clock.c
+++ /dev/null
@@ -1,846 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/clock.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25
26#include <plat/cpu-freq.h>
27#include <mach/regs-clock.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/clock-clksrc.h>
31#include <plat/s5p-clock.h>
32#include <plat/pll.h>
33#include <plat/s5p6440.h>
34
35/* APLL Mux output clock */
36static struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45static int s5p6440_epll_enable(struct clk *clk, int enable)
46{
47 unsigned int ctrlbit = clk->ctrlbit;
48 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
49
50 if (enable)
51 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
52 else
53 __raw_writel(epll_con, S5P_EPLL_CON);
54
55 return 0;
56}
57
58static unsigned long s5p6440_epll_get_rate(struct clk *clk)
59{
60 return clk->rate;
61}
62
63static u32 epll_div[][5] = {
64 { 36000000, 0, 48, 1, 4 },
65 { 48000000, 0, 32, 1, 3 },
66 { 60000000, 0, 40, 1, 3 },
67 { 72000000, 0, 48, 1, 3 },
68 { 84000000, 0, 28, 1, 2 },
69 { 96000000, 0, 32, 1, 2 },
70 { 32768000, 45264, 43, 1, 4 },
71 { 45158000, 6903, 30, 1, 3 },
72 { 49152000, 50332, 32, 1, 3 },
73 { 67738000, 10398, 45, 1, 3 },
74 { 73728000, 9961, 49, 1, 3 }
75};
76
77static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
78{
79 unsigned int epll_con, epll_con_k;
80 unsigned int i;
81
82 if (clk->rate == rate) /* Return if nothing changed */
83 return 0;
84
85 epll_con = __raw_readl(S5P_EPLL_CON);
86 epll_con_k = __raw_readl(S5P_EPLL_CON_K);
87
88 epll_con_k &= ~(PLL90XX_KDIV_MASK);
89 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
90
91 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
92 if (epll_div[i][0] == rate) {
93 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
94 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
95 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
96 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
97 break;
98 }
99 }
100
101 if (i == ARRAY_SIZE(epll_div)) {
102 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
103 return -EINVAL;
104 }
105
106 __raw_writel(epll_con, S5P_EPLL_CON);
107 __raw_writel(epll_con_k, S5P_EPLL_CON_K);
108
109 clk->rate = rate;
110
111 return 0;
112}
113
114static struct clk_ops s5p6440_epll_ops = {
115 .get_rate = s5p6440_epll_get_rate,
116 .set_rate = s5p6440_epll_set_rate,
117};
118
119static struct clksrc_clk clk_mout_epll = {
120 .clk = {
121 .name = "mout_epll",
122 .id = -1,
123 },
124 .sources = &clk_src_epll,
125 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
126};
127
128static struct clksrc_clk clk_mout_mpll = {
129 .clk = {
130 .name = "mout_mpll",
131 .id = -1,
132 },
133 .sources = &clk_src_mpll,
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
135};
136
137enum perf_level {
138 L0 = 532*1000,
139 L1 = 266*1000,
140 L2 = 133*1000,
141};
142
143static const u32 clock_table[][3] = {
144 /*{ARM_CLK, DIVarm, DIVhclk}*/
145 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
146 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
147 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
148};
149
150static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
151{
152 unsigned long rate = clk_get_rate(clk->parent);
153 u32 clkdiv;
154
155 /* divisor mask starts at bit0, so no need to shift */
156 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
157
158 return rate / (clkdiv + 1);
159}
160
161static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
162 unsigned long rate)
163{
164 u32 iter;
165
166 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
167 if (rate > clock_table[iter][0])
168 return clock_table[iter-1][0];
169 }
170
171 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
172}
173
174static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
175{
176 u32 round_tmp;
177 u32 iter;
178 u32 clk_div0_tmp;
179 u32 cur_rate = clk->ops->get_rate(clk);
180 unsigned long flags;
181
182 round_tmp = clk->ops->round_rate(clk, rate);
183 if (round_tmp == cur_rate)
184 return 0;
185
186
187 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
188 if (round_tmp == clock_table[iter][0])
189 break;
190 }
191
192 if (iter >= ARRAY_SIZE(clock_table))
193 iter = ARRAY_SIZE(clock_table) - 1;
194
195 local_irq_save(flags);
196 if (cur_rate > round_tmp) {
197 /* Frequency Down */
198 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
199 clk_div0_tmp |= clock_table[iter][1];
200 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
201
202 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
203 ~(S5P_CLKDIV0_HCLK_MASK);
204 clk_div0_tmp |= clock_table[iter][2];
205 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
206
207
208 } else {
209 /* Frequency Up */
210 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
211 ~(S5P_CLKDIV0_HCLK_MASK);
212 clk_div0_tmp |= clock_table[iter][2];
213 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
214
215 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
216 clk_div0_tmp |= clock_table[iter][1];
217 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
218 }
219 local_irq_restore(flags);
220
221 clk->rate = clock_table[iter][0];
222
223 return 0;
224}
225
226static struct clk_ops s5p6440_clkarm_ops = {
227 .get_rate = s5p6440_armclk_get_rate,
228 .set_rate = s5p6440_armclk_set_rate,
229 .round_rate = s5p6440_armclk_round_rate,
230};
231
232static struct clksrc_clk clk_armclk = {
233 .clk = {
234 .name = "armclk",
235 .id = 1,
236 .parent = &clk_mout_apll.clk,
237 .ops = &s5p6440_clkarm_ops,
238 },
239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
240};
241
242static struct clksrc_clk clk_dout_mpll = {
243 .clk = {
244 .name = "dout_mpll",
245 .id = -1,
246 .parent = &clk_mout_mpll.clk,
247 },
248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
249};
250
251static struct clksrc_clk clk_hclk = {
252 .clk = {
253 .name = "clk_hclk",
254 .id = -1,
255 .parent = &clk_armclk.clk,
256 },
257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
258};
259
260static struct clksrc_clk clk_pclk = {
261 .clk = {
262 .name = "clk_pclk",
263 .id = -1,
264 .parent = &clk_hclk.clk,
265 },
266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
267};
268
269static struct clk *clkset_hclklow_list[] = {
270 &clk_mout_apll.clk,
271 &clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources clkset_hclklow = {
275 .sources = clkset_hclklow_list,
276 .nr_sources = ARRAY_SIZE(clkset_hclklow_list),
277};
278
279static struct clksrc_clk clk_hclk_low = {
280 .clk = {
281 .name = "hclk_low",
282 .id = -1,
283 },
284 .sources = &clkset_hclklow,
285 .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
287};
288
289static struct clksrc_clk clk_pclk_low = {
290 .clk = {
291 .name = "pclk_low",
292 .id = -1,
293 .parent = &clk_hclk_low.clk,
294 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
296};
297
298int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
299{
300 unsigned long flags;
301 u32 val;
302
303 /* can't rely on clock lock, this register has other usages */
304 local_irq_save(flags);
305
306 val = __raw_readl(S5P_OTHERS);
307 if (enable)
308 val |= S5P_OTHERS_USB_SIG_MASK;
309 else
310 val &= ~S5P_OTHERS_USB_SIG_MASK;
311
312 __raw_writel(val, S5P_OTHERS);
313
314 local_irq_restore(flags);
315
316 return 0;
317}
318
319static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
320{
321 return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
322}
323
324static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
325{
326 return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
327}
328
329static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
330{
331 return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
332}
333
334static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
335{
336 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
337}
338
339static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
340{
341 return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
342}
343
344static int s5p6440_mem_ctrl(struct clk *clk, int enable)
345{
346 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
347}
348
349/*
350 * The following clocks will be disabled during clock initialization. It is
351 * recommended to keep the following clocks disabled until the driver requests
352 * for enabling the clock.
353 */
354static struct clk init_clocks_disable[] = {
355 {
356 .name = "nand",
357 .id = -1,
358 .parent = &clk_hclk.clk,
359 .enable = s5p6440_mem_ctrl,
360 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
361 }, {
362 .name = "adc",
363 .id = -1,
364 .parent = &clk_pclk_low.clk,
365 .enable = s5p6440_pclk_ctrl,
366 .ctrlbit = S5P_CLKCON_PCLK_TSADC,
367 }, {
368 .name = "i2c",
369 .id = -1,
370 .parent = &clk_pclk_low.clk,
371 .enable = s5p6440_pclk_ctrl,
372 .ctrlbit = S5P_CLKCON_PCLK_IIC0,
373 }, {
374 .name = "i2s_v40",
375 .id = 0,
376 .parent = &clk_pclk_low.clk,
377 .enable = s5p6440_pclk_ctrl,
378 .ctrlbit = S5P_CLKCON_PCLK_IIS2,
379 }, {
380 .name = "spi",
381 .id = 0,
382 .parent = &clk_pclk_low.clk,
383 .enable = s5p6440_pclk_ctrl,
384 .ctrlbit = S5P_CLKCON_PCLK_SPI0,
385 }, {
386 .name = "spi",
387 .id = 1,
388 .parent = &clk_pclk_low.clk,
389 .enable = s5p6440_pclk_ctrl,
390 .ctrlbit = S5P_CLKCON_PCLK_SPI1,
391 }, {
392 .name = "sclk_spi_48",
393 .id = 0,
394 .parent = &clk_48m,
395 .enable = s5p6440_sclk_ctrl,
396 .ctrlbit = S5P_CLKCON_SCLK0_SPI0_48,
397 }, {
398 .name = "sclk_spi_48",
399 .id = 1,
400 .parent = &clk_48m,
401 .enable = s5p6440_sclk_ctrl,
402 .ctrlbit = S5P_CLKCON_SCLK0_SPI1_48,
403 }, {
404 .name = "mmc_48m",
405 .id = 0,
406 .parent = &clk_48m,
407 .enable = s5p6440_sclk_ctrl,
408 .ctrlbit = S5P_CLKCON_SCLK0_MMC0_48,
409 }, {
410 .name = "mmc_48m",
411 .id = 1,
412 .parent = &clk_48m,
413 .enable = s5p6440_sclk_ctrl,
414 .ctrlbit = S5P_CLKCON_SCLK0_MMC1_48,
415 }, {
416 .name = "mmc_48m",
417 .id = 2,
418 .parent = &clk_48m,
419 .enable = s5p6440_sclk_ctrl,
420 .ctrlbit = S5P_CLKCON_SCLK0_MMC2_48,
421 }, {
422 .name = "otg",
423 .id = -1,
424 .parent = &clk_hclk_low.clk,
425 .enable = s5p6440_hclk0_ctrl,
426 .ctrlbit = S5P_CLKCON_HCLK0_USB
427 }, {
428 .name = "post",
429 .id = -1,
430 .parent = &clk_hclk_low.clk,
431 .enable = s5p6440_hclk0_ctrl,
432 .ctrlbit = S5P_CLKCON_HCLK0_POST0
433 }, {
434 .name = "lcd",
435 .id = -1,
436 .parent = &clk_hclk_low.clk,
437 .enable = s5p6440_hclk1_ctrl,
438 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
439 }, {
440 .name = "hsmmc",
441 .id = 0,
442 .parent = &clk_hclk_low.clk,
443 .enable = s5p6440_hclk0_ctrl,
444 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
445 }, {
446 .name = "hsmmc",
447 .id = 1,
448 .parent = &clk_hclk_low.clk,
449 .enable = s5p6440_hclk0_ctrl,
450 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
451 }, {
452 .name = "hsmmc",
453 .id = 2,
454 .parent = &clk_hclk_low.clk,
455 .enable = s5p6440_hclk0_ctrl,
456 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
457 }, {
458 .name = "rtc",
459 .id = -1,
460 .parent = &clk_pclk_low.clk,
461 .enable = s5p6440_pclk_ctrl,
462 .ctrlbit = S5P_CLKCON_PCLK_RTC,
463 }, {
464 .name = "watchdog",
465 .id = -1,
466 .parent = &clk_pclk_low.clk,
467 .enable = s5p6440_pclk_ctrl,
468 .ctrlbit = S5P_CLKCON_PCLK_WDT,
469 }, {
470 .name = "timers",
471 .id = -1,
472 .parent = &clk_pclk_low.clk,
473 .enable = s5p6440_pclk_ctrl,
474 .ctrlbit = S5P_CLKCON_PCLK_PWM,
475 }, {
476 .name = "hclk_fimgvg",
477 .id = -1,
478 .parent = &clk_hclk.clk,
479 .enable = s5p6440_hclk1_ctrl,
480 .ctrlbit = (1 << 2),
481 }, {
482 .name = "tsi",
483 .id = -1,
484 .parent = &clk_hclk_low.clk,
485 .enable = s5p6440_hclk1_ctrl,
486 .ctrlbit = (1 << 0),
487 }, {
488 .name = "pclk_fimgvg",
489 .id = -1,
490 .parent = &clk_pclk.clk,
491 .enable = s5p6440_pclk_ctrl,
492 .ctrlbit = (1 << 31),
493 }, {
494 .name = "dmc0",
495 .id = -1,
496 .parent = &clk_pclk.clk,
497 .enable = s5p6440_pclk_ctrl,
498 .ctrlbit = (1 << 30),
499 }, {
500 .name = "etm",
501 .id = -1,
502 .parent = &clk_pclk.clk,
503 .enable = s5p6440_pclk_ctrl,
504 .ctrlbit = (1 << 29),
505 }, {
506 .name = "dsim",
507 .id = -1,
508 .parent = &clk_pclk_low.clk,
509 .enable = s5p6440_pclk_ctrl,
510 .ctrlbit = (1 << 28),
511 }, {
512 .name = "gps",
513 .id = -1,
514 .parent = &clk_pclk_low.clk,
515 .enable = s5p6440_pclk_ctrl,
516 .ctrlbit = (1 << 25),
517 }, {
518 .name = "pcm",
519 .id = -1,
520 .parent = &clk_pclk_low.clk,
521 .enable = s5p6440_pclk_ctrl,
522 .ctrlbit = (1 << 8),
523 }, {
524 .name = "irom",
525 .id = -1,
526 .parent = &clk_hclk.clk,
527 .enable = s5p6440_hclk0_ctrl,
528 .ctrlbit = (1 << 25),
529 }, {
530 .name = "dma",
531 .id = -1,
532 .parent = &clk_hclk_low.clk,
533 .enable = s5p6440_hclk0_ctrl,
534 .ctrlbit = (1 << 12),
535 }, {
536 .name = "2d",
537 .id = -1,
538 .parent = &clk_hclk.clk,
539 .enable = s5p6440_hclk0_ctrl,
540 .ctrlbit = (1 << 8),
541 },
542};
543
544/*
545 * The following clocks will be enabled during clock initialization.
546 */
547static struct clk init_clocks[] = {
548 {
549 .name = "gpio",
550 .id = -1,
551 .parent = &clk_pclk_low.clk,
552 .enable = s5p6440_pclk_ctrl,
553 .ctrlbit = S5P_CLKCON_PCLK_GPIO,
554 }, {
555 .name = "uart",
556 .id = 0,
557 .parent = &clk_pclk_low.clk,
558 .enable = s5p6440_pclk_ctrl,
559 .ctrlbit = S5P_CLKCON_PCLK_UART0,
560 }, {
561 .name = "uart",
562 .id = 1,
563 .parent = &clk_pclk_low.clk,
564 .enable = s5p6440_pclk_ctrl,
565 .ctrlbit = S5P_CLKCON_PCLK_UART1,
566 }, {
567 .name = "uart",
568 .id = 2,
569 .parent = &clk_pclk_low.clk,
570 .enable = s5p6440_pclk_ctrl,
571 .ctrlbit = S5P_CLKCON_PCLK_UART2,
572 }, {
573 .name = "uart",
574 .id = 3,
575 .parent = &clk_pclk_low.clk,
576 .enable = s5p6440_pclk_ctrl,
577 .ctrlbit = S5P_CLKCON_PCLK_UART3,
578 }, {
579 .name = "mem",
580 .id = -1,
581 .parent = &clk_hclk.clk,
582 .enable = s5p6440_hclk0_ctrl,
583 .ctrlbit = (1 << 21),
584 }, {
585 .name = "intc",
586 .id = -1,
587 .parent = &clk_hclk.clk,
588 .enable = s5p6440_hclk0_ctrl,
589 .ctrlbit = (1 << 1),
590 },
591};
592
593static struct clk clk_iis_cd_v40 = {
594 .name = "iis_cdclk_v40",
595 .id = -1,
596};
597
598static struct clk clk_pcm_cd = {
599 .name = "pcm_cdclk",
600 .id = -1,
601};
602
603static struct clk *clkset_group1_list[] = {
604 &clk_mout_epll.clk,
605 &clk_dout_mpll.clk,
606 &clk_fin_epll,
607};
608
609static struct clksrc_sources clkset_group1 = {
610 .sources = clkset_group1_list,
611 .nr_sources = ARRAY_SIZE(clkset_group1_list),
612};
613
614static struct clk *clkset_uart_list[] = {
615 &clk_mout_epll.clk,
616 &clk_dout_mpll.clk,
617};
618
619static struct clksrc_sources clkset_uart = {
620 .sources = clkset_uart_list,
621 .nr_sources = ARRAY_SIZE(clkset_uart_list),
622};
623
624static struct clk *clkset_audio_list[] = {
625 &clk_mout_epll.clk,
626 &clk_dout_mpll.clk,
627 &clk_fin_epll,
628 &clk_iis_cd_v40,
629 &clk_pcm_cd,
630};
631
632static struct clksrc_sources clkset_audio = {
633 .sources = clkset_audio_list,
634 .nr_sources = ARRAY_SIZE(clkset_audio_list),
635};
636
637static struct clksrc_clk clksrcs[] = {
638 {
639 .clk = {
640 .name = "mmc_bus",
641 .id = 0,
642 .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
643 .enable = s5p6440_sclk_ctrl,
644 },
645 .sources = &clkset_group1,
646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
648 }, {
649 .clk = {
650 .name = "mmc_bus",
651 .id = 1,
652 .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
653 .enable = s5p6440_sclk_ctrl,
654 },
655 .sources = &clkset_group1,
656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
658 }, {
659 .clk = {
660 .name = "mmc_bus",
661 .id = 2,
662 .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
663 .enable = s5p6440_sclk_ctrl,
664 },
665 .sources = &clkset_group1,
666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
668 }, {
669 .clk = {
670 .name = "uclk1",
671 .id = -1,
672 .ctrlbit = S5P_CLKCON_SCLK0_UART,
673 .enable = s5p6440_sclk_ctrl,
674 },
675 .sources = &clkset_uart,
676 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
677 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
678 }, {
679 .clk = {
680 .name = "spi_epll",
681 .id = 0,
682 .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
683 .enable = s5p6440_sclk_ctrl,
684 },
685 .sources = &clkset_group1,
686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
687 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
688 }, {
689 .clk = {
690 .name = "spi_epll",
691 .id = 1,
692 .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
693 .enable = s5p6440_sclk_ctrl,
694 },
695 .sources = &clkset_group1,
696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
697 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
698 }, {
699 .clk = {
700 .name = "sclk_post",
701 .id = -1,
702 .ctrlbit = (1 << 10),
703 .enable = s5p6440_sclk_ctrl,
704 },
705 .sources = &clkset_group1,
706 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
708 }, {
709 .clk = {
710 .name = "sclk_dispcon",
711 .id = -1,
712 .ctrlbit = (1 << 1),
713 .enable = s5p6440_sclk1_ctrl,
714 },
715 .sources = &clkset_group1,
716 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
718 }, {
719 .clk = {
720 .name = "sclk_fimgvg",
721 .id = -1,
722 .ctrlbit = (1 << 2),
723 .enable = s5p6440_sclk1_ctrl,
724 },
725 .sources = &clkset_group1,
726 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
728 }, {
729 .clk = {
730 .name = "sclk_audio2",
731 .id = -1,
732 .ctrlbit = (1 << 11),
733 .enable = s5p6440_sclk_ctrl,
734 },
735 .sources = &clkset_audio,
736 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
737 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
738 },
739};
740
741/* Clock initialisation code */
742static struct clksrc_clk *sysclks[] = {
743 &clk_mout_apll,
744 &clk_mout_epll,
745 &clk_mout_mpll,
746 &clk_dout_mpll,
747 &clk_armclk,
748 &clk_hclk,
749 &clk_pclk,
750 &clk_hclk_low,
751 &clk_pclk_low,
752};
753
754void __init_or_cpufreq s5p6440_setup_clocks(void)
755{
756 struct clk *xtal_clk;
757 unsigned long xtal;
758 unsigned long fclk;
759 unsigned long hclk;
760 unsigned long hclk_low;
761 unsigned long pclk;
762 unsigned long pclk_low;
763 unsigned long epll;
764 unsigned long apll;
765 unsigned long mpll;
766 unsigned int ptr;
767
768 /* Set S5P6440 functions for clk_fout_epll */
769 clk_fout_epll.enable = s5p6440_epll_enable;
770 clk_fout_epll.ops = &s5p6440_epll_ops;
771
772 clk_48m.enable = s5p6440_clk48m_ctrl;
773
774 xtal_clk = clk_get(NULL, "ext_xtal");
775 BUG_ON(IS_ERR(xtal_clk));
776
777 xtal = clk_get_rate(xtal_clk);
778 clk_put(xtal_clk);
779
780 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
781 __raw_readl(S5P_EPLL_CON_K));
782 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
783 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
784
785 clk_fout_mpll.rate = mpll;
786 clk_fout_epll.rate = epll;
787 clk_fout_apll.rate = apll;
788
789 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
790 " E=%ld.%ldMHz\n",
791 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
792
793 fclk = clk_get_rate(&clk_armclk.clk);
794 hclk = clk_get_rate(&clk_hclk.clk);
795 pclk = clk_get_rate(&clk_pclk.clk);
796 hclk_low = clk_get_rate(&clk_hclk_low.clk);
797 pclk_low = clk_get_rate(&clk_pclk_low.clk);
798
799 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
800 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
801 print_mhz(hclk), print_mhz(hclk_low),
802 print_mhz(pclk), print_mhz(pclk_low));
803
804 clk_f.rate = fclk;
805 clk_h.rate = hclk;
806 clk_p.rate = pclk;
807
808 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
809 s3c_set_clksrc(&clksrcs[ptr], true);
810}
811
812static struct clk *clks[] __initdata = {
813 &clk_ext,
814 &clk_iis_cd_v40,
815 &clk_pcm_cd,
816};
817
818void __init s5p6440_register_clocks(void)
819{
820 struct clk *clkp;
821 int ret;
822 int ptr;
823
824 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
825 if (ret > 0)
826 printk(KERN_ERR "Failed to register %u clocks\n", ret);
827
828 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
829 s3c_register_clksrc(sysclks[ptr], 1);
830
831 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
832 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
833
834 clkp = init_clocks_disable;
835 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
836
837 ret = s3c24xx_register_clock(clkp);
838 if (ret < 0) {
839 printk(KERN_ERR "Failed to register clock %s (%d)\n",
840 clkp->name, ret);
841 }
842 (clkp->enable)(clkp, 0);
843 }
844
845 s3c_pwmclk_init();
846}
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
deleted file mode 100644
index 526f33adb31d..000000000000
--- a/arch/arm/mach-s5p6440/cpu.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/cpu.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <asm/proc-fns.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31#include <asm/irq.h>
32
33#include <plat/regs-serial.h>
34#include <mach/regs-clock.h>
35
36#include <plat/cpu.h>
37#include <plat/devs.h>
38#include <plat/clock.h>
39#include <plat/s5p6440.h>
40#include <plat/adc-core.h>
41
42static void s5p6440_idle(void)
43{
44 unsigned long val;
45
46 if (!need_resched()) {
47 val = __raw_readl(S5P_PWR_CFG);
48 val &= ~(0x3<<5);
49 val |= (0x1<<5);
50 __raw_writel(val, S5P_PWR_CFG);
51
52 cpu_do_idle();
53 }
54 local_irq_enable();
55}
56
57/* s5p6440_map_io
58 *
59 * register the standard cpu IO areas
60*/
61
62void __init s5p6440_map_io(void)
63{
64 /* initialize any device information early */
65 s3c_adc_setname("s3c64xx-adc");
66}
67
68void __init s5p6440_init_clocks(int xtal)
69{
70 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
71
72 s3c24xx_register_baseclocks(xtal);
73 s5p_register_clocks(xtal);
74 s5p6440_register_clocks();
75 s5p6440_setup_clocks();
76}
77
78void __init s5p6440_init_irq(void)
79{
80 /* S5P6440 supports only 2 VIC */
81 u32 vic[2];
82
83 /*
84 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
85 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
86 */
87 vic[0] = 0xff800ae7;
88 vic[1] = 0xffbf23e5;
89
90 s5p_init_irq(vic, ARRAY_SIZE(vic));
91}
92
93struct sysdev_class s5p6440_sysclass = {
94 .name = "s5p6440-core",
95};
96
97static struct sys_device s5p6440_sysdev = {
98 .cls = &s5p6440_sysclass,
99};
100
101static int __init s5p6440_core_init(void)
102{
103 return sysdev_class_register(&s5p6440_sysclass);
104}
105
106core_initcall(s5p6440_core_init);
107
108int __init s5p6440_init(void)
109{
110 printk(KERN_INFO "S5P6440: Initializing architecture\n");
111
112 /* set idle function */
113 pm_idle = s5p6440_idle;
114
115 return sysdev_register(&s5p6440_sysdev);
116}
diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c
deleted file mode 100644
index 3ca0d2b8275d..000000000000
--- a/arch/arm/mach-s5p6440/dev-audio.c
+++ /dev/null
@@ -1,127 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case -1:
27 s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
29 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
30 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
31 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
32 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
33 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
34 break;
35
36 default:
37 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
38 return -EINVAL;
39 }
40
41 return 0;
42}
43
44static struct s3c_audio_pdata s3c_i2s_pdata = {
45 .cfg_gpio = s5p6440_cfg_i2s,
46};
47
48static struct resource s5p6440_iis0_resource[] = {
49 [0] = {
50 .start = S5P6440_PA_I2S,
51 .end = S5P6440_PA_I2S + 0x100 - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = DMACH_I2S0_TX,
56 .end = DMACH_I2S0_TX,
57 .flags = IORESOURCE_DMA,
58 },
59 [2] = {
60 .start = DMACH_I2S0_RX,
61 .end = DMACH_I2S0_RX,
62 .flags = IORESOURCE_DMA,
63 },
64};
65
66struct platform_device s5p6440_device_iis = {
67 .name = "s3c64xx-iis-v4",
68 .id = -1,
69 .num_resources = ARRAY_SIZE(s5p6440_iis0_resource),
70 .resource = s5p6440_iis0_resource,
71 .dev = {
72 .platform_data = &s3c_i2s_pdata,
73 },
74};
75
76/* PCM Controller platform_devices */
77
78static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
79{
80 switch (pdev->id) {
81 case 0:
82 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
83 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
84 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
85 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
86 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
87 break;
88
89 default:
90 printk(KERN_DEBUG "Invalid PCM Controller number!");
91 return -EINVAL;
92 }
93
94 return 0;
95}
96
97static struct s3c_audio_pdata s3c_pcm_pdata = {
98 .cfg_gpio = s5p6440_pcm_cfg_gpio,
99};
100
101static struct resource s5p6440_pcm0_resource[] = {
102 [0] = {
103 .start = S5P6440_PA_PCM,
104 .end = S5P6440_PA_PCM + 0x100 - 1,
105 .flags = IORESOURCE_MEM,
106 },
107 [1] = {
108 .start = DMACH_PCM0_TX,
109 .end = DMACH_PCM0_TX,
110 .flags = IORESOURCE_DMA,
111 },
112 [2] = {
113 .start = DMACH_PCM0_RX,
114 .end = DMACH_PCM0_RX,
115 .flags = IORESOURCE_DMA,
116 },
117};
118
119struct platform_device s5p6440_device_pcm = {
120 .name = "samsung-pcm",
121 .id = 0,
122 .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
123 .resource = s5p6440_pcm0_resource,
124 .dev = {
125 .platform_data = &s3c_pcm_pdata,
126 },
127};
diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c
deleted file mode 100644
index 510af44d180c..000000000000
--- a/arch/arm/mach-s5p6440/dev-spi.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5P6440_SPI_SRCCLK_PCLK] = "pclk",
25 [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
37{
38 switch (pdev->id) {
39 case 0:
40 s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
41 s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
42 s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
43 s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
44 s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
45 s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
46 break;
47
48 case 1:
49 s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
50 s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
51 s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
52 s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
53 s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
54 s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
55 break;
56
57 default:
58 dev_err(&pdev->dev, "Invalid SPI Controller number!");
59 return -EINVAL;
60 }
61
62 return 0;
63}
64
65static struct resource s5p6440_spi0_resource[] = {
66 [0] = {
67 .start = S5P6440_PA_SPI0,
68 .end = S5P6440_PA_SPI0 + 0x100 - 1,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = DMACH_SPI0_TX,
73 .end = DMACH_SPI0_TX,
74 .flags = IORESOURCE_DMA,
75 },
76 [2] = {
77 .start = DMACH_SPI0_RX,
78 .end = DMACH_SPI0_RX,
79 .flags = IORESOURCE_DMA,
80 },
81 [3] = {
82 .start = IRQ_SPI0,
83 .end = IRQ_SPI0,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
89 .cfg_gpio = s5p6440_spi_cfg_gpio,
90 .fifo_lvl_mask = 0x1ff,
91 .rx_lvl_offset = 15,
92};
93
94static u64 spi_dmamask = DMA_BIT_MASK(32);
95
96struct platform_device s5p6440_device_spi0 = {
97 .name = "s3c64xx-spi",
98 .id = 0,
99 .num_resources = ARRAY_SIZE(s5p6440_spi0_resource),
100 .resource = s5p6440_spi0_resource,
101 .dev = {
102 .dma_mask = &spi_dmamask,
103 .coherent_dma_mask = DMA_BIT_MASK(32),
104 .platform_data = &s5p6440_spi0_pdata,
105 },
106};
107
108static struct resource s5p6440_spi1_resource[] = {
109 [0] = {
110 .start = S5P6440_PA_SPI1,
111 .end = S5P6440_PA_SPI1 + 0x100 - 1,
112 .flags = IORESOURCE_MEM,
113 },
114 [1] = {
115 .start = DMACH_SPI1_TX,
116 .end = DMACH_SPI1_TX,
117 .flags = IORESOURCE_DMA,
118 },
119 [2] = {
120 .start = DMACH_SPI1_RX,
121 .end = DMACH_SPI1_RX,
122 .flags = IORESOURCE_DMA,
123 },
124 [3] = {
125 .start = IRQ_SPI1,
126 .end = IRQ_SPI1,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
132 .cfg_gpio = s5p6440_spi_cfg_gpio,
133 .fifo_lvl_mask = 0x7f,
134 .rx_lvl_offset = 15,
135};
136
137struct platform_device s5p6440_device_spi1 = {
138 .name = "s3c64xx-spi",
139 .id = 1,
140 .num_resources = ARRAY_SIZE(s5p6440_spi1_resource),
141 .resource = s5p6440_spi1_resource,
142 .dev = {
143 .dma_mask = &spi_dmamask,
144 .coherent_dma_mask = DMA_BIT_MASK(32),
145 .platform_data = &s5p6440_spi1_pdata,
146 },
147};
148
149void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
150{
151 struct s3c64xx_spi_info *pd;
152
153 /* Reject invalid configuration */
154 if (!num_cs || src_clk_nr < 0
155 || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
156 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
157 return;
158 }
159
160 switch (cntrlr) {
161 case 0:
162 pd = &s5p6440_spi0_pdata;
163 break;
164 case 1:
165 pd = &s5p6440_spi1_pdata;
166 break;
167 default:
168 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
169 __func__, cntrlr);
170 return;
171 }
172
173 pd->num_cs = num_cs;
174 pd->src_clk_nr = src_clk_nr;
175 pd->src_clk_name = spi_src_clks[src_clk_nr];
176}
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p6440/dma.c
deleted file mode 100644
index 07606ad57519..000000000000
--- a/arch/arm/mach-s5p6440/dma.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h>
27#include <mach/irqs.h>
28
29#include <plat/s3c-pl330-pdata.h>
30
31static u64 dma_dmamask = DMA_BIT_MASK(32);
32
33static struct resource s5p6440_pdma_resource[] = {
34 [0] = {
35 .start = S5P6440_PA_PDMA,
36 .end = S5P6440_PA_PDMA + SZ_4K,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_DMA0,
41 .end = IRQ_DMA0,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
47 .peri = {
48 [0] = DMACH_UART0_RX,
49 [1] = DMACH_UART0_TX,
50 [2] = DMACH_UART1_RX,
51 [3] = DMACH_UART1_TX,
52 [4] = DMACH_UART2_RX,
53 [5] = DMACH_UART2_TX,
54 [6] = DMACH_UART3_RX,
55 [7] = DMACH_UART3_TX,
56 [8] = DMACH_MAX,
57 [9] = DMACH_MAX,
58 [10] = DMACH_PCM0_TX,
59 [11] = DMACH_PCM0_RX,
60 [12] = DMACH_I2S0_TX,
61 [13] = DMACH_I2S0_RX,
62 [14] = DMACH_SPI0_TX,
63 [15] = DMACH_SPI0_RX,
64 [16] = DMACH_MAX,
65 [17] = DMACH_MAX,
66 [18] = DMACH_MAX,
67 [19] = DMACH_MAX,
68 [20] = DMACH_SPI1_TX,
69 [21] = DMACH_SPI1_RX,
70 [22] = DMACH_MAX,
71 [23] = DMACH_MAX,
72 [24] = DMACH_MAX,
73 [25] = DMACH_MAX,
74 [26] = DMACH_MAX,
75 [27] = DMACH_MAX,
76 [28] = DMACH_MAX,
77 [29] = DMACH_PWM,
78 [30] = DMACH_MAX,
79 [31] = DMACH_MAX,
80 },
81};
82
83static struct platform_device s5p6440_device_pdma = {
84 .name = "s3c-pl330",
85 .id = 1,
86 .num_resources = ARRAY_SIZE(s5p6440_pdma_resource),
87 .resource = s5p6440_pdma_resource,
88 .dev = {
89 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5p6440_pdma_pdata,
92 },
93};
94
95static struct platform_device *s5p6440_dmacs[] __initdata = {
96 &s5p6440_device_pdma,
97};
98
99static int __init s5p6440_dma_init(void)
100{
101 platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
102
103 return 0;
104}
105arch_initcall(s5p6440_dma_init);
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c
deleted file mode 100644
index 8bf6e0ce51c9..000000000000
--- a/arch/arm/mach-s5p6440/gpio.c
+++ /dev/null
@@ -1,344 +0,0 @@
1/* arch/arm/mach-s5p6440/gpio.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19#include <mach/regs-gpio.h>
20
21#include <plat/gpio-core.h>
22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h>
24
25/* GPIO bank summary:
26*
27* Bank GPIOs Style SlpCon ExtInt Group
28* A 6 4Bit Yes 1
29* B 7 4Bit Yes 1
30* C 8 4Bit Yes 2
31* F 2 2Bit Yes 4 [1]
32* G 7 4Bit Yes 5
33* H 10 4Bit[2] Yes 6
34* I 16 2Bit Yes None
35* J 12 2Bit Yes None
36* N 16 2Bit No IRQ_EINT
37* P 8 2Bit Yes 8
38* R 15 4Bit[2] Yes 8
39*
40* [1] BANKF pins 14,15 do not form part of the external interrupt sources
41* [2] BANK has two control registers, GPxCON0 and GPxCON1
42*/
43
44static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
45 unsigned int offset)
46{
47 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
48 void __iomem *base = ourchip->base;
49 void __iomem *regcon = base;
50 unsigned long con;
51 unsigned long flags;
52
53 switch (offset) {
54 case 6:
55 offset += 1;
56 case 0:
57 case 1:
58 case 2:
59 case 3:
60 case 4:
61 case 5:
62 regcon -= 4;
63 break;
64 default:
65 offset -= 7;
66 break;
67 }
68
69 s3c_gpio_lock(ourchip, flags);
70
71 con = __raw_readl(regcon);
72 con &= ~(0xf << con_4bit_shift(offset));
73 __raw_writel(con, regcon);
74
75 s3c_gpio_unlock(ourchip, flags);
76
77 return 0;
78}
79
80static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
81 unsigned int offset, int value)
82{
83 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
84 void __iomem *base = ourchip->base;
85 void __iomem *regcon = base;
86 unsigned long con;
87 unsigned long dat;
88 unsigned long flags;
89 unsigned con_offset = offset;
90
91 switch (con_offset) {
92 case 6:
93 con_offset += 1;
94 case 0:
95 case 1:
96 case 2:
97 case 3:
98 case 4:
99 case 5:
100 regcon -= 4;
101 break;
102 default:
103 con_offset -= 7;
104 break;
105 }
106
107 s3c_gpio_lock(ourchip, flags);
108
109 con = __raw_readl(regcon);
110 con &= ~(0xf << con_4bit_shift(con_offset));
111 con |= 0x1 << con_4bit_shift(con_offset);
112
113 dat = __raw_readl(base + GPIODAT_OFF);
114 if (value)
115 dat |= 1 << offset;
116 else
117 dat &= ~(1 << offset);
118
119 __raw_writel(con, regcon);
120 __raw_writel(dat, base + GPIODAT_OFF);
121
122 s3c_gpio_unlock(ourchip, flags);
123
124 return 0;
125}
126
127int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
128 unsigned int off, unsigned int cfg)
129{
130 void __iomem *reg = chip->base;
131 unsigned int shift;
132 unsigned long flags;
133 u32 con;
134
135 switch (off) {
136 case 0:
137 case 1:
138 case 2:
139 case 3:
140 case 4:
141 case 5:
142 shift = (off & 7) * 4;
143 reg -= 4;
144 break;
145 case 6:
146 shift = ((off + 1) & 7) * 4;
147 reg -= 4;
148 default:
149 shift = ((off + 1) & 7) * 4;
150 break;
151 }
152
153 if (s3c_gpio_is_cfg_special(cfg)) {
154 cfg &= 0xf;
155 cfg <<= shift;
156 }
157
158 s3c_gpio_lock(chip, flags);
159
160 con = __raw_readl(reg);
161 con &= ~(0xf << shift);
162 con |= cfg;
163 __raw_writel(con, reg);
164
165 s3c_gpio_unlock(chip, flags);
166
167 return 0;
168}
169
170static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
171 {
172 .cfg_eint = 0,
173 }, {
174 .cfg_eint = 7,
175 }, {
176 .cfg_eint = 3,
177 .set_config = s5p6440_gpio_setcfg_4bit_rbank,
178 }, {
179 .cfg_eint = 0,
180 .set_config = s3c_gpio_setcfg_s3c24xx,
181 .get_config = s3c_gpio_getcfg_s3c24xx,
182 }, {
183 .cfg_eint = 2,
184 .set_config = s3c_gpio_setcfg_s3c24xx,
185 .get_config = s3c_gpio_getcfg_s3c24xx,
186 }, {
187 .cfg_eint = 3,
188 .set_config = s3c_gpio_setcfg_s3c24xx,
189 .get_config = s3c_gpio_getcfg_s3c24xx,
190 },
191};
192
193static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
194 {
195 .base = S5P6440_GPA_BASE,
196 .config = &s5p6440_gpio_cfgs[1],
197 .chip = {
198 .base = S5P6440_GPA(0),
199 .ngpio = S5P6440_GPIO_A_NR,
200 .label = "GPA",
201 },
202 }, {
203 .base = S5P6440_GPB_BASE,
204 .config = &s5p6440_gpio_cfgs[1],
205 .chip = {
206 .base = S5P6440_GPB(0),
207 .ngpio = S5P6440_GPIO_B_NR,
208 .label = "GPB",
209 },
210 }, {
211 .base = S5P6440_GPC_BASE,
212 .config = &s5p6440_gpio_cfgs[1],
213 .chip = {
214 .base = S5P6440_GPC(0),
215 .ngpio = S5P6440_GPIO_C_NR,
216 .label = "GPC",
217 },
218 }, {
219 .base = S5P6440_GPG_BASE,
220 .config = &s5p6440_gpio_cfgs[1],
221 .chip = {
222 .base = S5P6440_GPG(0),
223 .ngpio = S5P6440_GPIO_G_NR,
224 .label = "GPG",
225 },
226 },
227};
228
229static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
230 {
231 .base = S5P6440_GPH_BASE + 0x4,
232 .config = &s5p6440_gpio_cfgs[1],
233 .chip = {
234 .base = S5P6440_GPH(0),
235 .ngpio = S5P6440_GPIO_H_NR,
236 .label = "GPH",
237 },
238 },
239};
240
241static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
242 {
243 .base = S5P6440_GPR_BASE + 0x4,
244 .config = &s5p6440_gpio_cfgs[2],
245 .chip = {
246 .base = S5P6440_GPR(0),
247 .ngpio = S5P6440_GPIO_R_NR,
248 .label = "GPR",
249 },
250 },
251};
252
253static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
254 {
255 .base = S5P6440_GPF_BASE,
256 .config = &s5p6440_gpio_cfgs[5],
257 .chip = {
258 .base = S5P6440_GPF(0),
259 .ngpio = S5P6440_GPIO_F_NR,
260 .label = "GPF",
261 },
262 }, {
263 .base = S5P6440_GPI_BASE,
264 .config = &s5p6440_gpio_cfgs[3],
265 .chip = {
266 .base = S5P6440_GPI(0),
267 .ngpio = S5P6440_GPIO_I_NR,
268 .label = "GPI",
269 },
270 }, {
271 .base = S5P6440_GPJ_BASE,
272 .config = &s5p6440_gpio_cfgs[3],
273 .chip = {
274 .base = S5P6440_GPJ(0),
275 .ngpio = S5P6440_GPIO_J_NR,
276 .label = "GPJ",
277 },
278 }, {
279 .base = S5P6440_GPN_BASE,
280 .config = &s5p6440_gpio_cfgs[4],
281 .chip = {
282 .base = S5P6440_GPN(0),
283 .ngpio = S5P6440_GPIO_N_NR,
284 .label = "GPN",
285 },
286 }, {
287 .base = S5P6440_GPP_BASE,
288 .config = &s5p6440_gpio_cfgs[5],
289 .chip = {
290 .base = S5P6440_GPP(0),
291 .ngpio = S5P6440_GPIO_P_NR,
292 .label = "GPP",
293 },
294 },
295};
296
297void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
298{
299 for (; nr_chips > 0; nr_chips--, chipcfg++) {
300 if (!chipcfg->set_config)
301 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
302 if (!chipcfg->get_config)
303 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
304 if (!chipcfg->set_pull)
305 chipcfg->set_pull = s3c_gpio_setpull_updown;
306 if (!chipcfg->get_pull)
307 chipcfg->get_pull = s3c_gpio_getpull_updown;
308 }
309}
310
311static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
312 int nr_chips)
313{
314 for (; nr_chips > 0; nr_chips--, chip++) {
315 chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
316 chip->chip.direction_output =
317 s5p6440_gpiolib_rbank_4bit2_output;
318 s3c_gpiolib_add(chip);
319 }
320}
321
322static int __init s5p6440_gpiolib_init(void)
323{
324 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
325 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
326
327 s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
328 ARRAY_SIZE(s5p6440_gpio_cfgs));
329
330 for (; nr_chips > 0; nr_chips--, chips++)
331 s3c_gpiolib_add(chips);
332
333 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
334 ARRAY_SIZE(s5p6440_gpio_4bit));
335
336 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
337 ARRAY_SIZE(s5p6440_gpio_4bit2));
338
339 s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
340 ARRAY_SIZE(gpio_rbank_4bit2));
341
342 return 0;
343}
344arch_initcall(s5p6440_gpiolib_init);
diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S
deleted file mode 100644
index 1347d7f99079..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/debug-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <mach/map.h>
14#include <plat/regs-serial.h>
15
16 /* note, for the boot process to work we have to keep the UART
17 * virtual address aligned to an 1MiB boundary for the L1
18 * mapping the head code makes. We keep the UART virtual address
19 * aligned and add in the offset when we load the value here.
20 */
21
22 .macro addruart, rx, rtmp
23 mrc p15, 0, \rx, c1, c0
24 tst \rx, #1
25 ldreq \rx, = S3C_PA_UART
26 ldrne \rx, = S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0
28 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32/* include the reset of the code which will do the work, we're only
33 * compiling for a single cpu processor type so the default of s3c2440
34 * will be fine with us.
35 */
36
37#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p6440/include/mach/dma.h
deleted file mode 100644
index 81209eb1409b..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p6440/include/mach/entry-macro.S
deleted file mode 100644
index e65f1b967262..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Low-level IRQ helper macros for the Samsung S5P6440
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <mach/map.h>
14#include <plat/irqs.h>
15
16#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h
deleted file mode 100644
index 21783834f2a2..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/gpio.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22#define S5P6440_GPIO_A_NR (6)
23#define S5P6440_GPIO_B_NR (7)
24#define S5P6440_GPIO_C_NR (8)
25#define S5P6440_GPIO_F_NR (2)
26#define S5P6440_GPIO_G_NR (7)
27#define S5P6440_GPIO_H_NR (10)
28#define S5P6440_GPIO_I_NR (16)
29#define S5P6440_GPIO_J_NR (12)
30#define S5P6440_GPIO_N_NR (16)
31#define S5P6440_GPIO_P_NR (8)
32#define S5P6440_GPIO_R_NR (15)
33
34/* GPIO bank numbers */
35
36/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
37 * space for debugging purposes so that any accidental
38 * change from one gpio bank to another can be caught.
39*/
40#define S5P6440_GPIO_NEXT(__gpio) \
41 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
42
43enum s5p_gpio_number {
44 S5P6440_GPIO_A_START = 0,
45 S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A),
46 S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B),
47 S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C),
48 S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F),
49 S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G),
50 S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H),
51 S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I),
52 S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J),
53 S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N),
54 S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P),
55};
56
57/* S5P6440 GPIO number definitions. */
58#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
59#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
60#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
61#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
62#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
63#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
64#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
65#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
66#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
67#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
68#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
69
70/* the end of the S5P6440 specific gpios */
71#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
72#define S3C_GPIO_END S5P6440_GPIO_END
73
74/* define the number of gpios we need to the one after the GPR() range */
75#define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \
76 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
77
78#include <asm-generic/gpio.h>
79
80#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p6440/include/mach/hardware.h
deleted file mode 100644
index be8b26e875db..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
deleted file mode 100644
index fa2d69cb1ad7..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-s5p6440/include/mach/io.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben-linux@fluff.org>
5 *
6 * Default IO routines for S3C64XX based
7 */
8
9#ifndef __ASM_ARM_ARCH_IO_H
10#define __ASM_ARM_ARCH_IO_H
11
12/* No current ISA/PCI bus support. */
13#define __io(a) __typesafe_io(a)
14#define __mem_pci(a) (a)
15
16#define IO_SPACE_LIMIT (0xFFFFFFFF)
17
18#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h
deleted file mode 100644
index 16a761270de1..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/irqs.h
+++ /dev/null
@@ -1,118 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h
2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_S5P_IRQS_H
14#define __ASM_ARCH_S5P_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIC1 S5P_IRQ_VIC0(5)
24#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
25#define IRQ_GPS S5P_IRQ_VIC0(7)
26#define IRQ_POST0 S5P_IRQ_VIC0(9)
27#define IRQ_2D S5P_IRQ_VIC0(11)
28#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
29#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
30#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
31#define IRQ_WDT S5P_IRQ_VIC0(26)
32#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
33#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
34#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
35#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
36#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
37
38/* VIC1 */
39
40#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
41#define IRQ_PCM0 S5P_IRQ_VIC1(2)
42#define IRQ_UART0 S5P_IRQ_VIC1(5)
43#define IRQ_UART1 S5P_IRQ_VIC1(6)
44#define IRQ_UART2 S5P_IRQ_VIC1(7)
45#define IRQ_UART3 S5P_IRQ_VIC1(8)
46#define IRQ_DMA0 S5P_IRQ_VIC1(9)
47#define IRQ_NFC S5P_IRQ_VIC1(13)
48#define IRQ_SPI0 S5P_IRQ_VIC1(16)
49#define IRQ_SPI1 S5P_IRQ_VIC1(17)
50#define IRQ_IIC S5P_IRQ_VIC1(18)
51#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
52#define IRQ_FIMGVG S5P_IRQ_VIC1(20)
53#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
54#define IRQ_PMU S5P_IRQ_VIC1(23)
55#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
56#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
57#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
58#define IRQ_OTG S5P_IRQ_VIC1(26)
59#define IRQ_DSI S5P_IRQ_VIC1(27)
60#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
61#define IRQ_TSI S5P_IRQ_VIC1(29)
62#define IRQ_PENDN S5P_IRQ_VIC1(30)
63#define IRQ_TC IRQ_PENDN
64#define IRQ_ADC S5P_IRQ_VIC1(31)
65
66/*
67 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
68 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
69 * after the pair of VICs.
70 */
71
72#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
73
74#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
75
76#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
77/*
78 * S5P6440 has 0-15 external interrupts in group 0. Only these can be used
79 * to wake up from sleep. If request is beyond this range, by mistake, a large
80 * return value for an irq number should be indication of something amiss.
81 */
82#define S5P_EINT_BASE2 (0xf0000000)
83
84/*
85 * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
86 * that they are sourced from the GPIO pins but with a different scheme for
87 * priority and source indication.
88 *
89 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
90 * interrupts, but for historical reasons they are kept apart from these
91 * next interrupts.
92 *
93 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
94 * machine specific support files.
95 */
96
97/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
98#define IRQ_EINT_GROUP1_NR (15)
99#define IRQ_EINT_GROUP2_NR (8)
100#define IRQ_EINT_GROUP5_NR (7)
101#define IRQ_EINT_GROUP6_NR (10)
102/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
103#define IRQ_EINT_GROUP8_NR (11)
104
105#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
106#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
107#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
108#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
109#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
110#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
111
112#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
113
114/* Set the default NR_IRQS */
115
116#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
117
118#endif /* __ASM_ARCH_S5P_IRQS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
deleted file mode 100644
index 6cc5cbc88ffb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/map.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P6440_PA_CHIPID (0xE0000000)
20#define S5P_PA_CHIPID S5P6440_PA_CHIPID
21
22#define S5P6440_PA_SYSCON (0xE0100000)
23#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0)
24#define S5P_PA_SYSCON S5P6440_PA_SYSCON
25
26#define S5P6440_PA_GPIO (0xE0308000)
27#define S5P_PA_GPIO S5P6440_PA_GPIO
28
29#define S5P6440_PA_VIC0 (0xE4000000)
30#define S5P_PA_VIC0 S5P6440_PA_VIC0
31
32#define S5P6440_PA_PDMA 0xE9000000
33
34#define S5P6440_PA_VIC1 (0xE4100000)
35#define S5P_PA_VIC1 S5P6440_PA_VIC1
36
37#define S5P6440_PA_TIMER (0xEA000000)
38#define S5P_PA_TIMER S5P6440_PA_TIMER
39
40#define S5P6440_PA_RTC (0xEA100000)
41
42#define S5P6440_PA_WDT (0xEA200000)
43#define S5P_PA_WDT S5P6440_PA_WDT
44
45#define S5P6440_PA_UART (0xEC000000)
46
47#define S5P_PA_UART0 (S5P6440_PA_UART + 0x0)
48#define S5P_PA_UART1 (S5P6440_PA_UART + 0x400)
49#define S5P_PA_UART2 (S5P6440_PA_UART + 0x800)
50#define S5P_PA_UART3 (S5P6440_PA_UART + 0xC00)
51
52#define S5P_SZ_UART SZ_256
53
54#define S5P6440_PA_IIC0 (0xEC104000)
55#define S5P6440_PA_IIC1 (0xEC20F000)
56
57#define S5P6440_PA_SPI0 0xEC400000
58#define S5P6440_PA_SPI1 0xEC500000
59
60#define S5P6440_PA_HSOTG (0xED100000)
61
62#define S5P6440_PA_HSMMC0 (0xED800000)
63#define S5P6440_PA_HSMMC1 (0xED900000)
64#define S5P6440_PA_HSMMC2 (0xEDA00000)
65
66#define S5P6440_PA_SDRAM (0x20000000)
67#define S5P_PA_SDRAM S5P6440_PA_SDRAM
68
69/* I2S */
70#define S5P6440_PA_I2S 0xF2000000
71
72/* PCM */
73#define S5P6440_PA_PCM 0xF2100000
74
75#define S5P6440_PA_ADC (0xF3000000)
76
77/* compatibiltiy defines. */
78#define S3C_PA_UART S5P6440_PA_UART
79#define S3C_PA_IIC S5P6440_PA_IIC0
80#define S3C_PA_RTC S5P6440_PA_RTC
81#define S3C_PA_IIC1 S5P6440_PA_IIC1
82#define S3C_PA_WDT S5P6440_PA_WDT
83
84#define SAMSUNG_PA_ADC S5P6440_PA_ADC
85
86#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p6440/include/mach/memory.h
deleted file mode 100644
index d62910c71b56..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/memory.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PHYS_OFFSET UL(0x20000000)
17#define CONSISTENT_DMA_SIZE SZ_8M
18
19#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
deleted file mode 100644
index 6a2a02fdf12a..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
12 *
13 * S5P6440 - pwm clock and timer support
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#ifndef __ASM_ARCH_PWMCLK_H
21#define __ASM_ARCH_PWMCLK_H __FILE__
22
23/**
24 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
25 * @tcfg: The timer TCFG1 register bits shifted down to 0.
26 *
27 * Return true if the given configuration from TCFG1 is a TCLK instead
28 * any of the TDIV clocks.
29 */
30static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
31{
32 return 0;
33}
34
35/**
36 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
37 * @tcfg1: The tcfg1 setting, shifted down.
38 *
39 * Get the divisor value for the given tcfg1 setting. We assume the
40 * caller has already checked to see if this is not a TCLK source.
41 */
42static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
43{
44 return 1 << tcfg1;
45}
46
47/**
48 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
49 *
50 * Return true if we have a /1 in the tdiv setting.
51 */
52static inline unsigned int pwm_tdiv_has_div1(void)
53{
54 return 1;
55}
56
57/**
58 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
59 * @div: The divisor to calculate the bit information for.
60 *
61 * Turn a divisor into the necessary bit field for TCFG1.
62 */
63static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
64{
65 return ilog2(div);
66}
67
68#define S3C_TCFG1_MUX_TCLK 0
69
70#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h
deleted file mode 100644
index c783ecc9f193..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/regs-clock.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
23#define S5P_APLL_CON S5P_CLKREG(0x0C)
24#define S5P_MPLL_CON S5P_CLKREG(0x10)
25#define S5P_EPLL_CON S5P_CLKREG(0x14)
26#define S5P_EPLL_CON_K S5P_CLKREG(0x18)
27#define S5P_CLK_SRC0 S5P_CLKREG(0x1C)
28#define S5P_CLK_DIV0 S5P_CLKREG(0x20)
29#define S5P_CLK_DIV1 S5P_CLKREG(0x24)
30#define S5P_CLK_DIV2 S5P_CLKREG(0x28)
31#define S5P_CLK_OUT S5P_CLKREG(0x2C)
32#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
33#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34)
34#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
35#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
36#define S5P_CLK_DIV3 S5P_CLKREG(0x40)
37#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
38#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
39#define S5P_AHB_CON0 S5P_CLKREG(0x100)
40#define S5P_CLK_SRC1 S5P_CLKREG(0x10C)
41#define S5P_SWRESET S5P_CLKREG(0x114)
42#define S5P_SYS_ID S5P_CLKREG(0x118)
43#define S5P_SYS_OTHERS S5P_CLKREG(0x11C)
44#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C)
45#define S5P_PWR_CFG S5P_CLKREG(0x804)
46#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
47#define S5P_NORMAL_CFG S5P_CLKREG(0x810)
48#define S5P_STOP_CFG S5P_CLKREG(0x814)
49#define S5P_SLEEP_CFG S5P_CLKREG(0x818)
50#define S5P_OSC_FREQ S5P_CLKREG(0x820)
51#define S5P_OSC_STABLE S5P_CLKREG(0x824)
52#define S5P_PWR_STABLE S5P_CLKREG(0x828)
53#define S5P_MTC_STABLE S5P_CLKREG(0x830)
54#define S5P_OTHERS S5P_CLKREG(0x900)
55#define S5P_RST_STAT S5P_CLKREG(0x904)
56#define S5P_WAKEUP_STAT S5P_CLKREG(0x908)
57#define S5P_SLPEN S5P_CLKREG(0x930)
58#define S5P_INFORM0 S5P_CLKREG(0xA00)
59#define S5P_INFORM1 S5P_CLKREG(0xA04)
60#define S5P_INFORM2 S5P_CLKREG(0xA08)
61#define S5P_INFORM3 S5P_CLKREG(0xA0C)
62
63/* CLKDIV0 */
64#define S5P_CLKDIV0_PCLK_MASK (0xf << 12)
65#define S5P_CLKDIV0_PCLK_SHIFT (12)
66#define S5P_CLKDIV0_HCLK_MASK (0xf << 8)
67#define S5P_CLKDIV0_HCLK_SHIFT (8)
68#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4)
69#define S5P_CLKDIV0_ARM_MASK (0xf << 0)
70#define S5P_CLKDIV0_ARM_SHIFT (0)
71
72/* CLKDIV3 */
73#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12)
74#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12)
75#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8)
76#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8)
77
78/* HCLK0 GATE Registers */
79#define S5P_CLKCON_HCLK0_USB (1<<20)
80#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19)
81#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18)
82#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17)
83#define S5P_CLKCON_HCLK0_POST0 (1<<5)
84
85/* HCLK1 GATE Registers */
86#define S5P_CLKCON_HCLK1_DISPCON (1<<1)
87
88/* PCLK GATE Registers */
89#define S5P_CLKCON_PCLK_IIS2 (1<<26)
90#define S5P_CLKCON_PCLK_SPI1 (1<<22)
91#define S5P_CLKCON_PCLK_SPI0 (1<<21)
92#define S5P_CLKCON_PCLK_GPIO (1<<18)
93#define S5P_CLKCON_PCLK_IIC0 (1<<17)
94#define S5P_CLKCON_PCLK_TSADC (1<<12)
95#define S5P_CLKCON_PCLK_PWM (1<<7)
96#define S5P_CLKCON_PCLK_RTC (1<<6)
97#define S5P_CLKCON_PCLK_WDT (1<<5)
98#define S5P_CLKCON_PCLK_UART3 (1<<4)
99#define S5P_CLKCON_PCLK_UART2 (1<<3)
100#define S5P_CLKCON_PCLK_UART1 (1<<2)
101#define S5P_CLKCON_PCLK_UART0 (1<<1)
102
103/* SCLK0 GATE Registers */
104#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29)
105#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28)
106#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27)
107#define S5P_CLKCON_SCLK0_MMC2 (1<<26)
108#define S5P_CLKCON_SCLK0_MMC1 (1<<25)
109#define S5P_CLKCON_SCLK0_MMC0 (1<<24)
110#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23)
111#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22)
112#define S5P_CLKCON_SCLK0_SPI1 (1<<21)
113#define S5P_CLKCON_SCLK0_SPI0 (1<<20)
114#define S5P_CLKCON_SCLK0_UART (1<<5)
115
116/* SCLK1 GATE Registers */
117
118/* MEM0 GATE Registers */
119#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2)
120
121/*OTHERS Resgister */
122#define S5P_OTHERS_USB_SIG_MASK (1<<16)
123#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6)
124
125/* Compatibility defines */
126#define ARM_CLK_DIV S5P_CLK_DIV0
127#define ARM_DIV_RATIO_SHIFT 0
128#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT)
129
130#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
deleted file mode 100644
index 82ff753913da..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - GPIO register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18/* Base addresses for each of the banks */
19#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000)
20#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020)
21#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040)
22#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0)
23#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0)
24#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0)
25#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100)
26#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120)
27#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830)
28#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160)
29#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290)
30#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900)
31#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910)
32#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914)
33#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920)
34#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
35
36/* for LCD */
37#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
38#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
39
40/* These set of macros are not really useful for the
41 * GPF/GPI/GPJ/GPN/GPP,
42 * useful for others set of GPIO's (4 bit)
43 */
44#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
45#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
46#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
47
48/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
49 * */
50#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
51#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
52#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
53
54#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p6440/include/mach/regs-irq.h
deleted file mode 100644
index a961f4beeb0c..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/regs-irq.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <asm/hardware/vic.h>
17#include <mach/map.h>
18
19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
deleted file mode 100644
index 5fbca50d1cfb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S5P6440_PLAT_SPI_CLKS_H
12#define __S5P6440_PLAT_SPI_CLKS_H __FILE__
13
14#define S5P6440_SPI_SRCCLK_PCLK 0
15#define S5P6440_SPI_SRCCLK_SCLK 1
16
17#endif /* __S5P6440_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p6440/include/mach/system.h
deleted file mode 100644
index a359ee3fa510..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/system.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16#include <plat/system-reset.h>
17
18static void arch_idle(void)
19{
20 /* nothing here yet */
21}
22
23#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p6440/include/mach/tick.h
deleted file mode 100644
index 2f25c7f07970..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/tick.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/tick.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Timer tick support definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TICK_H
14#define __ASM_ARCH_TICK_H __FILE__
15
16static inline u32 s3c24xx_ostimer_pending(void)
17{
18 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
19 return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
20}
21
22#define TICK_MAX (0xffffffff)
23
24#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/timex.h b/arch/arm/mach-s5p6440/include/mach/timex.h
deleted file mode 100644
index fb2e8cd40829..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* arch/arm/mach-s3c64xx/include/mach/timex.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C6400 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
17 * a variable is useless. It seems as long as we make our timers an
18 * exact multiple of HZ, any value that makes a 1->1 correspondence
19 * for the time conversion functions to/from jiffies is acceptable.
20*/
21
22#define CLOCK_TICK_RATE 12000000
23
24#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h
deleted file mode 100644
index 7c1f600d65c0..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22}
23
24#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p6440/include/mach/vmalloc.h
deleted file mode 100644
index e3f0eebf5205..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-s5p6440/include/mach/vmalloc.h
2 *
3 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C6400 vmalloc definition
10*/
11
12#ifndef __ASM_ARCH_VMALLOC_H
13#define __ASM_ARCH_VMALLOC_H
14
15#define VMALLOC_END 0xE0000000UL
16
17#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6440/init.c b/arch/arm/mach-s5p6440/init.c
deleted file mode 100644
index a1f3727e4021..000000000000
--- a/arch/arm/mach-s5p6440/init.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/init.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Init support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/serial_core.h>
17
18#include <plat/cpu.h>
19#include <plat/devs.h>
20#include <plat/s5p6440.h>
21#include <plat/regs-serial.h>
22
23static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = {
24 [0] = {
25 .name = "pclk_low",
26 .divisor = 1,
27 .min_baud = 0,
28 .max_baud = 0,
29 },
30 [1] = {
31 .name = "uclk1",
32 .divisor = 1,
33 .min_baud = 0,
34 .max_baud = 0,
35 },
36};
37
38/* uart registration process */
39void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
40{
41 struct s3c2410_uartcfg *tcfg = cfg;
42 u32 ucnt;
43
44 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
45 if (!tcfg->clocks) {
46 tcfg->clocks = s5p6440_serial_clocks;
47 tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks);
48 }
49 }
50
51 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
52}
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c
deleted file mode 100644
index 9202aaac3b56..000000000000
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/i2c.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/clk.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27
28#include <mach/hardware.h>
29#include <mach/map.h>
30
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <plat/regs-serial.h>
35
36#include <plat/s5p6440.h>
37#include <plat/clock.h>
38#include <mach/regs-clock.h>
39#include <plat/devs.h>
40#include <plat/cpu.h>
41#include <plat/iic.h>
42#include <plat/pll.h>
43#include <plat/adc.h>
44#include <plat/ts.h>
45
46#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
47 S3C2410_UCON_RXILEVEL | \
48 S3C2410_UCON_TXIRQMODE | \
49 S3C2410_UCON_RXIRQMODE | \
50 S3C2410_UCON_RXFIFO_TOI | \
51 S3C2443_UCON_RXERR_IRQEN)
52
53#define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8
54
55#define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
56 S3C2440_UFCON_TXTRIG16 | \
57 S3C2410_UFCON_RXTRIG8)
58
59static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
60 [0] = {
61 .hwport = 0,
62 .flags = 0,
63 .ucon = SMDK6440_UCON_DEFAULT,
64 .ulcon = SMDK6440_ULCON_DEFAULT,
65 .ufcon = SMDK6440_UFCON_DEFAULT,
66 },
67 [1] = {
68 .hwport = 1,
69 .flags = 0,
70 .ucon = SMDK6440_UCON_DEFAULT,
71 .ulcon = SMDK6440_ULCON_DEFAULT,
72 .ufcon = SMDK6440_UFCON_DEFAULT,
73 },
74 [2] = {
75 .hwport = 2,
76 .flags = 0,
77 .ucon = SMDK6440_UCON_DEFAULT,
78 .ulcon = SMDK6440_ULCON_DEFAULT,
79 .ufcon = SMDK6440_UFCON_DEFAULT,
80 },
81 [3] = {
82 .hwport = 3,
83 .flags = 0,
84 .ucon = SMDK6440_UCON_DEFAULT,
85 .ulcon = SMDK6440_ULCON_DEFAULT,
86 .ufcon = SMDK6440_UFCON_DEFAULT,
87 },
88};
89
90static struct platform_device *smdk6440_devices[] __initdata = {
91 &s5p6440_device_iis,
92 &s3c_device_adc,
93 &s3c_device_rtc,
94 &s3c_device_i2c0,
95 &s3c_device_i2c1,
96 &s3c_device_ts,
97 &s3c_device_wdt,
98};
99
100static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
101 { I2C_BOARD_INFO("24c08", 0x50), },
102};
103
104static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
105 /* To be populated */
106};
107
108static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
109 .delay = 10000,
110 .presc = 49,
111 .oversampling_shift = 2,
112};
113
114static void __init smdk6440_map_io(void)
115{
116 s5p_init_io(NULL, 0, S5P_SYS_ID);
117 s3c24xx_init_clocks(12000000);
118 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
119}
120
121static void __init smdk6440_machine_init(void)
122{
123 s3c24xx_ts_set_platdata(&s3c_ts_platform);
124
125 /* I2C */
126 s3c_i2c0_set_platdata(NULL);
127 s3c_i2c1_set_platdata(NULL);
128 i2c_register_board_info(0, smdk6440_i2c_devs0,
129 ARRAY_SIZE(smdk6440_i2c_devs0));
130 i2c_register_board_info(1, smdk6440_i2c_devs1,
131 ARRAY_SIZE(smdk6440_i2c_devs1));
132
133 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
134}
135
136MACHINE_START(SMDK6440, "SMDK6440")
137 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
138 .phys_io = S3C_PA_UART & 0xfff00000,
139 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
140 .boot_params = S5P_PA_SDRAM + 0x100,
141
142 .init_irq = s5p6440_init_irq,
143 .map_io = smdk6440_map_io,
144 .init_machine = smdk6440_machine_init,
145 .timer = &s3c24xx_timer,
146MACHINE_END
diff --git a/arch/arm/mach-s5p6440/setup-i2c0.c b/arch/arm/mach-s5p6440/setup-i2c0.c
deleted file mode 100644
index 2c99d14f7ac7..000000000000
--- a/arch/arm/mach-s5p6440/setup-i2c0.c
+++ /dev/null
@@ -1,30 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/setup-i2c0.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C0 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <linux/gpio.h>
21#include <plat/gpio-cfg.h>
22#include <plat/iic.h>
23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
27 s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
30}
diff --git a/arch/arm/mach-s5p6440/setup-i2c1.c b/arch/arm/mach-s5p6440/setup-i2c1.c
deleted file mode 100644
index 9a1537f786e0..000000000000
--- a/arch/arm/mach-s5p6440/setup-i2c1.c
+++ /dev/null
@@ -1,30 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/setup-i2c1.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C1 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <plat/gpio-cfg.h>
22#include <plat/iic.h>
23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
27 s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
29 s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
30}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 03:00:14 -0500