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-rw-r--r--arch/arm/mach-s5p6440/include/mach/map.h65
1 files changed, 13 insertions, 52 deletions
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
index 4a73e73c9428..8924e5a4d6a6 100644
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ b/arch/arm/mach-s5p6440/include/mach/map.h
@@ -14,94 +14,55 @@
14#define __ASM_ARCH_MAP_H __FILE__ 14#define __ASM_ARCH_MAP_H __FILE__
15 15
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
17 18
18/* Chip ID */
19#define S5P6440_PA_CHIPID (0xE0000000) 19#define S5P6440_PA_CHIPID (0xE0000000)
20#define S5P_PA_CHIPID S5P6440_PA_CHIPID 20#define S5P_PA_CHIPID S5P6440_PA_CHIPID
21#define S5P_VA_CHIPID S3C_ADDR(0x00700000)
22 21
23/* SYSCON */
24#define S5P6440_PA_SYSCON (0xE0100000) 22#define S5P6440_PA_SYSCON (0xE0100000)
25#define S5P_PA_SYSCON S5P6440_PA_SYSCON
26#define S5P_VA_SYSCON S3C_VA_SYS
27
28#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0) 23#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0)
29#define S5P_PA_CLK S5P6440_PA_CLK 24#define S5P_PA_SYSCON S5P6440_PA_SYSCON
30#define S5P_VA_CLK (S5P_VA_SYSCON + 0x0)
31 25
32/* GPIO */
33#define S5P6440_PA_GPIO (0xE0308000) 26#define S5P6440_PA_GPIO (0xE0308000)
34#define S5P_PA_GPIO S5P6440_PA_GPIO 27#define S5P_PA_GPIO S5P6440_PA_GPIO
35#define S5P_VA_GPIO S3C_ADDR(0x00500000)
36 28
37/* VIC0 */
38#define S5P6440_PA_VIC0 (0xE4000000) 29#define S5P6440_PA_VIC0 (0xE4000000)
39#define S5P_PA_VIC0 S5P6440_PA_VIC0 30#define S5P_PA_VIC0 S5P6440_PA_VIC0
40#define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0)
41#define VA_VIC0 S5P_VA_VIC0
42 31
43/* VIC1 */
44#define S5P6440_PA_VIC1 (0xE4100000) 32#define S5P6440_PA_VIC1 (0xE4100000)
45#define S5P_PA_VIC1 S5P6440_PA_VIC1 33#define S5P_PA_VIC1 S5P6440_PA_VIC1
46#define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000)
47#define VA_VIC1 S5P_VA_VIC1
48 34
49/* Timer */
50#define S5P6440_PA_TIMER (0xEA000000) 35#define S5P6440_PA_TIMER (0xEA000000)
51#define S5P_PA_TIMER S5P6440_PA_TIMER 36#define S5P_PA_TIMER S5P6440_PA_TIMER
52#define S5P_VA_TIMER S3C_VA_TIMER
53 37
54/* RTC */
55#define S5P6440_PA_RTC (0xEA100000) 38#define S5P6440_PA_RTC (0xEA100000)
56#define S5P_PA_RTC S5P6440_PA_RTC 39#define S5P_PA_RTC S5P6440_PA_RTC
57#define S5P_VA_RTC S3C_ADDR(0x00600000)
58 40
59/* WDT */
60#define S5P6440_PA_WDT (0xEA200000) 41#define S5P6440_PA_WDT (0xEA200000)
61#define S5P_PA_WDT S5P6440_PA_WDT 42#define S5P_PA_WDT S5P6440_PA_WDT
62#define S5p_VA_WDT S3C_VA_WATCHDOG
63 43
64/* UART */
65#define S5P6440_PA_UART (0xEC000000) 44#define S5P6440_PA_UART (0xEC000000)
66#define S5P_PA_UART S5P6440_PA_UART
67#define S5P_VA_UART S3C_VA_UART
68 45
69/* HS USB OtG */ 46#define S5P_PA_UART0 (S5P6440_PA_UART + 0x0)
47#define S5P_PA_UART1 (S5P6440_PA_UART + 0x400)
48#define S5P_PA_UART2 (S5P6440_PA_UART + 0x800)
49#define S5P_PA_UART3 (S5P6440_PA_UART + 0xC00)
50
51#define S5P_SZ_UART SZ_256
52
53#define S5P6440_PA_IIC0 (0xEC104000)
54
70#define S5P6440_PA_HSOTG (0xED100000) 55#define S5P6440_PA_HSOTG (0xED100000)
71 56
72/* HSMMC */
73#define S5P6440_PA_HSMMC0 (0xED800000) 57#define S5P6440_PA_HSMMC0 (0xED800000)
74#define S5P6440_PA_HSMMC1 (0xED900000) 58#define S5P6440_PA_HSMMC1 (0xED900000)
75#define S5P6440_PA_HSMMC2 (0xEDA00000) 59#define S5P6440_PA_HSMMC2 (0xEDA00000)
76 60
77#define S5P_PA_UART0 (S5P_PA_UART + 0x0)
78#define S5P_PA_UART1 (S5P_PA_UART + 0x400)
79#define S5P_PA_UART2 (S5P_PA_UART + 0x800)
80#define S5P_PA_UART3 (S5P_PA_UART + 0xC00)
81#define S5P_UART_OFFSET (0x400)
82
83#define S5P_VA_UARTx(x) (S5P_VA_UART + (S5P_PA_UART & 0xfffff) \
84 + ((x) * S5P_UART_OFFSET))
85
86#define S5P_VA_UART0 S5P_VA_UARTx(0)
87#define S5P_VA_UART1 S5P_VA_UARTx(1)
88#define S5P_VA_UART2 S5P_VA_UARTx(2)
89#define S5P_VA_UART3 S5P_VA_UARTx(3)
90#define S5P_SZ_UART SZ_256
91
92/* I2C */
93#define S5P6440_PA_IIC0 (0xEC104000)
94#define S5P_PA_IIC0 S5P6440_PA_IIC0
95#define S5p_VA_IIC0 S3C_ADDR(0x00700000)
96
97/* SDRAM */
98#define S5P6440_PA_SDRAM (0x20000000) 61#define S5P6440_PA_SDRAM (0x20000000)
99#define S5P_PA_SDRAM S5P6440_PA_SDRAM 62#define S5P_PA_SDRAM S5P6440_PA_SDRAM
100 63
101/* compatibiltiy defines. */ 64/* compatibiltiy defines. */
102#define S3C_PA_UART S5P_PA_UART 65#define S3C_PA_UART S5P6440_PA_UART
103#define S3C_UART_OFFSET S5P_UART_OFFSET 66#define S3C_PA_IIC S5P6440_PA_IIC0
104#define S3C_PA_TIMER S5P_PA_TIMER
105#define S3C_PA_IIC S5P_PA_IIC0
106 67
107#endif /* __ASM_ARCH_MAP_H */ 68#endif /* __ASM_ARCH_MAP_H */