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-rw-r--r--arch/arm/mach-s5p6440/clock.c350
1 files changed, 249 insertions, 101 deletions
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
index b2672e16e7aa..ca6e48dce777 100644
--- a/arch/arm/mach-s5p6440/clock.c
+++ b/arch/arm/mach-s5p6440/clock.c
@@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = {
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, 134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
135}; 135};
136 136
137static struct clk clk_h_low = {
138 .name = "hclk_low",
139 .id = -1,
140 .rate = 0,
141 .parent = NULL,
142 .ctrlbit = 0,
143 .ops = &clk_ops_def_setrate,
144};
145
146static struct clk clk_p_low = {
147 .name = "pclk_low",
148 .id = -1,
149 .rate = 0,
150 .parent = NULL,
151 .ctrlbit = 0,
152 .ops = &clk_ops_def_setrate,
153};
154
155enum perf_level { 137enum perf_level {
156 L0 = 532*1000, 138 L0 = 532*1000,
157 L1 = 266*1000, 139 L1 = 266*1000,
@@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = {
247 .round_rate = s5p6440_armclk_round_rate, 229 .round_rate = s5p6440_armclk_round_rate,
248}; 230};
249 231
250static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) 232static struct clksrc_clk clk_armclk = {
251{ 233 .clk = {
252 unsigned long rate = clk_get_rate(clk->parent); 234 .name = "armclk",
235 .id = 1,
236 .parent = &clk_mout_apll.clk,
237 .ops = &s5p6440_clkarm_ops,
238 },
239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
240};
253 241
254 if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) 242static struct clksrc_clk clk_dout_mpll = {
255 rate /= 2; 243 .clk = {
244 .name = "dout_mpll",
245 .id = -1,
246 .parent = &clk_mout_mpll.clk,
247 },
248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
249};
256 250
257 return rate; 251static struct clksrc_clk clk_hclk = {
258} 252 .clk = {
253 .name = "clk_hclk",
254 .id = -1,
255 .parent = &clk_armclk.clk,
256 },
257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
258};
259 259
260static struct clk clk_dout_mpll = { 260static struct clksrc_clk clk_pclk = {
261 .name = "dout_mpll", 261 .clk = {
262 .id = -1, 262 .name = "clk_pclk",
263 .parent = &clk_mout_mpll.clk, 263 .id = -1,
264 .ops = &(struct clk_ops) { 264 .parent = &clk_hclk.clk,
265 .get_rate = s5p6440_clk_doutmpll_get_rate,
266 }, 265 },
266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
267};
268
269static struct clk *clkset_hclklow_list[] = {
270 &clk_mout_apll.clk,
271 &clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources clkset_hclklow = {
275 .sources = clkset_hclklow_list,
276 .nr_sources = ARRAY_SIZE(clkset_hclklow_list),
277};
278
279static struct clksrc_clk clk_hclk_low = {
280 .clk = {
281 .name = "hclk_low",
282 .id = -1,
283 },
284 .sources = &clkset_hclklow,
285 .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
287};
288
289static struct clksrc_clk clk_pclk_low = {
290 .clk = {
291 .name = "pclk_low",
292 .id = -1,
293 .parent = &clk_hclk_low.clk,
294 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
267}; 296};
268 297
269int s5p6440_clk48m_ctrl(struct clk *clk, int enable) 298int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
@@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
307 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); 336 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
308} 337}
309 338
339static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
340{
341 return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
342}
343
310static int s5p6440_mem_ctrl(struct clk *clk, int enable) 344static int s5p6440_mem_ctrl(struct clk *clk, int enable)
311{ 345{
312 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); 346 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
@@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = {
321 { 355 {
322 .name = "nand", 356 .name = "nand",
323 .id = -1, 357 .id = -1,
324 .parent = &clk_h, 358 .parent = &clk_hclk.clk,
325 .enable = s5p6440_mem_ctrl, 359 .enable = s5p6440_mem_ctrl,
326 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, 360 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
327 }, { 361 }, {
328 .name = "adc", 362 .name = "adc",
329 .id = -1, 363 .id = -1,
330 .parent = &clk_p_low, 364 .parent = &clk_pclk_low.clk,
331 .enable = s5p6440_pclk_ctrl, 365 .enable = s5p6440_pclk_ctrl,
332 .ctrlbit = S5P_CLKCON_PCLK_TSADC, 366 .ctrlbit = S5P_CLKCON_PCLK_TSADC,
333 }, { 367 }, {
334 .name = "i2c", 368 .name = "i2c",
335 .id = -1, 369 .id = -1,
336 .parent = &clk_p_low, 370 .parent = &clk_pclk_low.clk,
337 .enable = s5p6440_pclk_ctrl, 371 .enable = s5p6440_pclk_ctrl,
338 .ctrlbit = S5P_CLKCON_PCLK_IIC0, 372 .ctrlbit = S5P_CLKCON_PCLK_IIC0,
339 }, { 373 }, {
340 .name = "i2s_v40", 374 .name = "i2s_v40",
341 .id = 0, 375 .id = 0,
342 .parent = &clk_p_low, 376 .parent = &clk_pclk_low.clk,
343 .enable = s5p6440_pclk_ctrl, 377 .enable = s5p6440_pclk_ctrl,
344 .ctrlbit = S5P_CLKCON_PCLK_IIS2, 378 .ctrlbit = S5P_CLKCON_PCLK_IIS2,
345 }, { 379 }, {
346 .name = "spi", 380 .name = "spi",
347 .id = 0, 381 .id = 0,
348 .parent = &clk_p_low, 382 .parent = &clk_pclk_low.clk,
349 .enable = s5p6440_pclk_ctrl, 383 .enable = s5p6440_pclk_ctrl,
350 .ctrlbit = S5P_CLKCON_PCLK_SPI0, 384 .ctrlbit = S5P_CLKCON_PCLK_SPI0,
351 }, { 385 }, {
352 .name = "spi", 386 .name = "spi",
353 .id = 1, 387 .id = 1,
354 .parent = &clk_p_low, 388 .parent = &clk_pclk_low.clk,
355 .enable = s5p6440_pclk_ctrl, 389 .enable = s5p6440_pclk_ctrl,
356 .ctrlbit = S5P_CLKCON_PCLK_SPI1, 390 .ctrlbit = S5P_CLKCON_PCLK_SPI1,
357 }, { 391 }, {
@@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = {
387 }, { 421 }, {
388 .name = "otg", 422 .name = "otg",
389 .id = -1, 423 .id = -1,
390 .parent = &clk_h_low, 424 .parent = &clk_hclk_low.clk,
391 .enable = s5p6440_hclk0_ctrl, 425 .enable = s5p6440_hclk0_ctrl,
392 .ctrlbit = S5P_CLKCON_HCLK0_USB 426 .ctrlbit = S5P_CLKCON_HCLK0_USB
393 }, { 427 }, {
394 .name = "post", 428 .name = "post",
395 .id = -1, 429 .id = -1,
396 .parent = &clk_h_low, 430 .parent = &clk_hclk_low.clk,
397 .enable = s5p6440_hclk0_ctrl, 431 .enable = s5p6440_hclk0_ctrl,
398 .ctrlbit = S5P_CLKCON_HCLK0_POST0 432 .ctrlbit = S5P_CLKCON_HCLK0_POST0
399 }, { 433 }, {
400 .name = "lcd", 434 .name = "lcd",
401 .id = -1, 435 .id = -1,
402 .parent = &clk_h_low, 436 .parent = &clk_hclk_low.clk,
403 .enable = s5p6440_hclk1_ctrl, 437 .enable = s5p6440_hclk1_ctrl,
404 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, 438 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
405 }, { 439 }, {
406 .name = "hsmmc", 440 .name = "hsmmc",
407 .id = 0, 441 .id = 0,
408 .parent = &clk_h_low, 442 .parent = &clk_hclk_low.clk,
409 .enable = s5p6440_hclk0_ctrl, 443 .enable = s5p6440_hclk0_ctrl,
410 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, 444 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
411 }, { 445 }, {
412 .name = "hsmmc", 446 .name = "hsmmc",
413 .id = 1, 447 .id = 1,
414 .parent = &clk_h_low, 448 .parent = &clk_hclk_low.clk,
415 .enable = s5p6440_hclk0_ctrl, 449 .enable = s5p6440_hclk0_ctrl,
416 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, 450 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
417 }, { 451 }, {
418 .name = "hsmmc", 452 .name = "hsmmc",
419 .id = 2, 453 .id = 2,
420 .parent = &clk_h_low, 454 .parent = &clk_hclk_low.clk,
421 .enable = s5p6440_hclk0_ctrl, 455 .enable = s5p6440_hclk0_ctrl,
422 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, 456 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
423 }, { 457 }, {
424 .name = "rtc", 458 .name = "rtc",
425 .id = -1, 459 .id = -1,
426 .parent = &clk_p_low, 460 .parent = &clk_pclk_low.clk,
427 .enable = s5p6440_pclk_ctrl, 461 .enable = s5p6440_pclk_ctrl,
428 .ctrlbit = S5P_CLKCON_PCLK_RTC, 462 .ctrlbit = S5P_CLKCON_PCLK_RTC,
429 }, { 463 }, {
430 .name = "watchdog", 464 .name = "watchdog",
431 .id = -1, 465 .id = -1,
432 .parent = &clk_p_low, 466 .parent = &clk_pclk_low.clk,
433 .enable = s5p6440_pclk_ctrl, 467 .enable = s5p6440_pclk_ctrl,
434 .ctrlbit = S5P_CLKCON_PCLK_WDT, 468 .ctrlbit = S5P_CLKCON_PCLK_WDT,
435 }, { 469 }, {
436 .name = "timers", 470 .name = "timers",
437 .id = -1, 471 .id = -1,
438 .parent = &clk_p_low, 472 .parent = &clk_pclk_low.clk,
439 .enable = s5p6440_pclk_ctrl, 473 .enable = s5p6440_pclk_ctrl,
440 .ctrlbit = S5P_CLKCON_PCLK_PWM, 474 .ctrlbit = S5P_CLKCON_PCLK_PWM,
441 } 475 }, {
476 .name = "hclk_fimgvg",
477 .id = -1,
478 .parent = &clk_hclk.clk,
479 .enable = s5p6440_hclk1_ctrl,
480 .ctrlbit = (1 << 2),
481 }, {
482 .name = "tsi",
483 .id = -1,
484 .parent = &clk_hclk_low.clk,
485 .enable = s5p6440_hclk1_ctrl,
486 .ctrlbit = (1 << 0),
487 }, {
488 .name = "pclk_fimgvg",
489 .id = -1,
490 .parent = &clk_pclk.clk,
491 .enable = s5p6440_pclk_ctrl,
492 .ctrlbit = (1 << 31),
493 }, {
494 .name = "dmc0",
495 .id = -1,
496 .parent = &clk_pclk.clk,
497 .enable = s5p6440_pclk_ctrl,
498 .ctrlbit = (1 << 30),
499 }, {
500 .name = "etm",
501 .id = -1,
502 .parent = &clk_pclk.clk,
503 .enable = s5p6440_pclk_ctrl,
504 .ctrlbit = (1 << 29),
505 }, {
506 .name = "dsim",
507 .id = -1,
508 .parent = &clk_pclk_low.clk,
509 .enable = s5p6440_pclk_ctrl,
510 .ctrlbit = (1 << 28),
511 }, {
512 .name = "gps",
513 .id = -1,
514 .parent = &clk_pclk_low.clk,
515 .enable = s5p6440_pclk_ctrl,
516 .ctrlbit = (1 << 25),
517 }, {
518 .name = "pcm",
519 .id = -1,
520 .parent = &clk_pclk_low.clk,
521 .enable = s5p6440_pclk_ctrl,
522 .ctrlbit = (1 << 8),
523 }, {
524 .name = "irom",
525 .id = -1,
526 .parent = &clk_hclk.clk,
527 .enable = s5p6440_hclk0_ctrl,
528 .ctrlbit = (1 << 25),
529 }, {
530 .name = "dma",
531 .id = -1,
532 .parent = &clk_hclk_low.clk,
533 .enable = s5p6440_hclk0_ctrl,
534 .ctrlbit = (1 << 12),
535 }, {
536 .name = "2d",
537 .id = -1,
538 .parent = &clk_hclk.clk,
539 .enable = s5p6440_hclk0_ctrl,
540 .ctrlbit = (1 << 8),
541 },
442}; 542};
443 543
444/* 544/*
@@ -448,34 +548,46 @@ static struct clk init_clocks[] = {
448 { 548 {
449 .name = "gpio", 549 .name = "gpio",
450 .id = -1, 550 .id = -1,
451 .parent = &clk_p_low, 551 .parent = &clk_pclk_low.clk,
452 .enable = s5p6440_pclk_ctrl, 552 .enable = s5p6440_pclk_ctrl,
453 .ctrlbit = S5P_CLKCON_PCLK_GPIO, 553 .ctrlbit = S5P_CLKCON_PCLK_GPIO,
454 }, { 554 }, {
455 .name = "uart", 555 .name = "uart",
456 .id = 0, 556 .id = 0,
457 .parent = &clk_p_low, 557 .parent = &clk_pclk_low.clk,
458 .enable = s5p6440_pclk_ctrl, 558 .enable = s5p6440_pclk_ctrl,
459 .ctrlbit = S5P_CLKCON_PCLK_UART0, 559 .ctrlbit = S5P_CLKCON_PCLK_UART0,
460 }, { 560 }, {
461 .name = "uart", 561 .name = "uart",
462 .id = 1, 562 .id = 1,
463 .parent = &clk_p_low, 563 .parent = &clk_pclk_low.clk,
464 .enable = s5p6440_pclk_ctrl, 564 .enable = s5p6440_pclk_ctrl,
465 .ctrlbit = S5P_CLKCON_PCLK_UART1, 565 .ctrlbit = S5P_CLKCON_PCLK_UART1,
466 }, { 566 }, {
467 .name = "uart", 567 .name = "uart",
468 .id = 2, 568 .id = 2,
469 .parent = &clk_p_low, 569 .parent = &clk_pclk_low.clk,
470 .enable = s5p6440_pclk_ctrl, 570 .enable = s5p6440_pclk_ctrl,
471 .ctrlbit = S5P_CLKCON_PCLK_UART2, 571 .ctrlbit = S5P_CLKCON_PCLK_UART2,
472 }, { 572 }, {
473 .name = "uart", 573 .name = "uart",
474 .id = 3, 574 .id = 3,
475 .parent = &clk_p_low, 575 .parent = &clk_pclk_low.clk,
476 .enable = s5p6440_pclk_ctrl, 576 .enable = s5p6440_pclk_ctrl,
477 .ctrlbit = S5P_CLKCON_PCLK_UART3, 577 .ctrlbit = S5P_CLKCON_PCLK_UART3,
478 } 578 }, {
579 .name = "mem",
580 .id = -1,
581 .parent = &clk_hclk.clk,
582 .enable = s5p6440_hclk0_ctrl,
583 .ctrlbit = (1 << 21),
584 }, {
585 .name = "intc",
586 .id = -1,
587 .parent = &clk_hclk.clk,
588 .enable = s5p6440_hclk0_ctrl,
589 .ctrlbit = (1 << 1),
590 },
479}; 591};
480 592
481static struct clk clk_iis_cd_v40 = { 593static struct clk clk_iis_cd_v40 = {
@@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = {
488 .id = -1, 600 .id = -1,
489}; 601};
490 602
491static struct clk *clkset_spi_mmc_list[] = { 603static struct clk *clkset_group1_list[] = {
492 &clk_mout_epll.clk, 604 &clk_mout_epll.clk,
493 &clk_dout_mpll, 605 &clk_dout_mpll.clk,
494 &clk_fin_epll, 606 &clk_fin_epll,
495}; 607};
496 608
497static struct clksrc_sources clkset_spi_mmc = { 609static struct clksrc_sources clkset_group1 = {
498 .sources = clkset_spi_mmc_list, 610 .sources = clkset_group1_list,
499 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), 611 .nr_sources = ARRAY_SIZE(clkset_group1_list),
500}; 612};
501 613
502static struct clk *clkset_uart_list[] = { 614static struct clk *clkset_uart_list[] = {
503 &clk_mout_epll.clk, 615 &clk_mout_epll.clk,
504 &clk_dout_mpll 616 &clk_dout_mpll.clk,
505}; 617};
506 618
507static struct clksrc_sources clkset_uart = { 619static struct clksrc_sources clkset_uart = {
@@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = {
509 .nr_sources = ARRAY_SIZE(clkset_uart_list), 621 .nr_sources = ARRAY_SIZE(clkset_uart_list),
510}; 622};
511 623
624static struct clk *clkset_audio_list[] = {
625 &clk_mout_epll.clk,
626 &clk_dout_mpll.clk,
627 &clk_fin_epll,
628 &clk_iis_cd_v40,
629 &clk_pcm_cd,
630};
631
632static struct clksrc_sources clkset_audio = {
633 .sources = clkset_audio_list,
634 .nr_sources = ARRAY_SIZE(clkset_audio_list),
635};
636
512static struct clksrc_clk clksrcs[] = { 637static struct clksrc_clk clksrcs[] = {
513 { 638 {
514 .clk = { 639 .clk = {
@@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = {
517 .ctrlbit = S5P_CLKCON_SCLK0_MMC0, 642 .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
518 .enable = s5p6440_sclk_ctrl, 643 .enable = s5p6440_sclk_ctrl,
519 }, 644 },
520 .sources = &clkset_spi_mmc, 645 .sources = &clkset_group1,
521 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, 646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
522 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, 647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
523 }, { 648 }, {
@@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = {
527 .ctrlbit = S5P_CLKCON_SCLK0_MMC1, 652 .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
528 .enable = s5p6440_sclk_ctrl, 653 .enable = s5p6440_sclk_ctrl,
529 }, 654 },
530 .sources = &clkset_spi_mmc, 655 .sources = &clkset_group1,
531 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, 656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
532 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, 657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
533 }, { 658 }, {
@@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = {
537 .ctrlbit = S5P_CLKCON_SCLK0_MMC2, 662 .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
538 .enable = s5p6440_sclk_ctrl, 663 .enable = s5p6440_sclk_ctrl,
539 }, 664 },
540 .sources = &clkset_spi_mmc, 665 .sources = &clkset_group1,
541 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, 666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
542 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, 667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
543 }, { 668 }, {
@@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = {
557 .ctrlbit = S5P_CLKCON_SCLK0_SPI0, 682 .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
558 .enable = s5p6440_sclk_ctrl, 683 .enable = s5p6440_sclk_ctrl,
559 }, 684 },
560 .sources = &clkset_spi_mmc, 685 .sources = &clkset_group1,
561 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, 686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
562 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, 687 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
563 }, { 688 }, {
@@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = {
567 .ctrlbit = S5P_CLKCON_SCLK0_SPI1, 692 .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
568 .enable = s5p6440_sclk_ctrl, 693 .enable = s5p6440_sclk_ctrl,
569 }, 694 },
570 .sources = &clkset_spi_mmc, 695 .sources = &clkset_group1,
571 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, 696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
572 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, 697 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
573 } 698 }, {
699 .clk = {
700 .name = "sclk_post",
701 .id = -1,
702 .ctrlbit = (1 << 10),
703 .enable = s5p6440_sclk_ctrl,
704 },
705 .sources = &clkset_group1,
706 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
708 }, {
709 .clk = {
710 .name = "sclk_dispcon",
711 .id = -1,
712 .ctrlbit = (1 << 1),
713 .enable = s5p6440_sclk1_ctrl,
714 },
715 .sources = &clkset_group1,
716 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
718 }, {
719 .clk = {
720 .name = "sclk_fimgvg",
721 .id = -1,
722 .ctrlbit = (1 << 2),
723 .enable = s5p6440_sclk1_ctrl,
724 },
725 .sources = &clkset_group1,
726 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
728 }, {
729 .clk = {
730 .name = "sclk_audio2",
731 .id = -1,
732 .ctrlbit = (1 << 11),
733 .enable = s5p6440_sclk_ctrl,
734 },
735 .sources = &clkset_audio,
736 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
737 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
738 },
574}; 739};
575 740
576/* Clock initialisation code */ 741/* Clock initialisation code */
577static struct clksrc_clk *init_parents[] = { 742static struct clksrc_clk *sysclks[] = {
578 &clk_mout_apll, 743 &clk_mout_apll,
579 &clk_mout_epll, 744 &clk_mout_epll,
580 &clk_mout_mpll, 745 &clk_mout_mpll,
746 &clk_dout_mpll,
747 &clk_armclk,
748 &clk_hclk,
749 &clk_pclk,
750 &clk_hclk_low,
751 &clk_pclk_low,
581}; 752};
582 753
583void __init_or_cpufreq s5p6440_setup_clocks(void) 754void __init_or_cpufreq s5p6440_setup_clocks(void)
@@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
593 unsigned long apll; 764 unsigned long apll;
594 unsigned long mpll; 765 unsigned long mpll;
595 unsigned int ptr; 766 unsigned int ptr;
596 u32 clkdiv0;
597 u32 clkdiv3;
598 767
599 /* Set S5P6440 functions for clk_fout_epll */ 768 /* Set S5P6440 functions for clk_fout_epll */
600 clk_fout_epll.enable = s5p6440_epll_enable; 769 clk_fout_epll.enable = s5p6440_epll_enable;
601 clk_fout_epll.ops = &s5p6440_epll_ops; 770 clk_fout_epll.ops = &s5p6440_epll_ops;
602 771
603 /* Set S5P6440 functions for arm clock */
604 clk_arm.parent = &clk_mout_apll.clk;
605 clk_arm.ops = &s5p6440_clkarm_ops;
606 clk_48m.enable = s5p6440_clk48m_ctrl; 772 clk_48m.enable = s5p6440_clk48m_ctrl;
607 773
608 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
609 clkdiv3 = __raw_readl(S5P_CLK_DIV3);
610
611 xtal_clk = clk_get(NULL, "ext_xtal"); 774 xtal_clk = clk_get(NULL, "ext_xtal");
612 BUG_ON(IS_ERR(xtal_clk)); 775 BUG_ON(IS_ERR(xtal_clk));
613 776
@@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
619 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); 782 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
620 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); 783 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
621 784
785 clk_fout_mpll.rate = mpll;
786 clk_fout_epll.rate = epll;
787 clk_fout_apll.rate = apll;
788
622 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ 789 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
623 " E=%ld.%ldMHz\n", 790 " E=%ld.%ldMHz\n",
624 print_mhz(apll), print_mhz(mpll), print_mhz(epll)); 791 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
625 792
626 fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); 793 fclk = clk_get_rate(&clk_armclk.clk);
627 hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); 794 hclk = clk_get_rate(&clk_hclk.clk);
628 pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); 795 pclk = clk_get_rate(&clk_pclk.clk);
629 796 hclk_low = clk_get_rate(&clk_hclk_low.clk);
630 if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { 797 pclk_low = clk_get_rate(&clk_pclk_low.clk);
631 /* Asynchronous mode */
632 hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
633 } else {
634 /* Synchronous mode */
635 hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
636 }
637
638 pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
639 798
640 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ 799 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
641 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", 800 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
642 print_mhz(hclk), print_mhz(hclk_low), 801 print_mhz(hclk), print_mhz(hclk_low),
643 print_mhz(pclk), print_mhz(pclk_low)); 802 print_mhz(pclk), print_mhz(pclk_low));
644 803
645 clk_fout_mpll.rate = mpll;
646 clk_fout_epll.rate = epll;
647 clk_fout_apll.rate = apll;
648
649 clk_f.rate = fclk; 804 clk_f.rate = fclk;
650 clk_h.rate = hclk; 805 clk_h.rate = hclk;
651 clk_p.rate = pclk; 806 clk_p.rate = pclk;
652 clk_h_low.rate = hclk_low;
653 clk_p_low.rate = pclk_low;
654
655 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
656 s3c_set_clksrc(init_parents[ptr], true);
657 807
658 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 808 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
659 s3c_set_clksrc(&clksrcs[ptr], true); 809 s3c_set_clksrc(&clksrcs[ptr], true);
@@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
661 811
662static struct clk *clks[] __initdata = { 812static struct clk *clks[] __initdata = {
663 &clk_ext, 813 &clk_ext,
664 &clk_mout_epll.clk,
665 &clk_mout_mpll.clk,
666 &clk_dout_mpll,
667 &clk_iis_cd_v40, 814 &clk_iis_cd_v40,
668 &clk_pcm_cd, 815 &clk_pcm_cd,
669 &clk_p_low,
670 &clk_h_low,
671}; 816};
672 817
673void __init s5p6440_register_clocks(void) 818void __init s5p6440_register_clocks(void)
@@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void)
680 if (ret > 0) 825 if (ret > 0)
681 printk(KERN_ERR "Failed to register %u clocks\n", ret); 826 printk(KERN_ERR "Failed to register %u clocks\n", ret);
682 827
828 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
829 s3c_register_clksrc(sysclks[ptr], 1);
830
683 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 831 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
684 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 832 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
685 833