diff options
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r-- | arch/arm/mach-s3c64xx/clock.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/dma.c | 11 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/gpiolib.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/mach-smdk6410.c | 13 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/setup-keypad.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/setup-sdhci.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/sleep.S | 63 |
7 files changed, 27 insertions, 74 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index dd3782064508..fdfc4d5e37a1 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c | |||
@@ -151,6 +151,12 @@ static struct clk init_clocks_off[] = { | |||
151 | .enable = s3c64xx_pclk_ctrl, | 151 | .enable = s3c64xx_pclk_ctrl, |
152 | .ctrlbit = S3C_CLKCON_PCLK_IIC, | 152 | .ctrlbit = S3C_CLKCON_PCLK_IIC, |
153 | }, { | 153 | }, { |
154 | .name = "i2c", | ||
155 | .id = 1, | ||
156 | .parent = &clk_p, | ||
157 | .enable = s3c64xx_pclk_ctrl, | ||
158 | .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, | ||
159 | }, { | ||
154 | .name = "iis", | 160 | .name = "iis", |
155 | .id = 0, | 161 | .id = 0, |
156 | .parent = &clk_p, | 162 | .parent = &clk_p, |
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 135db1b41252..c35585cf8c4f 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c | |||
@@ -690,12 +690,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, | |||
690 | 690 | ||
691 | regptr = regs + PL080_Cx_BASE(0); | 691 | regptr = regs + PL080_Cx_BASE(0); |
692 | 692 | ||
693 | for (ch = 0; ch < 8; ch++, chno++, chptr++) { | 693 | for (ch = 0; ch < 8; ch++, chptr++) { |
694 | printk(KERN_INFO "%s: registering DMA %d (%p)\n", | 694 | pr_debug("%s: registering DMA %d (%p)\n", |
695 | __func__, chno, regptr); | 695 | __func__, chno + ch, regptr); |
696 | 696 | ||
697 | chptr->bit = 1 << ch; | 697 | chptr->bit = 1 << ch; |
698 | chptr->number = chno; | 698 | chptr->number = chno + ch; |
699 | chptr->dmac = dmac; | 699 | chptr->dmac = dmac; |
700 | chptr->regs = regptr; | 700 | chptr->regs = regptr; |
701 | regptr += PL080_Cx_STRIDE; | 701 | regptr += PL080_Cx_STRIDE; |
@@ -704,7 +704,8 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, | |||
704 | /* for the moment, permanently enable the controller */ | 704 | /* for the moment, permanently enable the controller */ |
705 | writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG); | 705 | writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG); |
706 | 706 | ||
707 | printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs); | 707 | printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n", |
708 | irq, regs, chno, chno+8); | ||
708 | 709 | ||
709 | return 0; | 710 | return 0; |
710 | 711 | ||
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c index fd99a82e82c4..92b09085caaa 100644 --- a/arch/arm/mach-s3c64xx/gpiolib.c +++ b/arch/arm/mach-s3c64xx/gpiolib.c | |||
@@ -72,7 +72,7 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { | |||
72 | .get_pull = s3c_gpio_getpull_updown, | 72 | .get_pull = s3c_gpio_getpull_updown, |
73 | }; | 73 | }; |
74 | 74 | ||
75 | int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin) | 75 | static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin) |
76 | { | 76 | { |
77 | return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; | 77 | return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; |
78 | } | 78 | } |
@@ -138,7 +138,7 @@ static struct s3c_gpio_chip gpio_4bit[] = { | |||
138 | }, | 138 | }, |
139 | }; | 139 | }; |
140 | 140 | ||
141 | int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin) | 141 | static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin) |
142 | { | 142 | { |
143 | return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; | 143 | return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; |
144 | } | 144 | } |
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index e85192a86fbe..a80a3163dd30 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/delay.h> | 28 | #include <linux/delay.h> |
29 | #include <linux/smsc911x.h> | 29 | #include <linux/smsc911x.h> |
30 | #include <linux/regulator/fixed.h> | 30 | #include <linux/regulator/fixed.h> |
31 | #include <linux/regulator/machine.h> | ||
31 | 32 | ||
32 | #ifdef CONFIG_SMDK6410_WM1190_EV1 | 33 | #ifdef CONFIG_SMDK6410_WM1190_EV1 |
33 | #include <linux/mfd/wm8350/core.h> | 34 | #include <linux/mfd/wm8350/core.h> |
@@ -351,7 +352,7 @@ static struct regulator_init_data smdk6410_vddpll = { | |||
351 | /* VDD_UH_MMC, LDO5 on J5 */ | 352 | /* VDD_UH_MMC, LDO5 on J5 */ |
352 | static struct regulator_init_data smdk6410_vdduh_mmc = { | 353 | static struct regulator_init_data smdk6410_vdduh_mmc = { |
353 | .constraints = { | 354 | .constraints = { |
354 | .name = "PVDD_UH/PVDD_MMC", | 355 | .name = "PVDD_UH+PVDD_MMC", |
355 | .always_on = 1, | 356 | .always_on = 1, |
356 | }, | 357 | }, |
357 | }; | 358 | }; |
@@ -417,7 +418,7 @@ static struct regulator_init_data smdk6410_vddaudio = { | |||
417 | /* S3C64xx internal logic & PLL */ | 418 | /* S3C64xx internal logic & PLL */ |
418 | static struct regulator_init_data wm8350_dcdc1_data = { | 419 | static struct regulator_init_data wm8350_dcdc1_data = { |
419 | .constraints = { | 420 | .constraints = { |
420 | .name = "PVDD_INT/PVDD_PLL", | 421 | .name = "PVDD_INT+PVDD_PLL", |
421 | .min_uV = 1200000, | 422 | .min_uV = 1200000, |
422 | .max_uV = 1200000, | 423 | .max_uV = 1200000, |
423 | .always_on = 1, | 424 | .always_on = 1, |
@@ -452,7 +453,7 @@ static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { | |||
452 | 453 | ||
453 | static struct regulator_init_data wm8350_dcdc4_data = { | 454 | static struct regulator_init_data wm8350_dcdc4_data = { |
454 | .constraints = { | 455 | .constraints = { |
455 | .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV", | 456 | .name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV", |
456 | .min_uV = 3000000, | 457 | .min_uV = 3000000, |
457 | .max_uV = 3000000, | 458 | .max_uV = 3000000, |
458 | .always_on = 1, | 459 | .always_on = 1, |
@@ -464,7 +465,7 @@ static struct regulator_init_data wm8350_dcdc4_data = { | |||
464 | /* OTGi/1190-EV1 HPVDD & AVDD */ | 465 | /* OTGi/1190-EV1 HPVDD & AVDD */ |
465 | static struct regulator_init_data wm8350_ldo4_data = { | 466 | static struct regulator_init_data wm8350_ldo4_data = { |
466 | .constraints = { | 467 | .constraints = { |
467 | .name = "PVDD_OTGI/HPVDD/AVDD", | 468 | .name = "PVDD_OTGI+HPVDD+AVDD", |
468 | .min_uV = 1200000, | 469 | .min_uV = 1200000, |
469 | .max_uV = 1200000, | 470 | .max_uV = 1200000, |
470 | .apply_uV = 1, | 471 | .apply_uV = 1, |
@@ -552,7 +553,7 @@ static struct wm831x_backlight_pdata wm1192_backlight_pdata = { | |||
552 | 553 | ||
553 | static struct regulator_init_data wm1192_dcdc3 = { | 554 | static struct regulator_init_data wm1192_dcdc3 = { |
554 | .constraints = { | 555 | .constraints = { |
555 | .name = "PVDD_MEM/PVDD_GPS", | 556 | .name = "PVDD_MEM+PVDD_GPS", |
556 | .always_on = 1, | 557 | .always_on = 1, |
557 | }, | 558 | }, |
558 | }; | 559 | }; |
@@ -563,7 +564,7 @@ static struct regulator_consumer_supply wm1192_ldo1_consumers[] = { | |||
563 | 564 | ||
564 | static struct regulator_init_data wm1192_ldo1 = { | 565 | static struct regulator_init_data wm1192_ldo1 = { |
565 | .constraints = { | 566 | .constraints = { |
566 | .name = "PVDD_LCD/PVDD_EXT", | 567 | .name = "PVDD_LCD+PVDD_EXT", |
567 | .always_on = 1, | 568 | .always_on = 1, |
568 | }, | 569 | }, |
569 | .consumer_supplies = wm1192_ldo1_consumers, | 570 | .consumer_supplies = wm1192_ldo1_consumers, |
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c index f8ed0d22db70..1d4d0ee9e870 100644 --- a/arch/arm/mach-s3c64xx/setup-keypad.c +++ b/arch/arm/mach-s3c64xx/setup-keypad.c | |||
@@ -17,7 +17,7 @@ | |||
17 | void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) | 17 | void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) |
18 | { | 18 | { |
19 | /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */ | 19 | /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */ |
20 | s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3)); | 20 | s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), rows, S3C_GPIO_SFN(3)); |
21 | 21 | ||
22 | /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */ | 22 | /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */ |
23 | s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3)); | 23 | s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3)); |
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c index 1a942037c4ef..f344a222bc84 100644 --- a/arch/arm/mach-s3c64xx/setup-sdhci.c +++ b/arch/arm/mach-s3c64xx/setup-sdhci.c | |||
@@ -56,7 +56,7 @@ void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, | |||
56 | else | 56 | else |
57 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | 57 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); |
58 | 58 | ||
59 | printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); | 59 | pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); |
60 | writel(ctrl2, r + S3C_SDHCI_CONTROL2); | 60 | writel(ctrl2, r + S3C_SDHCI_CONTROL2); |
61 | writel(ctrl3, r + S3C_SDHCI_CONTROL3); | 61 | writel(ctrl3, r + S3C_SDHCI_CONTROL3); |
62 | } | 62 | } |
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S index b2ef44317368..afe5a762f46e 100644 --- a/arch/arm/mach-s3c64xx/sleep.S +++ b/arch/arm/mach-s3c64xx/sleep.S | |||
@@ -32,25 +32,13 @@ | |||
32 | * code after resume. | 32 | * code after resume. |
33 | * | 33 | * |
34 | * entry: | 34 | * entry: |
35 | * r0 = pointer to the save block | 35 | * r1 = v:p offset |
36 | */ | 36 | */ |
37 | 37 | ||
38 | ENTRY(s3c_cpu_save) | 38 | ENTRY(s3c_cpu_save) |
39 | stmfd sp!, { r4 - r12, lr } | 39 | stmfd sp!, { r4 - r12, lr } |
40 | 40 | ldr r3, =resume_with_mmu | |
41 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID | 41 | bl cpu_suspend |
42 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID | ||
43 | mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 | ||
44 | mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 | ||
45 | mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control | ||
46 | mrc p15, 0, r9, c1, c0, 0 @ Control register | ||
47 | mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register | ||
48 | mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls | ||
49 | |||
50 | stmia r0, { r4 - r13 } @ Save CP registers and SP | ||
51 | |||
52 | @@ save our state to ram | ||
53 | bl s3c_pm_cb_flushcache | ||
54 | 42 | ||
55 | @@ call final suspend code | 43 | @@ call final suspend code |
56 | ldr r0, =pm_cpu_sleep | 44 | ldr r0, =pm_cpu_sleep |
@@ -61,18 +49,6 @@ ENTRY(s3c_cpu_save) | |||
61 | resume_with_mmu: | 49 | resume_with_mmu: |
62 | ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save | 50 | ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save |
63 | 51 | ||
64 | .data | ||
65 | |||
66 | /* the next bit is code, but it requires easy access to the | ||
67 | * s3c_sleep_save_phys data before the MMU is switched on, so | ||
68 | * we store the code that needs this variable in the .data where | ||
69 | * the value can be written to (the .text segment is RO). | ||
70 | */ | ||
71 | |||
72 | .global s3c_sleep_save_phys | ||
73 | s3c_sleep_save_phys: | ||
74 | .word 0 | ||
75 | |||
76 | /* Sleep magic, the word before the resume entry point so that the | 52 | /* Sleep magic, the word before the resume entry point so that the |
77 | * bootloader can check for a resumeable image. */ | 53 | * bootloader can check for a resumeable image. */ |
78 | 54 | ||
@@ -110,35 +86,4 @@ ENTRY(s3c_cpu_resume) | |||
110 | orr r0, r0, #1 << 15 @ GPN15 | 86 | orr r0, r0, #1 << 15 @ GPN15 |
111 | str r0, [ r3, #S3C64XX_GPNDAT ] | 87 | str r0, [ r3, #S3C64XX_GPNDAT ] |
112 | #endif | 88 | #endif |
113 | 89 | b cpu_resume | |
114 | /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches | ||
115 | * are thoroughly cleaned just in case the bootloader didn't do it | ||
116 | * for us. */ | ||
117 | mov r0, #0 | ||
118 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | ||
119 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | ||
120 | mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache | ||
121 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
122 | @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs | ||
123 | @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches | ||
124 | |||
125 | ldr r0, s3c_sleep_save_phys | ||
126 | ldmia r0, { r4 - r13 } | ||
127 | |||
128 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID | ||
129 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID | ||
130 | mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 | ||
131 | mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 | ||
132 | mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control | ||
133 | mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register | ||
134 | |||
135 | mov r0, #0 @ restore copro access controls | ||
136 | mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls | ||
137 | mcr p15, 0, r0, c7, c5, 4 | ||
138 | |||
139 | ldr r2, =resume_with_mmu | ||
140 | mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ | ||
141 | nop | ||
142 | mov pc, r2 /* jump back */ | ||
143 | |||
144 | .end | ||