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-rw-r--r--arch/arm/mach-s3c64xx/Kconfig15
-rw-r--r--arch/arm/mach-s3c64xx/Makefile2
-rw-r--r--arch/arm/mach-s3c64xx/clock.c243
-rw-r--r--arch/arm/mach-s3c64xx/common.c18
-rw-r--r--arch/arm/mach-s3c64xx/common.h1
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c180
-rw-r--r--arch/arm/mach-s3c64xx/dma.c23
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/crag6410.h6
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio.h2
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410-module.c56
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c47
-rw-r--r--arch/arm/mach-s3c64xx/pm.c189
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c15
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c15
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci.c24
-rw-r--r--arch/arm/mach-s3c64xx/setup-spi.c45
18 files changed, 536 insertions, 349 deletions
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 5552e048c2be..dd20c66cd700 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,6 +8,7 @@ config PLAT_S3C64XX
8 bool 8 bool
9 depends on ARCH_S3C64XX 9 depends on ARCH_S3C64XX
10 select SAMSUNG_WAKEMASK 10 select SAMSUNG_WAKEMASK
11 select PM_GENERIC_DOMAINS
11 default y 12 default y
12 help 13 help
13 Base platform code for any Samsung S3C64XX device 14 Base platform code for any Samsung S3C64XX device
@@ -77,6 +78,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
77 help 78 help
78 Common setup code for S3C64XX SDHCI GPIO configurations 79 Common setup code for S3C64XX SDHCI GPIO configurations
79 80
81config S3C64XX_SETUP_SPI
82 bool
83 help
84 Common setup code for SPI GPIO configurations
85
80# S36400 Macchine support 86# S36400 Macchine support
81 87
82config MACH_SMDK6400 88config MACH_SMDK6400
@@ -188,7 +194,7 @@ config SMDK6410_WM1190_EV1
188 depends on MACH_SMDK6410 194 depends on MACH_SMDK6410
189 select REGULATOR 195 select REGULATOR
190 select REGULATOR_WM8350 196 select REGULATOR_WM8350
191 select S3C24XX_GPIO_EXTRA64 197 select SAMSUNG_GPIO_EXTRA64
192 select MFD_WM8350_I2C 198 select MFD_WM8350_I2C
193 select MFD_WM8350_CONFIG_MODE_0 199 select MFD_WM8350_CONFIG_MODE_0
194 select MFD_WM8350_CONFIG_MODE_3 200 select MFD_WM8350_CONFIG_MODE_3
@@ -206,7 +212,7 @@ config SMDK6410_WM1192_EV1
206 depends on MACH_SMDK6410 212 depends on MACH_SMDK6410
207 select REGULATOR 213 select REGULATOR
208 select REGULATOR_WM831X 214 select REGULATOR_WM831X
209 select S3C24XX_GPIO_EXTRA64 215 select SAMSUNG_GPIO_EXTRA64
210 select MFD_WM831X 216 select MFD_WM831X
211 select MFD_WM831X_I2C 217 select MFD_WM831X_I2C
212 help 218 help
@@ -276,6 +282,7 @@ config MACH_WLF_CRAGG_6410
276 select S3C64XX_SETUP_IDE 282 select S3C64XX_SETUP_IDE
277 select S3C64XX_SETUP_FB_24BPP 283 select S3C64XX_SETUP_FB_24BPP
278 select S3C64XX_SETUP_KEYPAD 284 select S3C64XX_SETUP_KEYPAD
285 select S3C64XX_SETUP_SPI
279 select SAMSUNG_DEV_ADC 286 select SAMSUNG_DEV_ADC
280 select SAMSUNG_DEV_KEYPAD 287 select SAMSUNG_DEV_KEYPAD
281 select S3C_DEV_USB_HOST 288 select S3C_DEV_USB_HOST
@@ -286,8 +293,8 @@ config MACH_WLF_CRAGG_6410
286 select S3C_DEV_I2C1 293 select S3C_DEV_I2C1
287 select S3C_DEV_WDT 294 select S3C_DEV_WDT
288 select S3C_DEV_RTC 295 select S3C_DEV_RTC
289 select S3C64XX_DEV_SPI 296 select S3C64XX_DEV_SPI0
290 select S3C24XX_GPIO_EXTRA128 297 select SAMSUNG_GPIO_EXTRA128
291 select I2C 298 select I2C
292 help 299 help
293 Machine support for the Wolfson Cragganmore S3C6410 variant. 300 Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index f37016cebbe3..1822ac2eba31 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -40,8 +40,8 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
40obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o 40obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
41obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o 41obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
42obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o 42obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
43obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
44obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 43obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
44obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o
45 45
46# Machine support 46# Machine support
47 47
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 625219b9cefc..31bb27dc4aeb 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
184 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
186 }, { 186 }, {
187 .name = "spi_48m",
188 .devname = "s3c64xx-spi.0",
189 .parent = &clk_48m,
190 .enable = s3c64xx_sclk_ctrl,
191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
192 }, {
193 .name = "spi_48m",
194 .devname = "s3c64xx-spi.1",
195 .parent = &clk_48m,
196 .enable = s3c64xx_sclk_ctrl,
197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
198 }, {
199 .name = "48m", 187 .name = "48m",
200 .devname = "s3c-sdhci.0", 188 .devname = "s3c-sdhci.0",
201 .parent = &clk_48m, 189 .parent = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
226 }, 214 },
227}; 215};
228 216
217static struct clk clk_48m_spi0 = {
218 .name = "spi_48m",
219 .devname = "s3c64xx-spi.0",
220 .parent = &clk_48m,
221 .enable = s3c64xx_sclk_ctrl,
222 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
223};
224
225static struct clk clk_48m_spi1 = {
226 .name = "spi_48m",
227 .devname = "s3c64xx-spi.1",
228 .parent = &clk_48m,
229 .enable = s3c64xx_sclk_ctrl,
230 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
231};
232
229static struct clk init_clocks[] = { 233static struct clk init_clocks[] = {
230 { 234 {
231 .name = "lcd", 235 .name = "lcd",
@@ -243,24 +247,6 @@ static struct clk init_clocks[] = {
243 .enable = s3c64xx_hclk_ctrl, 247 .enable = s3c64xx_hclk_ctrl,
244 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 248 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
245 }, { 249 }, {
246 .name = "hsmmc",
247 .devname = "s3c-sdhci.0",
248 .parent = &clk_h,
249 .enable = s3c64xx_hclk_ctrl,
250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
251 }, {
252 .name = "hsmmc",
253 .devname = "s3c-sdhci.1",
254 .parent = &clk_h,
255 .enable = s3c64xx_hclk_ctrl,
256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
257 }, {
258 .name = "hsmmc",
259 .devname = "s3c-sdhci.2",
260 .parent = &clk_h,
261 .enable = s3c64xx_hclk_ctrl,
262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
263 }, {
264 .name = "otg", 250 .name = "otg",
265 .parent = &clk_h, 251 .parent = &clk_h,
266 .enable = s3c64xx_hclk_ctrl, 252 .enable = s3c64xx_hclk_ctrl,
@@ -310,6 +296,29 @@ static struct clk init_clocks[] = {
310 } 296 }
311}; 297};
312 298
299static struct clk clk_hsmmc0 = {
300 .name = "hsmmc",
301 .devname = "s3c-sdhci.0",
302 .parent = &clk_h,
303 .enable = s3c64xx_hclk_ctrl,
304 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
305};
306
307static struct clk clk_hsmmc1 = {
308 .name = "hsmmc",
309 .devname = "s3c-sdhci.1",
310 .parent = &clk_h,
311 .enable = s3c64xx_hclk_ctrl,
312 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
313};
314
315static struct clk clk_hsmmc2 = {
316 .name = "hsmmc",
317 .devname = "s3c-sdhci.2",
318 .parent = &clk_h,
319 .enable = s3c64xx_hclk_ctrl,
320 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
321};
313 322
314static struct clk clk_fout_apll = { 323static struct clk clk_fout_apll = {
315 .name = "fout_apll", 324 .name = "fout_apll",
@@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = {
578static struct clksrc_clk clksrcs[] = { 587static struct clksrc_clk clksrcs[] = {
579 { 588 {
580 .clk = { 589 .clk = {
581 .name = "mmc_bus",
582 .devname = "s3c-sdhci.0",
583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
584 .enable = s3c64xx_sclk_ctrl,
585 },
586 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
587 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
588 .sources = &clkset_spi_mmc,
589 }, {
590 .clk = {
591 .name = "mmc_bus",
592 .devname = "s3c-sdhci.1",
593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
594 .enable = s3c64xx_sclk_ctrl,
595 },
596 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
597 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
598 .sources = &clkset_spi_mmc,
599 }, {
600 .clk = {
601 .name = "mmc_bus",
602 .devname = "s3c-sdhci.2",
603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
604 .enable = s3c64xx_sclk_ctrl,
605 },
606 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
607 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
608 .sources = &clkset_spi_mmc,
609 }, {
610 .clk = {
611 .name = "usb-bus-host", 590 .name = "usb-bus-host",
612 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 591 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
613 .enable = s3c64xx_sclk_ctrl, 592 .enable = s3c64xx_sclk_ctrl,
@@ -617,35 +596,6 @@ static struct clksrc_clk clksrcs[] = {
617 .sources = &clkset_uhost, 596 .sources = &clkset_uhost,
618 }, { 597 }, {
619 .clk = { 598 .clk = {
620 .name = "uclk1",
621 .ctrlbit = S3C_CLKCON_SCLK_UART,
622 .enable = s3c64xx_sclk_ctrl,
623 },
624 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
625 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
626 .sources = &clkset_uart,
627 }, {
628/* Where does UCLK0 come from? */
629 .clk = {
630 .name = "spi-bus",
631 .devname = "s3c64xx-spi.0",
632 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
633 .enable = s3c64xx_sclk_ctrl,
634 },
635 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
636 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
637 .sources = &clkset_spi_mmc,
638 }, {
639 .clk = {
640 .name = "spi-bus",
641 .devname = "s3c64xx-spi.1",
642 .enable = s3c64xx_sclk_ctrl,
643 },
644 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
645 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
646 .sources = &clkset_spi_mmc,
647 }, {
648 .clk = {
649 .name = "audio-bus", 599 .name = "audio-bus",
650 .devname = "samsung-i2s.0", 600 .devname = "samsung-i2s.0",
651 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 601 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
@@ -695,6 +645,78 @@ static struct clksrc_clk clksrcs[] = {
695 }, 645 },
696}; 646};
697 647
648/* Where does UCLK0 come from? */
649static struct clksrc_clk clk_sclk_uclk = {
650 .clk = {
651 .name = "uclk1",
652 .ctrlbit = S3C_CLKCON_SCLK_UART,
653 .enable = s3c64xx_sclk_ctrl,
654 },
655 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
656 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
657 .sources = &clkset_uart,
658};
659
660static struct clksrc_clk clk_sclk_mmc0 = {
661 .clk = {
662 .name = "mmc_bus",
663 .devname = "s3c-sdhci.0",
664 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
665 .enable = s3c64xx_sclk_ctrl,
666 },
667 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
668 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
669 .sources = &clkset_spi_mmc,
670};
671
672static struct clksrc_clk clk_sclk_mmc1 = {
673 .clk = {
674 .name = "mmc_bus",
675 .devname = "s3c-sdhci.1",
676 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
677 .enable = s3c64xx_sclk_ctrl,
678 },
679 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
680 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
681 .sources = &clkset_spi_mmc,
682};
683
684static struct clksrc_clk clk_sclk_mmc2 = {
685 .clk = {
686 .name = "mmc_bus",
687 .devname = "s3c-sdhci.2",
688 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
689 .enable = s3c64xx_sclk_ctrl,
690 },
691 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
692 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
693 .sources = &clkset_spi_mmc,
694};
695
696static struct clksrc_clk clk_sclk_spi0 = {
697 .clk = {
698 .name = "spi-bus",
699 .devname = "s3c64xx-spi.0",
700 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
701 .enable = s3c64xx_sclk_ctrl,
702 },
703 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
704 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
705 .sources = &clkset_spi_mmc,
706};
707
708static struct clksrc_clk clk_sclk_spi1 = {
709 .clk = {
710 .name = "spi-bus",
711 .devname = "s3c64xx-spi.1",
712 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
713 .enable = s3c64xx_sclk_ctrl,
714 },
715 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
716 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
717 .sources = &clkset_spi_mmc,
718};
719
698/* Clock initialisation code */ 720/* Clock initialisation code */
699 721
700static struct clksrc_clk *init_parents[] = { 722static struct clksrc_clk *init_parents[] = {
@@ -703,6 +725,39 @@ static struct clksrc_clk *init_parents[] = {
703 &clk_mout_mpll, 725 &clk_mout_mpll,
704}; 726};
705 727
728static struct clksrc_clk *clksrc_cdev[] = {
729 &clk_sclk_uclk,
730 &clk_sclk_mmc0,
731 &clk_sclk_mmc1,
732 &clk_sclk_mmc2,
733 &clk_sclk_spi0,
734 &clk_sclk_spi1,
735};
736
737static struct clk *clk_cdev[] = {
738 &clk_hsmmc0,
739 &clk_hsmmc1,
740 &clk_hsmmc2,
741 &clk_48m_spi0,
742 &clk_48m_spi1,
743};
744
745static struct clk_lookup s3c64xx_clk_lookup[] = {
746 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
747 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
748 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
749 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
750 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
751 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
752 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
753 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
754 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
755 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
756 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
757 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
758 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
759};
760
706#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
707 762
708void __init_or_cpufreq s3c64xx_setup_clocks(void) 763void __init_or_cpufreq s3c64xx_setup_clocks(void)
@@ -811,6 +866,8 @@ static struct clk *clks[] __initdata = {
811void __init s3c64xx_register_clocks(unsigned long xtal, 866void __init s3c64xx_register_clocks(unsigned long xtal,
812 unsigned armclk_divlimit) 867 unsigned armclk_divlimit)
813{ 868{
869 unsigned int cnt;
870
814 armclk_mask = armclk_divlimit; 871 armclk_mask = armclk_divlimit;
815 872
816 s3c24xx_register_baseclocks(xtal); 873 s3c24xx_register_baseclocks(xtal);
@@ -821,7 +878,15 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
821 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 878 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
822 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 879 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
823 880
881 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
882 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
883 s3c_disable_clocks(clk_cdev[cnt], 1);
884
824 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); 885 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
825 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 886 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
887 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
888 s3c_register_clksrc(clksrc_cdev[cnt], 1);
889 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
890
826 s3c_pwmclk_init(); 891 s3c_pwmclk_init();
827} 892}
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 35182ba049da..4a7394d4bd9e 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -19,7 +19,6 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/ioport.h> 21#include <linux/ioport.h>
22#include <linux/sysdev.h>
23#include <linux/serial_core.h> 22#include <linux/serial_core.h>
24#include <linux/platform_device.h> 23#include <linux/platform_device.h>
25#include <linux/io.h> 24#include <linux/io.h>
@@ -139,12 +138,13 @@ static struct map_desc s3c_iodesc[] __initdata = {
139 }, 138 },
140}; 139};
141 140
142struct sysdev_class s3c64xx_sysclass = { 141static struct bus_type s3c64xx_subsys = {
143 .name = "s3c64xx-core", 142 .name = "s3c64xx-core",
143 .dev_name = "s3c64xx-core",
144}; 144};
145 145
146static struct sys_device s3c64xx_sysdev = { 146static struct device s3c64xx_dev = {
147 .cls = &s3c64xx_sysclass, 147 .bus = &s3c64xx_subsys,
148}; 148};
149 149
150/* read cpu identification code */ 150/* read cpu identification code */
@@ -162,12 +162,12 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
162 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 162 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
163} 163}
164 164
165static __init int s3c64xx_sysdev_init(void) 165static __init int s3c64xx_dev_init(void)
166{ 166{
167 sysdev_class_register(&s3c64xx_sysclass); 167 subsys_system_register(&s3c64xx_subsys, NULL);
168 return sysdev_register(&s3c64xx_sysdev); 168 return device_register(&s3c64xx_dev);
169} 169}
170core_initcall(s3c64xx_sysdev_init); 170core_initcall(s3c64xx_dev_init);
171 171
172/* 172/*
173 * setup the sources the vic should advertise resume 173 * setup the sources the vic should advertise resume
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 8dc8ab6d8d6d..5eb9c9a7d73b 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -26,7 +26,6 @@ void s3c64xx_setup_clocks(void);
26void s3c64xx_restart(char mode, const char *cmd); 26void s3c64xx_restart(char mode, const char *cmd);
27 27
28extern struct syscore_ops s3c64xx_irq_syscore_ops; 28extern struct syscore_ops s3c64xx_irq_syscore_ops;
29extern struct sysdev_class s3c64xx_sysclass;
30 29
31#ifdef CONFIG_CPU_S3C6400 30#ifdef CONFIG_CPU_S3C6400
32 31
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3341fd118723..000000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/dev-spi.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/export.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/spi-clocks.h>
21#include <mach/irqs.h>
22
23#include <plat/s3c64xx-spi.h>
24#include <plat/gpio-cfg.h>
25#include <plat/devs.h>
26
27static char *spi_src_clks[] = {
28 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
29 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
30 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S3C64XX_GPC(0);
48 break;
49
50 case 1:
51 base = S3C64XX_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static struct resource s3c64xx_spi0_resource[] = {
66 [0] = {
67 .start = S3C64XX_PA_SPI0,
68 .end = S3C64XX_PA_SPI0 + 0x100 - 1,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = DMACH_SPI0_TX,
73 .end = DMACH_SPI0_TX,
74 .flags = IORESOURCE_DMA,
75 },
76 [2] = {
77 .start = DMACH_SPI0_RX,
78 .end = DMACH_SPI0_RX,
79 .flags = IORESOURCE_DMA,
80 },
81 [3] = {
82 .start = IRQ_SPI0,
83 .end = IRQ_SPI0,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
89 .cfg_gpio = s3c64xx_spi_cfg_gpio,
90 .fifo_lvl_mask = 0x7f,
91 .rx_lvl_offset = 13,
92 .tx_st_done = 21,
93};
94
95static u64 spi_dmamask = DMA_BIT_MASK(32);
96
97struct platform_device s3c64xx_device_spi0 = {
98 .name = "s3c64xx-spi",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
101 .resource = s3c64xx_spi0_resource,
102 .dev = {
103 .dma_mask = &spi_dmamask,
104 .coherent_dma_mask = DMA_BIT_MASK(32),
105 .platform_data = &s3c64xx_spi0_pdata,
106 },
107};
108EXPORT_SYMBOL(s3c64xx_device_spi0);
109
110static struct resource s3c64xx_spi1_resource[] = {
111 [0] = {
112 .start = S3C64XX_PA_SPI1,
113 .end = S3C64XX_PA_SPI1 + 0x100 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = DMACH_SPI1_TX,
118 .end = DMACH_SPI1_TX,
119 .flags = IORESOURCE_DMA,
120 },
121 [2] = {
122 .start = DMACH_SPI1_RX,
123 .end = DMACH_SPI1_RX,
124 .flags = IORESOURCE_DMA,
125 },
126 [3] = {
127 .start = IRQ_SPI1,
128 .end = IRQ_SPI1,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
134 .cfg_gpio = s3c64xx_spi_cfg_gpio,
135 .fifo_lvl_mask = 0x7f,
136 .rx_lvl_offset = 13,
137 .tx_st_done = 21,
138};
139
140struct platform_device s3c64xx_device_spi1 = {
141 .name = "s3c64xx-spi",
142 .id = 1,
143 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
144 .resource = s3c64xx_spi1_resource,
145 .dev = {
146 .dma_mask = &spi_dmamask,
147 .coherent_dma_mask = DMA_BIT_MASK(32),
148 .platform_data = &s3c64xx_spi1_pdata,
149 },
150};
151EXPORT_SYMBOL(s3c64xx_device_spi1);
152
153void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
154{
155 struct s3c64xx_spi_info *pd;
156
157 /* Reject invalid configuration */
158 if (!num_cs || src_clk_nr < 0
159 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
160 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
161 return;
162 }
163
164 switch (cntrlr) {
165 case 0:
166 pd = &s3c64xx_spi0_pdata;
167 break;
168 case 1:
169 pd = &s3c64xx_spi1_pdata;
170 break;
171 default:
172 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
173 __func__, cntrlr);
174 return;
175 }
176
177 pd->num_cs = num_cs;
178 pd->src_clk_nr = src_clk_nr;
179 pd->src_clk_name = spi_src_clks[src_clk_nr];
180}
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 17d62f4f8204..f2a7a1725596 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -16,7 +16,7 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/dmapool.h> 18#include <linux/dmapool.h>
19#include <linux/sysdev.h> 19#include <linux/device.h>
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/slab.h> 21#include <linux/slab.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
@@ -35,7 +35,7 @@
35/* dma channel state information */ 35/* dma channel state information */
36 36
37struct s3c64xx_dmac { 37struct s3c64xx_dmac {
38 struct sys_device sysdev; 38 struct device dev;
39 struct clk *clk; 39 struct clk *clk;
40 void __iomem *regs; 40 void __iomem *regs;
41 struct s3c2410_dma_chan *channels; 41 struct s3c2410_dma_chan *channels;
@@ -631,8 +631,9 @@ static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
631 return IRQ_HANDLED; 631 return IRQ_HANDLED;
632} 632}
633 633
634static struct sysdev_class dma_sysclass = { 634static struct bus_type dma_subsys = {
635 .name = "s3c64xx-dma", 635 .name = "s3c64xx-dma",
636 .dev_name = "s3c64xx-dma",
636}; 637};
637 638
638static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, 639static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
@@ -651,12 +652,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
651 return -ENOMEM; 652 return -ENOMEM;
652 } 653 }
653 654
654 dmac->sysdev.id = chno / 8; 655 dmac->dev.id = chno / 8;
655 dmac->sysdev.cls = &dma_sysclass; 656 dmac->dev.bus = &dma_subsys;
656 657
657 err = sysdev_register(&dmac->sysdev); 658 err = device_register(&dmac->dev);
658 if (err) { 659 if (err) {
659 printk(KERN_ERR "%s: failed to register sysdevice\n", __func__); 660 printk(KERN_ERR "%s: failed to register device\n", __func__);
660 goto err_alloc; 661 goto err_alloc;
661 } 662 }
662 663
@@ -667,7 +668,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
667 goto err_dev; 668 goto err_dev;
668 } 669 }
669 670
670 snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id); 671 snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id);
671 672
672 dmac->clk = clk_get(NULL, clkname); 673 dmac->clk = clk_get(NULL, clkname);
673 if (IS_ERR(dmac->clk)) { 674 if (IS_ERR(dmac->clk)) {
@@ -715,7 +716,7 @@ err_clk:
715err_map: 716err_map:
716 iounmap(regs); 717 iounmap(regs);
717err_dev: 718err_dev:
718 sysdev_unregister(&dmac->sysdev); 719 device_unregister(&dmac->dev);
719err_alloc: 720err_alloc:
720 kfree(dmac); 721 kfree(dmac);
721 return err; 722 return err;
@@ -733,9 +734,9 @@ static int __init s3c64xx_dma_init(void)
733 return -ENOMEM; 734 return -ENOMEM;
734 } 735 }
735 736
736 ret = sysdev_class_register(&dma_sysclass); 737 ret = subsys_system_register(&dma_subsys, NULL);
737 if (ret) { 738 if (ret) {
738 printk(KERN_ERR "%s: failed to create sysclass\n", __func__); 739 printk(KERN_ERR "%s: failed to create subsys\n", __func__);
739 return -ENOMEM; 740 return -ENOMEM;
740 } 741 }
741 742
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
index be9074e17dfd..5d55ab018b6b 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -15,9 +15,11 @@
15 15
16#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START 16#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
17#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64) 17#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
18#define CODEC_IRQ_BASE (IRQ_BOARD_START + 128)
18 19
19#define PCA935X_GPIO_BASE GPIO_BOARD_START 20#define PCA935X_GPIO_BASE GPIO_BOARD_START
20#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) 21#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
21#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16) 22#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32)
23#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64)
22 24
23#endif 25#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h
index 6e34c2f6e670..8b540c42d5dd 100644
--- a/arch/arm/mach-s3c64xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h
@@ -88,6 +88,6 @@ enum s3c_gpio_number {
88/* define the number of gpios we need to the one after the GPQ() range */ 88/* define the number of gpios we need to the one after the GPQ() range */
89#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) 89#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
90 90
91#define BOARD_NR_GPIOS 16 91#define BOARD_NR_GPIOS (16 + CONFIG_SAMSUNG_GPIO_EXTRA)
92 92
93#define ARCH_NR_GPIOS (GPIO_BOARD_START + BOARD_NR_GPIOS) 93#define ARCH_NR_GPIOS (GPIO_BOARD_START + BOARD_NR_GPIOS)
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 443f85b3c203..96d60e0d9372 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -169,7 +169,7 @@
169#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) 169#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
170 170
171#ifdef CONFIG_MACH_WLF_CRAGG_6410 171#ifdef CONFIG_MACH_WLF_CRAGG_6410
172#define IRQ_BOARD_NR 128 172#define IRQ_BOARD_NR 160
173#elif defined(CONFIG_SMDK6410_WM1190_EV1) 173#elif defined(CONFIG_SMDK6410_WM1190_EV1)
174#define IRQ_BOARD_NR 64 174#define IRQ_BOARD_NR 64
175#elif defined(CONFIG_SMDK6410_WM1192_EV1) 175#elif defined(CONFIG_SMDK6410_WM1192_EV1)
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 23a1d71e4d53..8e2097bb208a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -115,6 +115,8 @@
115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG 115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
116#define S3C_PA_RTC S3C64XX_PA_RTC 116#define S3C_PA_RTC S3C64XX_PA_RTC
117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG 117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
118#define S3C_PA_SPI0 S3C64XX_PA_SPI0
119#define S3C_PA_SPI1 S3C64XX_PA_SPI1
118 120
119#define SAMSUNG_PA_ADC S3C64XX_PA_ADC 121#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
120#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON 122#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index f208154b1382..cd3c97e2ee75 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -14,13 +14,43 @@
14 14
15#include <linux/mfd/wm831x/irq.h> 15#include <linux/mfd/wm831x/irq.h>
16#include <linux/mfd/wm831x/gpio.h> 16#include <linux/mfd/wm831x/gpio.h>
17#include <linux/mfd/wm8994/pdata.h>
17 18
19#include <sound/wm5100.h>
18#include <sound/wm8996.h> 20#include <sound/wm8996.h>
19#include <sound/wm8962.h> 21#include <sound/wm8962.h>
20#include <sound/wm9081.h> 22#include <sound/wm9081.h>
21 23
22#include <mach/crag6410.h> 24#include <mach/crag6410.h>
23 25
26static struct wm5100_pdata wm5100_pdata = {
27 .ldo_ena = S3C64XX_GPN(7),
28 .irq_flags = IRQF_TRIGGER_HIGH,
29 .gpio_base = CODEC_GPIO_BASE,
30
31 .in_mode = {
32 WM5100_IN_DIFF,
33 WM5100_IN_DIFF,
34 WM5100_IN_DIFF,
35 WM5100_IN_SE,
36 },
37
38 .hp_pol = CODEC_GPIO_BASE + 3,
39 .jack_modes = {
40 { WM5100_MICDET_MICBIAS3, 0, 0 },
41 { WM5100_MICDET_MICBIAS2, 1, 1 },
42 },
43
44 .gpio_defaults = {
45 0,
46 0,
47 0,
48 0,
49 0x2, /* IRQ: CMOS output */
50 0x3, /* CLKOUT: CMOS output */
51 },
52};
53
24static struct wm8996_retune_mobile_config wm8996_retune[] = { 54static struct wm8996_retune_mobile_config wm8996_retune[] = {
25 { 55 {
26 .name = "Sub LPF", 56 .name = "Sub LPF",
@@ -72,7 +102,6 @@ static struct wm8962_pdata wm8962_pdata __initdata = {
72 0x8000 | WM8962_GPIO_FN_DMICDAT, 102 0x8000 | WM8962_GPIO_FN_DMICDAT,
73 WM8962_GPIO_FN_IRQ, /* Open drain mode */ 103 WM8962_GPIO_FN_IRQ, /* Open drain mode */
74 }, 104 },
75 .irq_active_low = true,
76}; 105};
77 106
78static struct wm9081_pdata wm9081_pdata __initdata = { 107static struct wm9081_pdata wm9081_pdata __initdata = {
@@ -91,6 +120,7 @@ static const struct i2c_board_info wm1254_devs[] = {
91 120
92static const struct i2c_board_info wm1255_devs[] = { 121static const struct i2c_board_info wm1255_devs[] = {
93 { I2C_BOARD_INFO("wm5100", 0x1a), 122 { I2C_BOARD_INFO("wm5100", 0x1a),
123 .platform_data = &wm5100_pdata,
94 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, 124 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
95 }, 125 },
96 { I2C_BOARD_INFO("wm9081", 0x6c), 126 { I2C_BOARD_INFO("wm9081", 0x6c),
@@ -104,6 +134,24 @@ static const struct i2c_board_info wm1259_devs[] = {
104 }, 134 },
105}; 135};
106 136
137static struct wm8994_pdata wm8994_pdata = {
138 .gpio_base = CODEC_GPIO_BASE,
139 .gpio_defaults = {
140 0x3, /* IRQ out, active high, CMOS */
141 },
142 .irq_base = CODEC_IRQ_BASE,
143 .ldo = {
144 { .supply = "WALLVDD" },
145 { .supply = "WALLVDD" },
146 },
147};
148
149static const struct i2c_board_info wm1277_devs[] = {
150 { I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */
151 .platform_data = &wm8994_pdata,
152 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
153 },
154};
107 155
108static __devinitdata const struct { 156static __devinitdata const struct {
109 u8 id; 157 u8 id;
@@ -125,6 +173,8 @@ static __devinitdata const struct {
125 { .id = 0x3b, .name = "1255-EV1 Kilchoman", 173 { .id = 0x3b, .name = "1255-EV1 Kilchoman",
126 .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) }, 174 .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
127 { .id = 0x3c, .name = "1273-EV1 Longmorn" }, 175 { .id = 0x3c, .name = "1273-EV1 Longmorn" },
176 { .id = 0x3d, .name = "1277-EV1 Littlemill",
177 .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
128}; 178};
129 179
130static __devinit int wlf_gf_module_probe(struct i2c_client *i2c, 180static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
@@ -154,8 +204,8 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
154 "Failed to register dev: %d\n", ret); 204 "Failed to register dev: %d\n", ret);
155 } 205 }
156 } else { 206 } else {
157 dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n", 207 dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
158 id, rev); 208 id, rev + 1);
159 } 209 }
160 210
161 return 0; 211 return 0;
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index f1c848aa4a1e..1cc91d794c97 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -37,6 +37,8 @@
37#include <linux/mfd/wm831x/irq.h> 37#include <linux/mfd/wm831x/irq.h>
38#include <linux/mfd/wm831x/gpio.h> 38#include <linux/mfd/wm831x/gpio.h>
39 39
40#include <sound/wm1250-ev1.h>
41
40#include <asm/hardware/vic.h> 42#include <asm/hardware/vic.h>
41#include <asm/mach/arch.h> 43#include <asm/mach/arch.h>
42#include <asm/mach-types.h> 44#include <asm/mach-types.h>
@@ -284,8 +286,13 @@ static struct platform_device lowland_device = {
284 .id = -1, 286 .id = -1,
285}; 287};
286 288
287static struct platform_device speyside_wm8962_device = { 289static struct platform_device tobermory_device = {
288 .name = "speyside-wm8962", 290 .name = "tobermory",
291 .id = -1,
292};
293
294static struct platform_device littlemill_device = {
295 .name = "littlemill",
289 .id = -1, 296 .id = -1,
290}; 297};
291 298
@@ -340,7 +347,8 @@ static struct platform_device *crag6410_devices[] __initdata = {
340 &crag6410_lcd_powerdev, 347 &crag6410_lcd_powerdev,
341 &crag6410_backlight_device, 348 &crag6410_backlight_device,
342 &speyside_device, 349 &speyside_device,
343 &speyside_wm8962_device, 350 &tobermory_device,
351 &littlemill_device,
344 &lowland_device, 352 &lowland_device,
345 &wallvdd_device, 353 &wallvdd_device,
346}; 354};
@@ -374,6 +382,10 @@ static struct regulator_init_data vddarm __initdata = {
374 .driver_data = &vddarm_pdata, 382 .driver_data = &vddarm_pdata,
375}; 383};
376 384
385static struct regulator_consumer_supply vddint_consumers[] __initdata = {
386 REGULATOR_SUPPLY("vddint", NULL),
387};
388
377static struct regulator_init_data vddint __initdata = { 389static struct regulator_init_data vddint __initdata = {
378 .constraints = { 390 .constraints = {
379 .name = "VDDINT", 391 .name = "VDDINT",
@@ -382,6 +394,9 @@ static struct regulator_init_data vddint __initdata = {
382 .always_on = 1, 394 .always_on = 1,
383 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 395 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
384 }, 396 },
397 .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
398 .consumer_supplies = vddint_consumers,
399 .supply_regulator = "WALLVDD",
385}; 400};
386 401
387static struct regulator_init_data vddmem __initdata = { 402static struct regulator_init_data vddmem __initdata = {
@@ -502,7 +517,8 @@ static struct wm831x_touch_pdata touch_pdata __initdata = {
502static struct wm831x_pdata crag_pmic_pdata __initdata = { 517static struct wm831x_pdata crag_pmic_pdata __initdata = {
503 .wm831x_num = 1, 518 .wm831x_num = 1,
504 .irq_base = BANFF_PMIC_IRQ_BASE, 519 .irq_base = BANFF_PMIC_IRQ_BASE,
505 .gpio_base = GPIO_BOARD_START + 8, 520 .gpio_base = BANFF_PMIC_GPIO_BASE,
521 .soft_shutdown = true,
506 522
507 .backup = &banff_backup_pdata, 523 .backup = &banff_backup_pdata,
508 524
@@ -607,6 +623,7 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
607 .wm831x_num = 2, 623 .wm831x_num = 2,
608 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE, 624 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
609 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE, 625 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
626 .soft_shutdown = true,
610 627
611 .gpio_defaults = { 628 .gpio_defaults = {
612 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */ 629 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
@@ -624,6 +641,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
624 .disable_touch = true, 641 .disable_touch = true,
625}; 642};
626 643
644static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
645 .gpios = {
646 [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
647 [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
648 [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
649 [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
650 [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
651 },
652};
653
627static struct i2c_board_info i2c_devs1[] __initdata = { 654static struct i2c_board_info i2c_devs1[] __initdata = {
628 { I2C_BOARD_INFO("wm8311", 0x34), 655 { I2C_BOARD_INFO("wm8311", 0x34),
629 .irq = S3C_EINT(0), 656 .irq = S3C_EINT(0),
@@ -633,7 +660,13 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
633 { I2C_BOARD_INFO("wlf-gf-module", 0x25) }, 660 { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
634 { I2C_BOARD_INFO("wlf-gf-module", 0x26) }, 661 { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
635 662
636 { I2C_BOARD_INFO("wm1250-ev1", 0x27) }, 663 { I2C_BOARD_INFO("wm1250-ev1", 0x27),
664 .platform_data = &wm1250_ev1_pdata },
665};
666
667static struct s3c2410_platform_i2c i2c1_pdata = {
668 .frequency = 400000,
669 .bus_num = 1,
637}; 670};
638 671
639static void __init crag6410_map_io(void) 672static void __init crag6410_map_io(void)
@@ -694,7 +727,7 @@ static void __init crag6410_machine_init(void)
694 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata); 727 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
695 728
696 s3c_i2c0_set_platdata(&i2c0_pdata); 729 s3c_i2c0_set_platdata(&i2c0_pdata);
697 s3c_i2c1_set_platdata(NULL); 730 s3c_i2c1_set_platdata(&i2c1_pdata);
698 s3c_fb_set_platdata(&crag6410_lcd_pdata); 731 s3c_fb_set_platdata(&crag6410_lcd_pdata);
699 732
700 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); 733 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
@@ -706,7 +739,7 @@ static void __init crag6410_machine_init(void)
706 739
707 regulator_has_full_constraints(); 740 regulator_has_full_constraints();
708 741
709 s3c_pm_init(); 742 s3c64xx_pm_init();
710} 743}
711 744
712MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") 745MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b375cd5c47cb..055dac90e0e2 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -17,10 +17,12 @@
17#include <linux/serial_core.h> 17#include <linux/serial_core.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/pm_domain.h>
20 21
21#include <mach/map.h> 22#include <mach/map.h>
22#include <mach/irqs.h> 23#include <mach/irqs.h>
23 24
25#include <plat/devs.h>
24#include <plat/pm.h> 26#include <plat/pm.h>
25#include <plat/wakeup-mask.h> 27#include <plat/wakeup-mask.h>
26 28
@@ -31,6 +33,148 @@
31#include <mach/regs-gpio-memport.h> 33#include <mach/regs-gpio-memport.h>
32#include <mach/regs-modem.h> 34#include <mach/regs-modem.h>
33 35
36struct s3c64xx_pm_domain {
37 char *const name;
38 u32 ena;
39 u32 pwr_stat;
40 struct generic_pm_domain pd;
41};
42
43static int s3c64xx_pd_off(struct generic_pm_domain *domain)
44{
45 struct s3c64xx_pm_domain *pd;
46 u32 val;
47
48 pd = container_of(domain, struct s3c64xx_pm_domain, pd);
49
50 val = __raw_readl(S3C64XX_NORMAL_CFG);
51 val &= ~(pd->ena);
52 __raw_writel(val, S3C64XX_NORMAL_CFG);
53
54 return 0;
55}
56
57static int s3c64xx_pd_on(struct generic_pm_domain *domain)
58{
59 struct s3c64xx_pm_domain *pd;
60 u32 val;
61 long retry = 1000000L;
62
63 pd = container_of(domain, struct s3c64xx_pm_domain, pd);
64
65 val = __raw_readl(S3C64XX_NORMAL_CFG);
66 val |= pd->ena;
67 __raw_writel(val, S3C64XX_NORMAL_CFG);
68
69 /* Not all domains provide power status readback */
70 if (pd->pwr_stat) {
71 do {
72 cpu_relax();
73 if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
74 break;
75 } while (retry--);
76
77 if (!retry) {
78 pr_err("Failed to start domain %s\n", pd->name);
79 return -EBUSY;
80 }
81 }
82
83 return 0;
84}
85
86static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
87 .name = "IROM",
88 .ena = S3C64XX_NORMALCFG_IROM_ON,
89 .pd = {
90 .power_off = s3c64xx_pd_off,
91 .power_on = s3c64xx_pd_on,
92 },
93};
94
95static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
96 .name = "ETM",
97 .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
98 .pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
99 .pd = {
100 .power_off = s3c64xx_pd_off,
101 .power_on = s3c64xx_pd_on,
102 },
103};
104
105static struct s3c64xx_pm_domain s3c64xx_pm_s = {
106 .name = "S",
107 .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
108 .pwr_stat = S3C64XX_BLKPWRSTAT_S,
109 .pd = {
110 .power_off = s3c64xx_pd_off,
111 .power_on = s3c64xx_pd_on,
112 },
113};
114
115static struct s3c64xx_pm_domain s3c64xx_pm_f = {
116 .name = "F",
117 .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
118 .pwr_stat = S3C64XX_BLKPWRSTAT_F,
119 .pd = {
120 .power_off = s3c64xx_pd_off,
121 .power_on = s3c64xx_pd_on,
122 },
123};
124
125static struct s3c64xx_pm_domain s3c64xx_pm_p = {
126 .name = "P",
127 .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
128 .pwr_stat = S3C64XX_BLKPWRSTAT_P,
129 .pd = {
130 .power_off = s3c64xx_pd_off,
131 .power_on = s3c64xx_pd_on,
132 },
133};
134
135static struct s3c64xx_pm_domain s3c64xx_pm_i = {
136 .name = "I",
137 .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
138 .pwr_stat = S3C64XX_BLKPWRSTAT_I,
139 .pd = {
140 .power_off = s3c64xx_pd_off,
141 .power_on = s3c64xx_pd_on,
142 },
143};
144
145static struct s3c64xx_pm_domain s3c64xx_pm_g = {
146 .name = "G",
147 .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
148 .pd = {
149 .power_off = s3c64xx_pd_off,
150 .power_on = s3c64xx_pd_on,
151 },
152};
153
154static struct s3c64xx_pm_domain s3c64xx_pm_v = {
155 .name = "V",
156 .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
157 .pwr_stat = S3C64XX_BLKPWRSTAT_V,
158 .pd = {
159 .power_off = s3c64xx_pd_off,
160 .power_on = s3c64xx_pd_on,
161 },
162};
163
164static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
165 &s3c64xx_pm_irom,
166};
167
168static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
169 &s3c64xx_pm_etm,
170 &s3c64xx_pm_g,
171 &s3c64xx_pm_v,
172 &s3c64xx_pm_i,
173 &s3c64xx_pm_p,
174 &s3c64xx_pm_s,
175 &s3c64xx_pm_f,
176};
177
34#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 178#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
35void s3c_pm_debug_smdkled(u32 set, u32 clear) 179void s3c_pm_debug_smdkled(u32 set, u32 clear)
36{ 180{
@@ -89,6 +233,8 @@ static struct sleep_save misc_save[] = {
89 233
90 SAVE_ITEM(S3C64XX_SDMA_SEL), 234 SAVE_ITEM(S3C64XX_SDMA_SEL),
91 SAVE_ITEM(S3C64XX_MODEM_MIFPCON), 235 SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
236
237 SAVE_ITEM(S3C64XX_NORMAL_CFG),
92}; 238};
93 239
94void s3c_pm_configure_extint(void) 240void s3c_pm_configure_extint(void)
@@ -179,12 +325,44 @@ static void s3c64xx_pm_prepare(void)
179 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); 325 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
180} 326}
181 327
182static int s3c64xx_pm_init(void) 328int __init s3c64xx_pm_init(void)
329{
330 int i;
331
332 s3c_pm_init();
333
334 for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
335 pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
336 &pm_domain_always_on_gov, false);
337
338 for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
339 pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
340
341 if (dev_get_platdata(&s3c_device_fb.dev))
342 pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
343
344 return 0;
345}
346
347static __init int s3c64xx_pm_initcall(void)
183{ 348{
349 u32 val;
350
184 pm_cpu_prep = s3c64xx_pm_prepare; 351 pm_cpu_prep = s3c64xx_pm_prepare;
185 pm_cpu_sleep = s3c64xx_cpu_suspend; 352 pm_cpu_sleep = s3c64xx_cpu_suspend;
186 pm_uart_udivslot = 1; 353 pm_uart_udivslot = 1;
187 354
355 /*
356 * Unconditionally disable power domains that contain only
357 * blocks which have no mainline driver support.
358 */
359 val = __raw_readl(S3C64XX_NORMAL_CFG);
360 val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
361 S3C64XX_NORMALCFG_DOMAIN_V_ON |
362 S3C64XX_NORMALCFG_DOMAIN_I_ON |
363 S3C64XX_NORMALCFG_DOMAIN_P_ON);
364 __raw_writel(val, S3C64XX_NORMAL_CFG);
365
188#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 366#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
189 gpio_request(S3C64XX_GPN(12), "DEBUG_LED0"); 367 gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
190 gpio_request(S3C64XX_GPN(13), "DEBUG_LED1"); 368 gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
@@ -198,5 +376,12 @@ static int s3c64xx_pm_init(void)
198 376
199 return 0; 377 return 0;
200} 378}
379arch_initcall(s3c64xx_pm_initcall);
380
381static __init int s3c64xx_pm_late_initcall(void)
382{
383 pm_genpd_poweroff_unused();
201 384
202arch_initcall(s3c64xx_pm_init); 385 return 0;
386}
387late_initcall(s3c64xx_pm_late_initcall);
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index b1e1571f2f6b..4869714c6f1b 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -17,7 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/sysdev.h> 20#include <linux/device.h>
21#include <linux/serial_core.h> 21#include <linux/serial_core.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23 23
@@ -71,17 +71,18 @@ void __init s3c6400_init_irq(void)
71 s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); 71 s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
72} 72}
73 73
74static struct sysdev_class s3c6400_sysclass = { 74static struct bus_type s3c6400_subsys = {
75 .name = "s3c6400-core", 75 .name = "s3c6400-core",
76 .dev_name = "s3c6400-core",
76}; 77};
77 78
78static struct sys_device s3c6400_sysdev = { 79static struct device s3c6400_dev = {
79 .cls = &s3c6400_sysclass, 80 .bus = &s3c6400_subsys,
80}; 81};
81 82
82static int __init s3c6400_core_init(void) 83static int __init s3c6400_core_init(void)
83{ 84{
84 return sysdev_class_register(&s3c6400_sysclass); 85 return subsys_system_register(&s3c6400_subsys, NULL);
85} 86}
86 87
87core_initcall(s3c6400_core_init); 88core_initcall(s3c6400_core_init);
@@ -90,5 +91,5 @@ int __init s3c6400_init(void)
90{ 91{
91 printk("S3C6400: Initialising architecture\n"); 92 printk("S3C6400: Initialising architecture\n");
92 93
93 return sysdev_register(&s3c6400_sysdev); 94 return device_register(&s3c6400_dev);
94} 95}
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index fba71bd991c7..31c29fdf1800 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -18,7 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/sysdev.h> 21#include <linux/device.h>
22#include <linux/serial_core.h> 22#include <linux/serial_core.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
@@ -75,17 +75,18 @@ void __init s3c6410_init_irq(void)
75 s3c64xx_init_irq(~0 & ~(1 << 7), ~0); 75 s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
76} 76}
77 77
78struct sysdev_class s3c6410_sysclass = { 78struct bus_type s3c6410_subsys = {
79 .name = "s3c6410-core", 79 .name = "s3c6410-core",
80 .dev_name = "s3c6410-core",
80}; 81};
81 82
82static struct sys_device s3c6410_sysdev = { 83static struct device s3c6410_dev = {
83 .cls = &s3c6410_sysclass, 84 .bus = &s3c6410_subsys,
84}; 85};
85 86
86static int __init s3c6410_core_init(void) 87static int __init s3c6410_core_init(void)
87{ 88{
88 return sysdev_class_register(&s3c6410_sysclass); 89 return subsys_system_register(&s3c6410_subsys, NULL);
89} 90}
90 91
91core_initcall(s3c6410_core_init); 92core_initcall(s3c6410_core_init);
@@ -94,5 +95,5 @@ int __init s3c6410_init(void)
94{ 95{
95 printk("S3C6410: Initialising architecture\n"); 96 printk("S3C6410: Initialising architecture\n");
96 97
97 return sysdev_register(&s3c6410_sysdev); 98 return device_register(&s3c6410_dev);
98} 99}
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b21165..000000000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16
17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
18
19char *s3c64xx_hsmmc_clksrcs[4] = {
20 [0] = "hsmmc",
21 [1] = "hsmmc",
22 [2] = "mmc_bus",
23 /* [3] = "48m", - note not successfully used yet */
24};
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
new file mode 100644
index 000000000000..d9592ad7a825
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -0,0 +1,45 @@
1/* linux/arch/arm/mach-s3c64xx/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .tx_st_done = 21,
22};
23
24int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 return 0;
29}
30#endif
31
32#ifdef CONFIG_S3C64XX_DEV_SPI1
33struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
34 .fifo_lvl_mask = 0x7f,
35 .rx_lvl_offset = 13,
36 .tx_st_done = 21,
37};
38
39int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
40{
41 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
43 return 0;
44}
45#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 11:04:46 -0500