8 files changed, 313 insertions, 10 deletions

diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index dd20c66cd700..326ea3a98725 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -83,6 +83,11 @@ config S3C64XX_SETUP_SPI
         help
          Common setup code for SPI GPIO configurations
 
+config S3C64XX_SETUP_USB_PHY
+        bool
+        help
+          Common setup code for USB PHY controller
+
 # S36400 Macchine support
 
 config MACH_SMDK6400
@@ -157,6 +162,7 @@ config MACH_SMDK6410
         select S3C64XX_SETUP_IDE
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
+        select S3C64XX_SETUP_USB_PHY
         help
           Machine support for the Samsung SMDK6410
 
@@ -256,6 +262,7 @@ config MACH_SMARTQ
         select S3C_DEV_USB_HOST
         select S3C64XX_SETUP_SDHCI
         select S3C64XX_SETUP_FB_24BPP
+        select S3C64XX_SETUP_USB_PHY
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
@@ -283,6 +290,7 @@ config MACH_WLF_CRAGG_6410
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
         select S3C64XX_SETUP_SPI
+        select S3C64XX_SETUP_USB_PHY
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_KEYPAD
         select S3C_DEV_USB_HOST
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 1822ac2eba31..f9ce1dc28ce4 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_CPU_S3C6410)	+= s3c6410.o
 # PM
 
 obj-$(CONFIG_PM)                += pm.o irq-pm.o sleep.o
+obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
 # DMA support
 
@@ -42,6 +43,7 @@ obj-$(CONFIG_S3C64XX_SETUP_IDE)		+= setup-ide.o
 obj-$(CONFIG_S3C64XX_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_S3C64XX_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index aebbcc291b4e..52f079a691cb 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -207,6 +207,15 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c64xx_sclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
         }, {
+                .name           = "ac97",
+                .parent         = &clk_p,
+                .ctrlbit        = S3C_CLKCON_PCLK_AC97,
+        }, {
+                .name           = "cfcon",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
+        }, {
                 .name           = "dma0",
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
@@ -216,6 +225,107 @@ static struct clk init_clocks_off[] = {
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
+        }, {
+                .name           = "3dse",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_3DSE,
+        }, {
+                .name           = "hclk_secur",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SECUR,
+        }, {
+                .name           = "sdma1",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SDMA1,
+        }, {
+                .name           = "sdma0",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SDMA0,
+        }, {
+                .name           = "hclk_jpeg",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_JPEG,
+        }, {
+                .name           = "camif",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_CAMIF,
+        }, {
+                .name           = "hclk_scaler",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SCALER,
+        }, {
+                .name           = "2d",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_2D,
+        }, {
+                .name           = "tv",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_TV,
+        }, {
+                .name           = "post0",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_POST0,
+        }, {
+                .name           = "rot",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_ROT,
+        }, {
+                .name           = "hclk_mfc",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_MFC,
+        }, {
+                .name           = "pclk_mfc",
+                .parent         = &clk_p,
+                .enable         = s3c64xx_pclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_PCLK_MFC,
+        }, {
+                .name           = "dac27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_DAC27,
+        }, {
+                .name           = "tv27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_TV27,
+        }, {
+                .name           = "scaler27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SCALER27,
+        }, {
+                .name           = "sclk_scaler",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SCALER,
+        }, {
+                .name           = "post0_27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_POST0_27,
+        }, {
+                .name           = "secur",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SECUR,
+        }, {
+                .name           = "sclk_mfc",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_MFC,
+        }, {
+                .name           = "cam",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_CAM,
+        }, {
+                .name           = "sclk_jpeg",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_JPEG,
         },
 };
 
@@ -289,16 +399,7 @@ static struct clk init_clocks[] = {
                 .name           = "watchdog",
                 .parent         = &clk_p,
                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
-        }, {
-                .name           = "ac97",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C_CLKCON_PCLK_AC97,
-        }, {
-                .name           = "cfcon",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
-        }
+        },
 };
 
 static struct clk clk_hsmmc0 = {
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
new file mode 100644
index 000000000000..179460f38db7
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -0,0 +1,91 @@
+/* linux/arch/arm/mach-s3c64xx/cpuidle.c
+ *
+ * Copyright (c) 2011 Wolfson Microelectronics, plc
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+#include <linux/export.h>
+#include <linux/time.h>
+
+#include <asm/proc-fns.h>
+
+#include <mach/map.h>
+
+#include <mach/regs-sys.h>
+#include <mach/regs-syscon-power.h>
+
+static int s3c64xx_enter_idle(struct cpuidle_device *dev,
+                              struct cpuidle_driver *drv,
+                              int index)
+{
+        struct timeval before, after;
+        unsigned long tmp;
+        int idle_time;
+
+        local_irq_disable();
+        do_gettimeofday(&before);
+
+        /* Setup PWRCFG to enter idle mode */
+        tmp = __raw_readl(S3C64XX_PWR_CFG);
+        tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+        tmp |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
+        __raw_writel(tmp, S3C64XX_PWR_CFG);
+
+        cpu_do_idle();
+
+        do_gettimeofday(&after);
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                    (after.tv_usec - before.tv_usec);
+
+        dev->last_residency = idle_time;
+        return index;
+}
+
+static struct cpuidle_state s3c64xx_cpuidle_set[] = {
+        [0] = {
+                .enter                  = s3c64xx_enter_idle,
+                .exit_latency           = 1,
+                .target_residency       = 1,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "IDLE",
+                .desc                   = "System active, ARM gated",
+        },
+};
+
+static struct cpuidle_driver s3c64xx_cpuidle_driver = {
+        .name           = "s3c64xx_cpuidle",
+        .owner          = THIS_MODULE,
+        .state_count    = ARRAY_SIZE(s3c64xx_cpuidle_set),
+};
+
+static struct cpuidle_device s3c64xx_cpuidle_device = {
+        .state_count    = ARRAY_SIZE(s3c64xx_cpuidle_set),
+};
+
+static int __init s3c64xx_init_cpuidle(void)
+{
+        int ret;
+
+        memcpy(s3c64xx_cpuidle_driver.states, s3c64xx_cpuidle_set,
+               sizeof(s3c64xx_cpuidle_set));
+        cpuidle_register_driver(&s3c64xx_cpuidle_driver);
+
+        ret = cpuidle_register_device(&s3c64xx_cpuidle_device);
+        if (ret) {
+                pr_err("Failed to register cpuidle device: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+device_initcall(s3c64xx_init_cpuidle);
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 8077f650eb0e..3b56bd9cb880 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -59,6 +59,7 @@
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
 #include <plat/s3c64xx-spi.h>
+#include <plat/udc-hs.h>
 
 #include <plat/keypad.h>
 #include <plat/clock.h>
@@ -698,6 +699,8 @@ static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
         .cfg_gpio               = crag6410_cfg_sdhci0,
 };
 
+static struct s3c_hsotg_plat crag6410_hsotg_pdata;
+
 static void __init crag6410_machine_init(void)
 {
         /* Open drain IRQs need pullups */
@@ -722,6 +725,7 @@ static void __init crag6410_machine_init(void)
         s3c_i2c0_set_platdata(&i2c0_pdata);
         s3c_i2c1_set_platdata(&i2c1_pdata);
         s3c_fb_set_platdata(&crag6410_lcd_pdata);
+        s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ce31db136231..ce745e19aa27 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -187,6 +187,8 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
         },
 };
 
+static struct s3c_hsotg_plat smartq_hsotg_pdata;
+
 static int __init smartq_lcd_setup_gpio(void)
 {
         int ret;
@@ -383,6 +385,7 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
+        s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
         s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
         s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
         s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ca6fc204f0ea..d55bc96d9582 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -72,6 +72,7 @@
 #include <plat/keypad.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include <plat/udc-hs.h>
 
 #include "common.h"
 
@@ -631,6 +632,8 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
         .pwm_id = 1,
 };
 
+static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
+
 static void __init smdk6410_map_io(void)
 {
         u32 tmp;
@@ -659,6 +662,7 @@ static void __init smdk6410_machine_init(void)
         s3c_i2c0_set_platdata(NULL);
         s3c_i2c1_set_platdata(NULL);
         s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+        s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
         samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
new file mode 100644
index 000000000000..f6757e02d7db
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+#include <plat/cpu.h>
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/usb-phy.h>
+
+static int s3c_usb_otgphy_init(struct platform_device *pdev)
+{
+        struct clk *xusbxti;
+        u32 phyclk;
+
+        writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+        /* set clock frequency for PLL */
+        phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
+
+        xusbxti = clk_get(&pdev->dev, "xusbxti");
+        if (xusbxti && !IS_ERR(xusbxti)) {
+                switch (clk_get_rate(xusbxti)) {
+                case 12 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_12M;
+                        break;
+                case 24 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_24M;
+                        break;
+                default:
+                case 48 * MHZ:
+                        /* default reference clock */
+                        break;
+                }
+                clk_put(xusbxti);
+        }
+
+        /* TODO: select external clock/oscillator */
+        writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
+
+        /* set to normal OTG PHY */
+        writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
+        mdelay(1);
+
+        /* reset OTG PHY and Link */
+        writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
+                        S3C_RSTCON);
+        udelay(20);     /* at-least 10uS */
+        writel(0, S3C_RSTCON);
+
+        return 0;
+}
+
+static int s3c_usb_otgphy_exit(struct platform_device *pdev)
+{
+        writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
+                                S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
+
+        writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+        return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s3c_usb_otgphy_init(pdev);
+
+        return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s3c_usb_otgphy_exit(pdev);
+
+        return -EINVAL;
+}