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-rw-r--r--arch/arm/mach-s3c64xx/Kconfig21
-rw-r--r--arch/arm/mach-s3c64xx/Makefile1
-rw-r--r--arch/arm/mach-s3c64xx/dev-audio.c63
-rw-r--r--arch/arm/mach-s3c64xx/gpiolib.c8
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s3c64xx/mach-mini6410.c357
-rw-r--r--arch/arm/mach-s3c64xx/mach-real6410.c198
-rw-r--r--arch/arm/mach-s3c64xx/setup-fb-24bpp.c13
-rw-r--r--arch/arm/mach-s3c64xx/setup-ide.c11
-rw-r--r--arch/arm/mach-s3c64xx/setup-keypad.c16
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci-gpio.c41
11 files changed, 609 insertions, 122 deletions
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 546db5cb8929..1ca7bdc6485c 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -98,12 +98,33 @@ config MACH_ANW6410
98 help 98 help
99 Machine support for the A&W6410 99 Machine support for the A&W6410
100 100
101config MACH_MINI6410
102 bool "MINI6410"
103 select CPU_S3C6410
104 select S3C_DEV_HSMMC
105 select S3C_DEV_HSMMC1
106 select S3C64XX_SETUP_SDHCI
107 select S3C_DEV_USB_HOST
108 select S3C_DEV_NAND
109 select S3C_DEV_FB
110 select S3C64XX_SETUP_FB_24BPP
111 select SAMSUNG_DEV_ADC
112 select SAMSUNG_DEV_TS
113 help
114 Machine support for the FriendlyARM MINI6410
115
101config MACH_REAL6410 116config MACH_REAL6410
102 bool "REAL6410" 117 bool "REAL6410"
103 select CPU_S3C6410 118 select CPU_S3C6410
104 select S3C_DEV_HSMMC 119 select S3C_DEV_HSMMC
105 select S3C_DEV_HSMMC1 120 select S3C_DEV_HSMMC1
106 select S3C64XX_SETUP_SDHCI 121 select S3C64XX_SETUP_SDHCI
122 select S3C_DEV_FB
123 select S3C64XX_SETUP_FB_24BPP
124 select S3C_DEV_NAND
125 select SAMSUNG_DEV_ADC
126 select SAMSUNG_DEV_TS
127 select S3C_DEV_USB_HOST
107 help 128 help
108 Machine support for the CoreWind REAL6410 129 Machine support for the CoreWind REAL6410
109 130
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 90221a2e0c55..4657363f0674 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
53obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o 53obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
54obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o 54obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
55obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o 55obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
56obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
56obj-$(CONFIG_MACH_NCP) += mach-ncp.o 57obj-$(CONFIG_MACH_NCP) += mach-ncp.o
57obj-$(CONFIG_MACH_HMT) += mach-hmt.o 58obj-$(CONFIG_MACH_HMT) += mach-hmt.o
58obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o 59obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index 3838335f125b..76426a32c013 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -22,27 +22,16 @@
22#include <plat/audio.h> 22#include <plat/audio.h>
23#include <plat/gpio-cfg.h> 23#include <plat/gpio-cfg.h>
24 24
25#include <mach/gpio-bank-c.h>
26#include <mach/gpio-bank-d.h>
27#include <mach/gpio-bank-e.h>
28#include <mach/gpio-bank-h.h>
29
30static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) 25static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
31{ 26{
27 unsigned int base;
28
32 switch (pdev->id) { 29 switch (pdev->id) {
33 case 0: 30 case 0:
34 s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK); 31 base = S3C64XX_GPD(0);
35 s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
36 s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
37 s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
38 s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
39 break; 32 break;
40 case 1: 33 case 1:
41 s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK); 34 base = S3C64XX_GPE(0);
42 s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
43 s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
44 s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
45 s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
46 break; 35 break;
47 default: 36 default:
48 printk(KERN_DEBUG "Invalid I2S Controller number: %d\n", 37 printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
@@ -50,18 +39,17 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
50 return -EINVAL; 39 return -EINVAL;
51 } 40 }
52 41
42 s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
43
53 return 0; 44 return 0;
54} 45}
55 46
56static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev) 47static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
57{ 48{
58 s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); 49 s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
59 s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); 50 s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
60 s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); 51 s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
61 s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); 52 s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
62 s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
63 s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
64 s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
65 53
66 return 0; 54 return 0;
67} 55}
@@ -170,20 +158,14 @@ EXPORT_SYMBOL(s3c64xx_device_iisv4);
170 158
171static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev) 159static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
172{ 160{
161 unsigned int base;
162
173 switch (pdev->id) { 163 switch (pdev->id) {
174 case 0: 164 case 0:
175 s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_PCM0_SCLK); 165 base = S3C64XX_GPD(0);
176 s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_PCM0_EXTCLK);
177 s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_PCM0_FSYNC);
178 s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_PCM0_SIN);
179 s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_PCM0_SOUT);
180 break; 166 break;
181 case 1: 167 case 1:
182 s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_PCM1_SCLK); 168 base = S3C64XX_GPE(0);
183 s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_PCM1_EXTCLK);
184 s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_PCM1_FSYNC);
185 s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_PCM1_SIN);
186 s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
187 break; 169 break;
188 default: 170 default:
189 printk(KERN_DEBUG "Invalid PCM Controller number: %d\n", 171 printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
@@ -191,6 +173,7 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
191 return -EINVAL; 173 return -EINVAL;
192 } 174 }
193 175
176 s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
194 return 0; 177 return 0;
195} 178}
196 179
@@ -264,24 +247,12 @@ EXPORT_SYMBOL(s3c64xx_device_pcm1);
264 247
265static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev) 248static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
266{ 249{
267 s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_AC97_BITCLK); 250 return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
268 s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_AC97_nRESET);
269 s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_AC97_SYNC);
270 s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_AC97_SDI);
271 s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_AC97_SDO);
272
273 return 0;
274} 251}
275 252
276static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev) 253static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
277{ 254{
278 s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_AC97_BITCLK); 255 return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
279 s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_AC97_nRESET);
280 s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_AC97_SYNC);
281 s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_AC97_SDI);
282 s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_AC97_SDO);
283
284 return 0;
285} 256}
286 257
287static struct resource s3c64xx_ac97_resource[] = { 258static struct resource s3c64xx_ac97_resource[] = {
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
index 300dee4a667b..fd99a82e82c4 100644
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -195,11 +195,6 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
195 .get_pull = s3c_gpio_getpull_updown, 195 .get_pull = s3c_gpio_getpull_updown,
196}; 196};
197 197
198int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
199{
200 return IRQ_EINT(0) + pin;
201}
202
203static struct s3c_gpio_chip gpio_2bit[] = { 198static struct s3c_gpio_chip gpio_2bit[] = {
204 { 199 {
205 .base = S3C64XX_GPF_BASE, 200 .base = S3C64XX_GPF_BASE,
@@ -227,12 +222,13 @@ static struct s3c_gpio_chip gpio_2bit[] = {
227 }, 222 },
228 }, { 223 }, {
229 .base = S3C64XX_GPN_BASE, 224 .base = S3C64XX_GPN_BASE,
225 .irq_base = IRQ_EINT(0),
230 .config = &gpio_2bit_cfg_eint10, 226 .config = &gpio_2bit_cfg_eint10,
231 .chip = { 227 .chip = {
232 .base = S3C64XX_GPN(0), 228 .base = S3C64XX_GPN(0),
233 .ngpio = S3C64XX_GPIO_N_NR, 229 .ngpio = S3C64XX_GPIO_N_NR,
234 .label = "GPN", 230 .label = "GPN",
235 .to_irq = s3c64xx_gpio2int_gpn, 231 .to_irq = samsung_gpiolib_to_irq,
236 }, 232 },
237 }, { 233 }, {
238 .base = S3C64XX_GPO_BASE, 234 .base = S3C64XX_GPO_BASE,
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
index bc0e91389864..23f75e556a30 100644
--- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
15#ifndef __ASM_ARCH_VMALLOC_H 15#ifndef __ASM_ARCH_VMALLOC_H
16#define __ASM_ARCH_VMALLOC_H 16#define __ASM_ARCH_VMALLOC_H
17 17
18#define VMALLOC_END 0xE0000000UL 18#define VMALLOC_END 0xF6000000UL
19 19
20#endif /* __ASM_ARCH_VMALLOC_H */ 20#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
new file mode 100644
index 000000000000..249c62956471
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -0,0 +1,357 @@
1/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
2 *
3 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13*/
14
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/fb.h>
18#include <linux/gpio.h>
19#include <linux/kernel.h>
20#include <linux/list.h>
21#include <linux/dm9000.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/partitions.h>
24#include <linux/serial_core.h>
25#include <linux/types.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30
31#include <mach/map.h>
32#include <mach/regs-fb.h>
33#include <mach/regs-gpio.h>
34#include <mach/regs-modem.h>
35#include <mach/regs-srom.h>
36#include <mach/s3c6410.h>
37
38#include <plat/adc.h>
39#include <plat/cpu.h>
40#include <plat/devs.h>
41#include <plat/fb.h>
42#include <plat/nand.h>
43#include <plat/regs-serial.h>
44#include <plat/ts.h>
45
46#include <video/platform_lcd.h>
47
48#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
49#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
50#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
51
52static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
53 [0] = {
54 .hwport = 0,
55 .flags = 0,
56 .ucon = UCON,
57 .ulcon = ULCON,
58 .ufcon = UFCON,
59 },
60 [1] = {
61 .hwport = 1,
62 .flags = 0,
63 .ucon = UCON,
64 .ulcon = ULCON,
65 .ufcon = UFCON,
66 },
67 [2] = {
68 .hwport = 2,
69 .flags = 0,
70 .ucon = UCON,
71 .ulcon = ULCON,
72 .ufcon = UFCON,
73 },
74 [3] = {
75 .hwport = 3,
76 .flags = 0,
77 .ucon = UCON,
78 .ulcon = ULCON,
79 .ufcon = UFCON,
80 },
81};
82
83/* DM9000AEP 10/100 ethernet controller */
84
85static struct resource mini6410_dm9k_resource[] = {
86 [0] = {
87 .start = S3C64XX_PA_XM0CSN1,
88 .end = S3C64XX_PA_XM0CSN1 + 1,
89 .flags = IORESOURCE_MEM
90 },
91 [1] = {
92 .start = S3C64XX_PA_XM0CSN1 + 4,
93 .end = S3C64XX_PA_XM0CSN1 + 5,
94 .flags = IORESOURCE_MEM
95 },
96 [2] = {
97 .start = S3C_EINT(7),
98 .end = S3C_EINT(7),
99 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
100 }
101};
102
103static struct dm9000_plat_data mini6410_dm9k_pdata = {
104 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
105};
106
107static struct platform_device mini6410_device_eth = {
108 .name = "dm9000",
109 .id = -1,
110 .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
111 .resource = mini6410_dm9k_resource,
112 .dev = {
113 .platform_data = &mini6410_dm9k_pdata,
114 },
115};
116
117static struct mtd_partition mini6410_nand_part[] = {
118 [0] = {
119 .name = "uboot",
120 .size = SZ_1M,
121 .offset = 0,
122 },
123 [1] = {
124 .name = "kernel",
125 .size = SZ_2M,
126 .offset = SZ_1M,
127 },
128 [2] = {
129 .name = "rootfs",
130 .size = MTDPART_SIZ_FULL,
131 .offset = SZ_1M + SZ_2M,
132 },
133};
134
135static struct s3c2410_nand_set mini6410_nand_sets[] = {
136 [0] = {
137 .name = "nand",
138 .nr_chips = 1,
139 .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
140 .partitions = mini6410_nand_part,
141 },
142};
143
144static struct s3c2410_platform_nand mini6410_nand_info = {
145 .tacls = 25,
146 .twrph0 = 55,
147 .twrph1 = 40,
148 .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
149 .sets = mini6410_nand_sets,
150};
151
152static struct s3c_fb_pd_win mini6410_fb_win[] = {
153 {
154 .win_mode = { /* 4.3" 480x272 */
155 .left_margin = 3,
156 .right_margin = 2,
157 .upper_margin = 1,
158 .lower_margin = 1,
159 .hsync_len = 40,
160 .vsync_len = 1,
161 .xres = 480,
162 .yres = 272,
163 },
164 .max_bpp = 32,
165 .default_bpp = 16,
166 }, {
167 .win_mode = { /* 7.0" 800x480 */
168 .left_margin = 8,
169 .right_margin = 13,
170 .upper_margin = 7,
171 .lower_margin = 5,
172 .hsync_len = 3,
173 .vsync_len = 1,
174 .xres = 800,
175 .yres = 480,
176 },
177 .max_bpp = 32,
178 .default_bpp = 16,
179 },
180};
181
182static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
183 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
184 .win[0] = &mini6410_fb_win[0],
185 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
186 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
187};
188
189static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
190 unsigned int power)
191{
192 if (power)
193 gpio_direction_output(S3C64XX_GPE(0), 1);
194 else
195 gpio_direction_output(S3C64XX_GPE(0), 0);
196}
197
198static struct plat_lcd_data mini6410_lcd_power_data = {
199 .set_power = mini6410_lcd_power_set,
200};
201
202static struct platform_device mini6410_lcd_powerdev = {
203 .name = "platform-lcd",
204 .dev.parent = &s3c_device_fb.dev,
205 .dev.platform_data = &mini6410_lcd_power_data,
206};
207
208static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
209 .delay = 10000,
210 .presc = 49,
211 .oversampling_shift = 2,
212};
213
214static struct platform_device *mini6410_devices[] __initdata = {
215 &mini6410_device_eth,
216 &s3c_device_hsmmc0,
217 &s3c_device_hsmmc1,
218 &s3c_device_ohci,
219 &s3c_device_nand,
220 &s3c_device_fb,
221 &mini6410_lcd_powerdev,
222 &s3c_device_adc,
223 &s3c_device_ts,
224};
225
226static void __init mini6410_map_io(void)
227{
228 u32 tmp;
229
230 s3c64xx_init_io(NULL, 0);
231 s3c24xx_init_clocks(12000000);
232 s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
233
234 /* set the LCD type */
235 tmp = __raw_readl(S3C64XX_SPCON);
236 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
237 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
238 __raw_writel(tmp, S3C64XX_SPCON);
239
240 /* remove the LCD bypass */
241 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
242 tmp &= ~MIFPCON_LCD_BYPASS;
243 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
244}
245
246/*
247 * mini6410_features string
248 *
249 * 0-9 LCD configuration
250 *
251 */
252static char mini6410_features_str[12] __initdata = "0";
253
254static int __init mini6410_features_setup(char *str)
255{
256 if (str)
257 strlcpy(mini6410_features_str, str,
258 sizeof(mini6410_features_str));
259 return 1;
260}
261
262__setup("mini6410=", mini6410_features_setup);
263
264#define FEATURE_SCREEN (1 << 0)
265
266struct mini6410_features_t {
267 int done;
268 int lcd_index;
269};
270
271static void mini6410_parse_features(
272 struct mini6410_features_t *features,
273 const char *features_str)
274{
275 const char *fp = features_str;
276
277 features->done = 0;
278 features->lcd_index = 0;
279
280 while (*fp) {
281 char f = *fp++;
282
283 switch (f) {
284 case '0'...'9': /* tft screen */
285 if (features->done & FEATURE_SCREEN) {
286 printk(KERN_INFO "MINI6410: '%c' ignored, "
287 "screen type already set\n", f);
288 } else {
289 int li = f - '0';
290 if (li >= ARRAY_SIZE(mini6410_fb_win))
291 printk(KERN_INFO "MINI6410: '%c' out "
292 "of range LCD mode\n", f);
293 else {
294 features->lcd_index = li;
295 }
296 }
297 features->done |= FEATURE_SCREEN;
298 break;
299 }
300 }
301}
302
303static void __init mini6410_machine_init(void)
304{
305 u32 cs1;
306 struct mini6410_features_t features = { 0 };
307
308 printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
309 mini6410_features_str);
310
311 /* Parse the feature string */
312 mini6410_parse_features(&features, mini6410_features_str);
313
314 mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
315
316 printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
317 mini6410_lcd_pdata.win[0]->win_mode.xres,
318 mini6410_lcd_pdata.win[0]->win_mode.yres);
319
320 s3c_nand_set_platdata(&mini6410_nand_info);
321 s3c_fb_set_platdata(&mini6410_lcd_pdata);
322 s3c24xx_ts_set_platdata(&s3c_ts_platform);
323
324 /* configure nCS1 width to 16 bits */
325
326 cs1 = __raw_readl(S3C64XX_SROM_BW) &
327 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
328 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
329 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
330 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
331 S3C64XX_SROM_BW__NCS1__SHIFT;
332 __raw_writel(cs1, S3C64XX_SROM_BW);
333
334 /* set timing for nCS1 suitable for ethernet chip */
335
336 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
337 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
338 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
339 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
340 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
341 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
342 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
343
344 gpio_request(S3C64XX_GPF(15), "LCD power");
345 gpio_request(S3C64XX_GPE(0), "LCD power");
346
347 platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
348}
349
350MACHINE_START(MINI6410, "MINI6410")
351 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
352 .boot_params = S3C64XX_PA_SDRAM + 0x100,
353 .init_irq = s3c6410_init_irq,
354 .map_io = mini6410_map_io,
355 .init_machine = mini6410_machine_init,
356 .timer = &s3c24xx_timer,
357MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 4b4475da8ec6..f9ef9b5c5f5a 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -12,23 +12,39 @@
12 * 12 *
13*/ 13*/
14 14
15#include <linux/kernel.h> 15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/fb.h>
18#include <linux/gpio.h>
19#include <linux/kernel.h>
18#include <linux/list.h> 20#include <linux/list.h>
19#include <linux/init.h>
20#include <linux/dm9000.h> 21#include <linux/dm9000.h>
21#include <linux/serial_core.h> 22#include <linux/mtd/mtd.h>
23#include <linux/mtd/partitions.h>
22#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/serial_core.h>
26#include <linux/types.h>
27
23#include <asm/mach-types.h> 28#include <asm/mach-types.h>
24#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 30#include <asm/mach/map.h>
31
26#include <mach/map.h> 32#include <mach/map.h>
27#include <mach/s3c6410.h> 33#include <mach/regs-fb.h>
34#include <mach/regs-gpio.h>
35#include <mach/regs-modem.h>
28#include <mach/regs-srom.h> 36#include <mach/regs-srom.h>
37#include <mach/s3c6410.h>
38
39#include <plat/adc.h>
29#include <plat/cpu.h> 40#include <plat/cpu.h>
30#include <plat/devs.h> 41#include <plat/devs.h>
42#include <plat/fb.h>
43#include <plat/nand.h>
31#include <plat/regs-serial.h> 44#include <plat/regs-serial.h>
45#include <plat/ts.h>
46
47#include <video/platform_lcd.h>
32 48
33#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) 49#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
34#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) 50#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -99,22 +115,192 @@ static struct platform_device real6410_device_eth = {
99 }, 115 },
100}; 116};
101 117
118static struct s3c_fb_pd_win real6410_fb_win[] = {
119 {
120 .win_mode = { /* 4.3" 480x272 */
121 .left_margin = 3,
122 .right_margin = 2,
123 .upper_margin = 1,
124 .lower_margin = 1,
125 .hsync_len = 40,
126 .vsync_len = 1,
127 .xres = 480,
128 .yres = 272,
129 },
130 .max_bpp = 32,
131 .default_bpp = 16,
132 }, {
133 .win_mode = { /* 7.0" 800x480 */
134 .left_margin = 8,
135 .right_margin = 13,
136 .upper_margin = 7,
137 .lower_margin = 5,
138 .hsync_len = 3,
139 .vsync_len = 1,
140 .xres = 800,
141 .yres = 480,
142 },
143 .max_bpp = 32,
144 .default_bpp = 16,
145 },
146};
147
148static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
149 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
150 .win[0] = &real6410_fb_win[0],
151 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
152 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
153};
154
155static struct mtd_partition real6410_nand_part[] = {
156 [0] = {
157 .name = "uboot",
158 .size = SZ_1M,
159 .offset = 0,
160 },
161 [1] = {
162 .name = "kernel",
163 .size = SZ_2M,
164 .offset = SZ_1M,
165 },
166 [2] = {
167 .name = "rootfs",
168 .size = MTDPART_SIZ_FULL,
169 .offset = SZ_1M + SZ_2M,
170 },
171};
172
173static struct s3c2410_nand_set real6410_nand_sets[] = {
174 [0] = {
175 .name = "nand",
176 .nr_chips = 1,
177 .nr_partitions = ARRAY_SIZE(real6410_nand_part),
178 .partitions = real6410_nand_part,
179 },
180};
181
182static struct s3c2410_platform_nand real6410_nand_info = {
183 .tacls = 25,
184 .twrph0 = 55,
185 .twrph1 = 40,
186 .nr_sets = ARRAY_SIZE(real6410_nand_sets),
187 .sets = real6410_nand_sets,
188};
189
102static struct platform_device *real6410_devices[] __initdata = { 190static struct platform_device *real6410_devices[] __initdata = {
103 &real6410_device_eth, 191 &real6410_device_eth,
104 &s3c_device_hsmmc0, 192 &s3c_device_hsmmc0,
105 &s3c_device_hsmmc1, 193 &s3c_device_hsmmc1,
194 &s3c_device_fb,
195 &s3c_device_nand,
196 &s3c_device_adc,
197 &s3c_device_ts,
198 &s3c_device_ohci,
199};
200
201static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
202 .delay = 10000,
203 .presc = 49,
204 .oversampling_shift = 2,
106}; 205};
107 206
108static void __init real6410_map_io(void) 207static void __init real6410_map_io(void)
109{ 208{
209 u32 tmp;
210
110 s3c64xx_init_io(NULL, 0); 211 s3c64xx_init_io(NULL, 0);
111 s3c24xx_init_clocks(12000000); 212 s3c24xx_init_clocks(12000000);
112 s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs)); 213 s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
214
215 /* set the LCD type */
216 tmp = __raw_readl(S3C64XX_SPCON);
217 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
218 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
219 __raw_writel(tmp, S3C64XX_SPCON);
220
221 /* remove the LCD bypass */
222 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
223 tmp &= ~MIFPCON_LCD_BYPASS;
224 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
225}
226
227/*
228 * real6410_features string
229 *
230 * 0-9 LCD configuration
231 *
232 */
233static char real6410_features_str[12] __initdata = "0";
234
235static int __init real6410_features_setup(char *str)
236{
237 if (str)
238 strlcpy(real6410_features_str, str,
239 sizeof(real6410_features_str));
240 return 1;
241}
242
243__setup("real6410=", real6410_features_setup);
244
245#define FEATURE_SCREEN (1 << 0)
246
247struct real6410_features_t {
248 int done;
249 int lcd_index;
250};
251
252static void real6410_parse_features(
253 struct real6410_features_t *features,
254 const char *features_str)
255{
256 const char *fp = features_str;
257
258 features->done = 0;
259 features->lcd_index = 0;
260
261 while (*fp) {
262 char f = *fp++;
263
264 switch (f) {
265 case '0'...'9': /* tft screen */
266 if (features->done & FEATURE_SCREEN) {
267 printk(KERN_INFO "REAL6410: '%c' ignored, "
268 "screen type already set\n", f);
269 } else {
270 int li = f - '0';
271 if (li >= ARRAY_SIZE(real6410_fb_win))
272 printk(KERN_INFO "REAL6410: '%c' out "
273 "of range LCD mode\n", f);
274 else {
275 features->lcd_index = li;
276 }
277 }
278 features->done |= FEATURE_SCREEN;
279 break;
280 }
281 }
113} 282}
114 283
115static void __init real6410_machine_init(void) 284static void __init real6410_machine_init(void)
116{ 285{
117 u32 cs1; 286 u32 cs1;
287 struct real6410_features_t features = { 0 };
288
289 printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
290 real6410_features_str);
291
292 /* Parse the feature string */
293 real6410_parse_features(&features, real6410_features_str);
294
295 real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
296
297 printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
298 real6410_lcd_pdata.win[0]->win_mode.xres,
299 real6410_lcd_pdata.win[0]->win_mode.yres);
300
301 s3c_fb_set_platdata(&real6410_lcd_pdata);
302 s3c_nand_set_platdata(&real6410_nand_info);
303 s3c24xx_ts_set_platdata(&s3c_ts_platform);
118 304
119 /* configure nCS1 width to 16 bits */ 305 /* configure nCS1 width to 16 bits */
120 306
@@ -136,6 +322,8 @@ static void __init real6410_machine_init(void)
136 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | 322 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
137 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); 323 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
138 324
325 gpio_request(S3C64XX_GPF(15), "LCD power");
326
139 platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices)); 327 platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
140} 328}
141 329
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
index 000736877df2..8f3091182f9c 100644
--- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
+++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
@@ -23,15 +23,6 @@
23 23
24extern void s3c64xx_fb_gpio_setup_24bpp(void) 24extern void s3c64xx_fb_gpio_setup_24bpp(void)
25{ 25{
26 unsigned int gpio; 26 s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2));
27 27 s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2));
28 for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
29 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
30 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
31 }
32
33 for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
34 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
35 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
36 }
37} 28}
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c
index c12c315f33bc..41b425602d88 100644
--- a/arch/arm/mach-s3c64xx/setup-ide.c
+++ b/arch/arm/mach-s3c64xx/setup-ide.c
@@ -17,11 +17,11 @@
17#include <mach/map.h> 17#include <mach/map.h>
18#include <mach/regs-clock.h> 18#include <mach/regs-clock.h>
19#include <plat/gpio-cfg.h> 19#include <plat/gpio-cfg.h>
20#include <plat/ata.h>
20 21
21void s3c64xx_ide_setup_gpio(void) 22void s3c64xx_ide_setup_gpio(void)
22{ 23{
23 u32 reg; 24 u32 reg;
24 u32 gpio = 0;
25 25
26 reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); 26 reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
27 27
@@ -32,15 +32,12 @@ void s3c64xx_ide_setup_gpio(void)
32 s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4)); 32 s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
33 33
34 /* Set XhiDATA[15:0] pins as CF Data[15:0] */ 34 /* Set XhiDATA[15:0] pins as CF Data[15:0] */
35 for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++) 35 s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
36 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
37 36
38 /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */ 37 /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
39 for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++) 38 s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
40 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
41 39
42 /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */ 40 /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
43 s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1)); 41 s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
44 for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++) 42 s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
45 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
46} 43}
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c
index abc34e4e1a93..f8ed0d22db70 100644
--- a/arch/arm/mach-s3c64xx/setup-keypad.c
+++ b/arch/arm/mach-s3c64xx/setup-keypad.c
@@ -12,23 +12,13 @@
12 12
13#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <plat/gpio-cfg.h> 14#include <plat/gpio-cfg.h>
15#include <plat/keypad.h>
15 16
16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) 17void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
17{ 18{
18 unsigned int gpio;
19 unsigned int end;
20
21 /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */ 19 /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
22 end = S3C64XX_GPK(8 + rows); 20 s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
23 for (gpio = S3C64XX_GPK(8); gpio < end; gpio++) {
24 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
25 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
26 }
27 21
28 /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */ 22 /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
29 end = S3C64XX_GPL(0 + cols); 23 s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
30 for (gpio = S3C64XX_GPL(0); gpio < end; gpio++) {
31 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
32 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
33 }
34} 24}
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
index 322359591374..6eac071afae2 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
@@ -24,16 +24,9 @@
24void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) 24void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{ 25{
26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
27 unsigned int gpio;
28 unsigned int end;
29 27
30 end = S3C64XX_GPG(2 + width); 28 /* Set all the necessary GPG pins to special-function 2 */
31 29 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
32 /* Set all the necessary GPG pins to special-function 0 */
33 for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
34 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
35 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
36 }
37 30
38 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 31 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
39 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); 32 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
@@ -44,16 +37,9 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
44void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) 37void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
45{ 38{
46 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 39 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
47 unsigned int gpio;
48 unsigned int end;
49 40
50 end = S3C64XX_GPH(2 + width); 41 /* Set all the necessary GPH pins to special-function 2 */
51 42 s3c_gpio_cfgrange_nopull(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2));
52 /* Set all the necessary GPG pins to special-function 0 */
53 for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
54 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
55 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
56 }
57 43
58 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 44 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
59 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); 45 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
@@ -63,20 +49,9 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
63 49
64void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) 50void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
65{ 51{
66 unsigned int gpio; 52 /* Set all the necessary GPH pins to special-function 3 */
67 unsigned int end; 53 s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3));
68 54
69 end = S3C64XX_GPH(6 + width); 55 /* Set all the necessary GPC pins to special-function 3 */
70 56 s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3));
71 /* Set all the necessary GPH pins to special-function 1 */
72 for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
73 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
74 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
75 }
76
77 /* Set all the necessary GPC pins to special-function 1 */
78 for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
79 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
80 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
81 }
82} 57}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 07:00:11 -0500