diff options
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h')
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h deleted file mode 100644 index 21868fa102d0..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h +++ /dev/null | |||
| @@ -1,70 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * GPIO Bank O register and configuration definitions | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00) | ||
| 16 | #define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04) | ||
| 17 | #define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08) | ||
| 18 | #define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c) | ||
| 19 | #define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10) | ||
| 20 | |||
| 21 | #define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
| 22 | #define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
| 23 | #define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
| 24 | |||
| 25 | #define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0) | ||
| 26 | #define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0) | ||
| 27 | |||
| 28 | #define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2) | ||
| 29 | #define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2) | ||
| 30 | |||
| 31 | #define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4) | ||
| 32 | #define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4) | ||
| 33 | |||
| 34 | #define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6) | ||
| 35 | #define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6) | ||
| 36 | |||
| 37 | #define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8) | ||
| 38 | |||
| 39 | #define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10) | ||
| 40 | |||
| 41 | #define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12) | ||
| 42 | #define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12) | ||
| 43 | |||
| 44 | #define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14) | ||
| 45 | #define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14) | ||
| 46 | |||
| 47 | #define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16) | ||
| 48 | #define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16) | ||
| 49 | |||
| 50 | #define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18) | ||
| 51 | #define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18) | ||
| 52 | |||
| 53 | #define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20) | ||
| 54 | #define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20) | ||
| 55 | |||
| 56 | #define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22) | ||
| 57 | #define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22) | ||
| 58 | |||
| 59 | #define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24) | ||
| 60 | #define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24) | ||
| 61 | |||
| 62 | #define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26) | ||
| 63 | #define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26) | ||
| 64 | |||
| 65 | #define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28) | ||
| 66 | #define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28) | ||
| 67 | |||
| 68 | #define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30) | ||
| 69 | #define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30) | ||
| 70 | |||