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Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h')
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h74
1 files changed, 0 insertions, 74 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
deleted file mode 100644
index 5d75aaad865e..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
+++ /dev/null
@@ -1,74 +0,0 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank H register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
16#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
17#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
18#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
19#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
20#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
21
22#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
23#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
24#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
25
26#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
27#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
28#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
29
30#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
31#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
32#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
33
34#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
35#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
36#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
37
38#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
39#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
40#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
41
42#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
43#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
44#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
45
46#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
47#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
48#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
49
50#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
51#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
52#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
53#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
54#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
55#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
56
57#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
58#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
59#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
60#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
61#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
62#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
63
64#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
65#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
66#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
67#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
68#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
69
70#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
71#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
72#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
73#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
74#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)