diff options
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h')
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h deleted file mode 100644 index f057adb627dd..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * GPIO Bank E register and configuration definitions | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) | ||
| 16 | #define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) | ||
| 17 | #define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) | ||
| 18 | #define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) | ||
| 19 | #define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) | ||
| 20 | |||
| 21 | #define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
| 22 | #define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
| 23 | #define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
| 24 | |||
| 25 | #define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) | ||
| 26 | #define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) | ||
| 27 | #define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) | ||
| 28 | |||
| 29 | #define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) | ||
| 30 | #define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) | ||
| 31 | #define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) | ||
| 32 | |||
| 33 | #define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) | ||
| 34 | #define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) | ||
| 35 | #define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) | ||
| 36 | |||
| 37 | #define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) | ||
| 38 | #define S3C64XX_GPE3_I2S1_DI (0x03 << 12) | ||
| 39 | #define S3C64XX_GPE3_AC97_SDI (0x04 << 12) | ||
| 40 | |||
| 41 | #define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) | ||
| 42 | #define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) | ||
| 43 | #define S3C64XX_GPE4_AC97_SDO (0x04 << 16) | ||
| 44 | |||