diff options
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h')
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h deleted file mode 100644 index 7232c037e642..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * GPIO Bank B register and configuration definitions | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00) | ||
| 16 | #define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04) | ||
| 17 | #define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08) | ||
| 18 | #define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c) | ||
| 19 | #define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10) | ||
| 20 | |||
| 21 | #define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
| 22 | #define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
| 23 | #define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
| 24 | |||
| 25 | #define S3C64XX_GPB0_UART_RXD2 (0x02 << 0) | ||
| 26 | #define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0) | ||
| 27 | #define S3C64XX_GPB0_IrDA_RXD (0x04 << 0) | ||
| 28 | #define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0) | ||
| 29 | #define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0) | ||
| 30 | |||
| 31 | #define S3C64XX_GPB1_UART_TXD2 (0x02 << 4) | ||
| 32 | #define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4) | ||
| 33 | #define S3C64XX_GPB1_IrDA_TXD (0x04 << 4) | ||
| 34 | #define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4) | ||
| 35 | #define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4) | ||
| 36 | |||
| 37 | #define S3C64XX_GPB2_UART_RXD3 (0x02 << 8) | ||
| 38 | #define S3C64XX_GPB2_IrDA_RXD (0x03 << 8) | ||
| 39 | #define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8) | ||
| 40 | #define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8) | ||
| 41 | #define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8) | ||
| 42 | #define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8) | ||
| 43 | |||
| 44 | #define S3C64XX_GPB3_UART_TXD3 (0x02 << 12) | ||
| 45 | #define S3C64XX_GPB3_IrDA_TXD (0x03 << 12) | ||
| 46 | #define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12) | ||
| 47 | #define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12) | ||
| 48 | #define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12) | ||
| 49 | |||
| 50 | #define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16) | ||
| 51 | #define S3C64XX_GPB4_CAM_FIELD (0x03 << 16) | ||
| 52 | #define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16) | ||
| 53 | #define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16) | ||
| 54 | |||
| 55 | #define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20) | ||
| 56 | #define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20) | ||
| 57 | |||
| 58 | #define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24) | ||
| 59 | #define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24) | ||
| 60 | |||