diff options
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/dma.h')
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/dma.h | 144 |
1 files changed, 42 insertions, 102 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index fe1a98cf0e4c..059b1fc85037 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h | |||
| @@ -11,51 +11,48 @@ | |||
| 11 | #ifndef __ASM_ARCH_DMA_H | 11 | #ifndef __ASM_ARCH_DMA_H |
| 12 | #define __ASM_ARCH_DMA_H __FILE__ | 12 | #define __ASM_ARCH_DMA_H __FILE__ |
| 13 | 13 | ||
| 14 | #define S3C_DMA_CHANNELS (16) | 14 | #define S3C64XX_DMA_CHAN(name) ((unsigned long)(name)) |
| 15 | |||
| 16 | /* DMA0/SDMA0 */ | ||
| 17 | #define DMACH_UART0 S3C64XX_DMA_CHAN("uart0_tx") | ||
| 18 | #define DMACH_UART0_SRC2 S3C64XX_DMA_CHAN("uart0_rx") | ||
| 19 | #define DMACH_UART1 S3C64XX_DMA_CHAN("uart1_tx") | ||
| 20 | #define DMACH_UART1_SRC2 S3C64XX_DMA_CHAN("uart1_rx") | ||
| 21 | #define DMACH_UART2 S3C64XX_DMA_CHAN("uart2_tx") | ||
| 22 | #define DMACH_UART2_SRC2 S3C64XX_DMA_CHAN("uart2_rx") | ||
| 23 | #define DMACH_UART3 S3C64XX_DMA_CHAN("uart3_tx") | ||
| 24 | #define DMACH_UART3_SRC2 S3C64XX_DMA_CHAN("uart3_rx") | ||
| 25 | #define DMACH_PCM0_TX S3C64XX_DMA_CHAN("pcm0_tx") | ||
| 26 | #define DMACH_PCM0_RX S3C64XX_DMA_CHAN("pcm0_rx") | ||
| 27 | #define DMACH_I2S0_OUT S3C64XX_DMA_CHAN("i2s0_tx") | ||
| 28 | #define DMACH_I2S0_IN S3C64XX_DMA_CHAN("i2s0_rx") | ||
| 29 | #define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx") | ||
| 30 | #define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx") | ||
| 31 | #define DMACH_HSI_I2SV40_TX S3C64XX_DMA_CHAN("i2s2_tx") | ||
| 32 | #define DMACH_HSI_I2SV40_RX S3C64XX_DMA_CHAN("i2s2_rx") | ||
| 33 | |||
| 34 | /* DMA1/SDMA1 */ | ||
| 35 | #define DMACH_PCM1_TX S3C64XX_DMA_CHAN("pcm1_tx") | ||
| 36 | #define DMACH_PCM1_RX S3C64XX_DMA_CHAN("pcm1_rx") | ||
| 37 | #define DMACH_I2S1_OUT S3C64XX_DMA_CHAN("i2s1_tx") | ||
| 38 | #define DMACH_I2S1_IN S3C64XX_DMA_CHAN("i2s1_rx") | ||
| 39 | #define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx") | ||
| 40 | #define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx") | ||
| 41 | #define DMACH_AC97_PCMOUT S3C64XX_DMA_CHAN("ac97_out") | ||
| 42 | #define DMACH_AC97_PCMIN S3C64XX_DMA_CHAN("ac97_in") | ||
| 43 | #define DMACH_AC97_MICIN S3C64XX_DMA_CHAN("ac97_mic") | ||
| 44 | #define DMACH_PWM S3C64XX_DMA_CHAN("pwm") | ||
| 45 | #define DMACH_IRDA S3C64XX_DMA_CHAN("irda") | ||
| 46 | #define DMACH_EXTERNAL S3C64XX_DMA_CHAN("external") | ||
| 47 | #define DMACH_SECURITY_RX S3C64XX_DMA_CHAN("sec_rx") | ||
| 48 | #define DMACH_SECURITY_TX S3C64XX_DMA_CHAN("sec_tx") | ||
| 15 | 49 | ||
| 16 | /* see mach-s3c2410/dma.h for notes on dma channel numbers */ | ||
| 17 | |||
| 18 | /* Note, for the S3C64XX architecture we keep the DMACH_ | ||
| 19 | * defines in the order they are allocated to [S]DMA0/[S]DMA1 | ||
| 20 | * so that is easy to do DHACH_ -> DMA controller conversion | ||
| 21 | */ | ||
| 22 | enum dma_ch { | 50 | enum dma_ch { |
| 23 | /* DMA0/SDMA0 */ | 51 | DMACH_MAX = 32 |
| 24 | DMACH_UART0 = 0, | 52 | }; |
| 25 | DMACH_UART0_SRC2, | ||
| 26 | DMACH_UART1, | ||
| 27 | DMACH_UART1_SRC2, | ||
| 28 | DMACH_UART2, | ||
| 29 | DMACH_UART2_SRC2, | ||
| 30 | DMACH_UART3, | ||
| 31 | DMACH_UART3_SRC2, | ||
| 32 | DMACH_PCM0_TX, | ||
| 33 | DMACH_PCM0_RX, | ||
| 34 | DMACH_I2S0_OUT, | ||
| 35 | DMACH_I2S0_IN, | ||
| 36 | DMACH_SPI0_TX, | ||
| 37 | DMACH_SPI0_RX, | ||
| 38 | DMACH_HSI_I2SV40_TX, | ||
| 39 | DMACH_HSI_I2SV40_RX, | ||
| 40 | 53 | ||
| 41 | /* DMA1/SDMA1 */ | 54 | struct s3c2410_dma_client { |
| 42 | DMACH_PCM1_TX = 16, | 55 | char *name; |
| 43 | DMACH_PCM1_RX, | ||
| 44 | DMACH_I2S1_OUT, | ||
| 45 | DMACH_I2S1_IN, | ||
| 46 | DMACH_SPI1_TX, | ||
| 47 | DMACH_SPI1_RX, | ||
| 48 | DMACH_AC97_PCMOUT, | ||
| 49 | DMACH_AC97_PCMIN, | ||
| 50 | DMACH_AC97_MICIN, | ||
| 51 | DMACH_PWM, | ||
| 52 | DMACH_IRDA, | ||
| 53 | DMACH_EXTERNAL, | ||
| 54 | DMACH_RES1, | ||
| 55 | DMACH_RES2, | ||
| 56 | DMACH_SECURITY_RX, /* SDMA1 only */ | ||
| 57 | DMACH_SECURITY_TX, /* SDMA1 only */ | ||
| 58 | DMACH_MAX /* the end */ | ||
| 59 | }; | 56 | }; |
| 60 | 57 | ||
| 61 | static inline bool samsung_dma_has_circular(void) | 58 | static inline bool samsung_dma_has_circular(void) |
| @@ -65,67 +62,10 @@ static inline bool samsung_dma_has_circular(void) | |||
| 65 | 62 | ||
| 66 | static inline bool samsung_dma_is_dmadev(void) | 63 | static inline bool samsung_dma_is_dmadev(void) |
| 67 | { | 64 | { |
| 68 | return false; | 65 | return true; |
| 69 | } | 66 | } |
| 70 | #define S3C2410_DMAF_CIRCULAR (1 << 0) | ||
| 71 | |||
| 72 | #include <plat/dma.h> | ||
| 73 | |||
| 74 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ | ||
| 75 | |||
| 76 | struct s3c64xx_dma_buff; | ||
| 77 | |||
| 78 | /** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor | ||
| 79 | * @next: Pointer to next buffer in queue or ring. | ||
| 80 | * @pw: Client provided identifier | ||
| 81 | * @lli: Pointer to hardware descriptor this buffer is associated with. | ||
| 82 | * @lli_dma: Hardare address of the descriptor. | ||
| 83 | */ | ||
| 84 | struct s3c64xx_dma_buff { | ||
| 85 | struct s3c64xx_dma_buff *next; | ||
| 86 | |||
| 87 | void *pw; | ||
| 88 | struct pl080s_lli *lli; | ||
| 89 | dma_addr_t lli_dma; | ||
| 90 | }; | ||
| 91 | |||
| 92 | struct s3c64xx_dmac; | ||
| 93 | |||
| 94 | struct s3c2410_dma_chan { | ||
| 95 | unsigned char number; /* number of this dma channel */ | ||
| 96 | unsigned char in_use; /* channel allocated */ | ||
| 97 | unsigned char bit; /* bit for enable/disable/etc */ | ||
| 98 | unsigned char hw_width; | ||
| 99 | unsigned char peripheral; | ||
| 100 | |||
| 101 | unsigned int flags; | ||
| 102 | enum dma_data_direction source; | ||
| 103 | |||
| 104 | |||
| 105 | dma_addr_t dev_addr; | ||
| 106 | |||
| 107 | struct s3c2410_dma_client *client; | ||
| 108 | struct s3c64xx_dmac *dmac; /* pointer to controller */ | ||
| 109 | |||
| 110 | void __iomem *regs; | ||
| 111 | |||
| 112 | /* cdriver callbacks */ | ||
| 113 | s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ | ||
| 114 | s3c2410_dma_opfn_t op_fn; /* channel op callback */ | ||
| 115 | |||
| 116 | /* buffer list and information */ | ||
| 117 | struct s3c64xx_dma_buff *curr; /* current dma buffer */ | ||
| 118 | struct s3c64xx_dma_buff *next; /* next buffer to load */ | ||
| 119 | struct s3c64xx_dma_buff *end; /* end of queue */ | ||
| 120 | |||
| 121 | /* note, when channel is running in circular mode, curr is the | ||
| 122 | * first buffer enqueued, end is the last and curr is where the | ||
| 123 | * last buffer-done event is set-at. The buffers are not freed | ||
| 124 | * and the last buffer hardware descriptor points back to the | ||
| 125 | * first. | ||
| 126 | */ | ||
| 127 | }; | ||
| 128 | 67 | ||
| 129 | #include <plat/dma-core.h> | 68 | #include <linux/amba/pl08x.h> |
| 69 | #include <plat/dma-ops.h> | ||
| 130 | 70 | ||
| 131 | #endif /* __ASM_ARCH_IRQ_H */ | 71 | #endif /* __ASM_ARCH_IRQ_H */ |
