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-rw-r--r--arch/arm/mach-s3c6410/Kconfig37
-rw-r--r--arch/arm/mach-s3c6410/Makefile4
-rw-r--r--arch/arm/mach-s3c6410/cpu.c3
-rw-r--r--arch/arm/mach-s3c6410/mach-anw6410.c245
-rw-r--r--arch/arm/mach-s3c6410/mach-ncp.c107
-rw-r--r--arch/arm/mach-s3c6410/mach-smdk6410.c198
-rw-r--r--arch/arm/mach-s3c6410/setup-sdhci.c34
7 files changed, 593 insertions, 35 deletions
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
index 1d5010070027..e63aac7f4e5a 100644
--- a/arch/arm/mach-s3c6410/Kconfig
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -16,9 +16,18 @@ config CPU_S3C6410
16 16
17config S3C6410_SETUP_SDHCI 17config S3C6410_SETUP_SDHCI
18 bool 18 bool
19 select S3C64XX_SETUP_SDHCI_GPIO
19 help 20 help
20 Internal helper functions for S3C6410 based SDHCI systems 21 Internal helper functions for S3C6410 based SDHCI systems
21 22
23config MACH_ANW6410
24 bool "A&W6410"
25 select CPU_S3C6410
26 select S3C_DEV_FB
27 select S3C64XX_SETUP_FB_24BPP
28 help
29 Machine support for the A&W6410
30
22config MACH_SMDK6410 31config MACH_SMDK6410
23 bool "SMDK6410" 32 bool "SMDK6410"
24 select CPU_S3C6410 33 select CPU_S3C6410
@@ -26,6 +35,8 @@ config MACH_SMDK6410
26 select S3C_DEV_HSMMC1 35 select S3C_DEV_HSMMC1
27 select S3C_DEV_I2C1 36 select S3C_DEV_I2C1
28 select S3C_DEV_FB 37 select S3C_DEV_FB
38 select S3C_DEV_USB_HOST
39 select S3C_DEV_USB_HSOTG
29 select S3C6410_SETUP_SDHCI 40 select S3C6410_SETUP_SDHCI
30 select S3C64XX_SETUP_I2C1 41 select S3C64XX_SETUP_I2C1
31 select S3C64XX_SETUP_FB_24BPP 42 select S3C64XX_SETUP_FB_24BPP
@@ -60,3 +71,29 @@ config SMDK6410_SD_CH1
60 channels 0 and 1 are the same. 71 channels 0 and 1 are the same.
61 72
62endchoice 73endchoice
74
75config SMDK6410_WM1190_EV1
76 bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
77 depends on MACH_SMDK6410
78 select REGULATOR
79 select REGULATOR_WM8350
80 select MFD_WM8350_I2C
81 select MFD_WM8350_CONFIG_MODE_0
82 select MFD_WM8350_CONFIG_MODE_3
83 select MFD_WM8352_CONFIG_MODE_0
84 help
85 The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
86 and audio daughtercard for the Samsung SMDK6410 reference
87 platform. Enabling this option will build support for this
88 module into the kernel. The presence of the module will be
89 detected at runtime so the the resulting kernel can be used
90 with or without the 1190-EV1 fitted.
91
92config MACH_NCP
93 bool "NCP"
94 select CPU_S3C6410
95 select S3C_DEV_I2C1
96 select S3C_DEV_HSMMC1
97 select S3C64XX_SETUP_I2C1
98 help
99 Machine support for the Samsung NCP
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
index 2cd4f189036b..6f9deac88612 100644
--- a/arch/arm/mach-s3c6410/Makefile
+++ b/arch/arm/mach-s3c6410/Makefile
@@ -20,4 +20,8 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
20 20
21# machine support 21# machine support
22 22
23obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
23obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o 24obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
25obj-$(CONFIG_MACH_NCP) += mach-ncp.o
26
27
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index 6a73ca6b7a3a..ade904de8895 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -31,6 +31,7 @@
31 31
32#include <plat/cpu-freq.h> 32#include <plat/cpu-freq.h>
33#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <plat/regs-clock.h>
34 35
35#include <plat/cpu.h> 36#include <plat/cpu.h>
36#include <plat/devs.h> 37#include <plat/devs.h>
@@ -68,7 +69,7 @@ void __init s3c6410_init_clocks(int xtal)
68 printk(KERN_DEBUG "%s: initialising clocks\n", __func__); 69 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
69 s3c24xx_register_baseclocks(xtal); 70 s3c24xx_register_baseclocks(xtal);
70 s3c64xx_register_clocks(); 71 s3c64xx_register_clocks();
71 s3c6400_register_clocks(); 72 s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
72 s3c6400_setup_clocks(); 73 s3c6400_setup_clocks();
73} 74}
74 75
diff --git a/arch/arm/mach-s3c6410/mach-anw6410.c b/arch/arm/mach-s3c6410/mach-anw6410.c
new file mode 100644
index 000000000000..661cca63de25
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-anw6410.c
@@ -0,0 +1,245 @@
1/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 * Copyright 2009 Kwangwoo Lee
8 * Kwangwoo Lee <kwangwoo.lee@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/i2c.h>
26#include <linux/fb.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
29#include <linux/dm9000.h>
30
31#include <video/platform_lcd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38#include <mach/regs-fb.h>
39#include <mach/map.h>
40
41#include <asm/irq.h>
42#include <asm/mach-types.h>
43
44#include <plat/regs-serial.h>
45#include <plat/iic.h>
46#include <plat/fb.h>
47
48#include <plat/s3c6410.h>
49#include <plat/clock.h>
50#include <plat/devs.h>
51#include <plat/cpu.h>
52#include <plat/regs-gpio.h>
53#include <plat/regs-modem.h>
54
55/* DM9000 */
56#define ANW6410_PA_DM9000 (0x18000000)
57
58/* A hardware buffer to control external devices is mapped at 0x30000000.
59 * It can not be read. So current status must be kept in anw6410_extdev_status.
60 */
61#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
62#define ANW6410_PA_EXTDEV (0x30000000)
63
64#define ANW6410_EN_DM9000 (1<<11)
65#define ANW6410_EN_LCD (1<<14)
66
67static __u32 anw6410_extdev_status;
68
69static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
70 [0] = {
71 .hwport = 0,
72 .flags = 0,
73 .ucon = 0x3c5,
74 .ulcon = 0x03,
75 .ufcon = 0x51,
76 },
77 [1] = {
78 .hwport = 1,
79 .flags = 0,
80 .ucon = 0x3c5,
81 .ulcon = 0x03,
82 .ufcon = 0x51,
83 },
84};
85
86/* framebuffer and LCD setup. */
87static void __init anw6410_lcd_mode_set(void)
88{
89 u32 tmp;
90
91 /* set the LCD type */
92 tmp = __raw_readl(S3C64XX_SPCON);
93 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
94 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
95 __raw_writel(tmp, S3C64XX_SPCON);
96
97 /* remove the LCD bypass */
98 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
99 tmp &= ~MIFPCON_LCD_BYPASS;
100 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
101}
102
103/* GPF1 = LCD panel power
104 * GPF4 = LCD backlight control
105 */
106static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
107 unsigned int power)
108{
109 if (power) {
110 anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
111 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
112
113 gpio_direction_output(S3C64XX_GPF(1), 1);
114 gpio_direction_output(S3C64XX_GPF(4), 1);
115 } else {
116 anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
117 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
118
119 gpio_direction_output(S3C64XX_GPF(1), 0);
120 gpio_direction_output(S3C64XX_GPF(4), 0);
121 }
122}
123
124static struct plat_lcd_data anw6410_lcd_power_data = {
125 .set_power = anw6410_lcd_power_set,
126};
127
128static struct platform_device anw6410_lcd_powerdev = {
129 .name = "platform-lcd",
130 .dev.parent = &s3c_device_fb.dev,
131 .dev.platform_data = &anw6410_lcd_power_data,
132};
133
134static struct s3c_fb_pd_win anw6410_fb_win0 = {
135 /* this is to ensure we use win0 */
136 .win_mode = {
137 .pixclock = 41094,
138 .left_margin = 8,
139 .right_margin = 13,
140 .upper_margin = 7,
141 .lower_margin = 5,
142 .hsync_len = 3,
143 .vsync_len = 1,
144 .xres = 800,
145 .yres = 480,
146 },
147 .max_bpp = 32,
148 .default_bpp = 16,
149};
150
151/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
152static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
153 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
154 .win[0] = &anw6410_fb_win0,
155 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
156 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
157};
158
159/* DM9000AEP 10/100 ethernet controller */
160static void __init anw6410_dm9000_enable(void)
161{
162 anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
163 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
164}
165
166static struct resource anw6410_dm9000_resource[] = {
167 [0] = {
168 .start = ANW6410_PA_DM9000,
169 .end = ANW6410_PA_DM9000 + 3,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = ANW6410_PA_DM9000 + 4,
174 .end = ANW6410_PA_DM9000 + 4 + 500,
175 .flags = IORESOURCE_MEM,
176 },
177 [2] = {
178 .start = IRQ_EINT(15),
179 .end = IRQ_EINT(15),
180 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
181 },
182};
183
184static struct dm9000_plat_data anw6410_dm9000_pdata = {
185 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
186 /* dev_addr can be set to provide hwaddr. */
187};
188
189static struct platform_device anw6410_device_eth = {
190 .name = "dm9000",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
193 .resource = anw6410_dm9000_resource,
194 .dev = {
195 .platform_data = &anw6410_dm9000_pdata,
196 },
197};
198
199static struct map_desc anw6410_iodesc[] __initdata = {
200 {
201 .virtual = (unsigned long)ANW6410_VA_EXTDEV,
202 .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
203 .length = SZ_64K,
204 .type = MT_DEVICE,
205 },
206};
207
208static struct platform_device *anw6410_devices[] __initdata = {
209 &s3c_device_fb,
210 &anw6410_lcd_powerdev,
211 &anw6410_device_eth,
212};
213
214static void __init anw6410_map_io(void)
215{
216 s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
217 s3c24xx_init_clocks(12000000);
218 s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
219
220 anw6410_lcd_mode_set();
221}
222
223static void __init anw6410_machine_init(void)
224{
225 s3c_fb_set_platdata(&anw6410_lcd_pdata);
226
227 gpio_request(S3C64XX_GPF(1), "panel power");
228 gpio_request(S3C64XX_GPF(4), "LCD backlight");
229
230 anw6410_dm9000_enable();
231
232 platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
233}
234
235MACHINE_START(ANW6410, "A&W6410")
236 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
237 .phys_io = S3C_PA_UART & 0xfff00000,
238 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
239 .boot_params = S3C64XX_PA_SDRAM + 0x100,
240
241 .init_irq = s3c6410_init_irq,
242 .map_io = anw6410_map_io,
243 .init_machine = anw6410_machine_init,
244 .timer = &s3c24xx_timer,
245MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c6410/mach-ncp.c
new file mode 100644
index 000000000000..6030636f8548
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-ncp.c
@@ -0,0 +1,107 @@
1/*
2 * linux/arch/arm/mach-s3c6410/mach-ncp.c
3 *
4 * Copyright (C) 2008-2009 Samsung Electronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/i2c.h>
22#include <linux/fb.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25
26#include <video/platform_lcd.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <mach/hardware.h>
33#include <mach/regs-fb.h>
34#include <mach/map.h>
35
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <plat/regs-serial.h>
40#include <plat/iic.h>
41#include <plat/fb.h>
42
43#include <plat/s3c6410.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47
48#define UCON S3C2410_UCON_DEFAULT
49#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
50#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
51
52static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
53 /* REVISIT: NCP uses only serial 1, 2 */
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = UCON,
58 .ulcon = ULCON,
59 .ufcon = UFCON,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = UCON,
65 .ulcon = ULCON,
66 .ufcon = UFCON,
67 },
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 },
75};
76
77static struct platform_device *ncp_devices[] __initdata = {
78 &s3c_device_hsmmc1,
79 &s3c_device_i2c0,
80};
81
82struct map_desc ncp_iodesc[] = {};
83
84static void __init ncp_map_io(void)
85{
86 s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
87 s3c24xx_init_clocks(12000000);
88 s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
89}
90
91static void __init ncp_machine_init(void)
92{
93 s3c_i2c0_set_platdata(NULL);
94
95 platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
96}
97
98MACHINE_START(NCP, "NCP")
99 /* Maintainer: Samsung Electronics */
100 .phys_io = S3C_PA_UART & 0xfff00000,
101 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
102 .boot_params = S3C64XX_PA_SDRAM + 0x100,
103 .init_irq = s3c6410_init_irq,
104 .map_io = ncp_map_io,
105 .init_machine = ncp_machine_init,
106 .timer = &s3c24xx_timer,
107MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 7f473e47e4f1..bc9a7dea567f 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -24,6 +24,12 @@
24#include <linux/fb.h> 24#include <linux/fb.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/smsc911x.h>
28
29#ifdef CONFIG_SMDK6410_WM1190_EV1
30#include <linux/mfd/wm8350/core.h>
31#include <linux/mfd/wm8350/pmic.h>
32#endif
27 33
28#include <video/platform_lcd.h> 34#include <video/platform_lcd.h>
29 35
@@ -39,8 +45,12 @@
39#include <asm/mach-types.h> 45#include <asm/mach-types.h>
40 46
41#include <plat/regs-serial.h> 47#include <plat/regs-serial.h>
48#include <plat/regs-modem.h>
49#include <plat/regs-gpio.h>
50#include <plat/regs-sys.h>
42#include <plat/iic.h> 51#include <plat/iic.h>
43#include <plat/fb.h> 52#include <plat/fb.h>
53#include <plat/gpio-cfg.h>
44 54
45#include <plat/s3c6410.h> 55#include <plat/s3c6410.h>
46#include <plat/clock.h> 56#include <plat/clock.h>
@@ -129,6 +139,37 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
129 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, 139 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
130}; 140};
131 141
142static struct resource smdk6410_smsc911x_resources[] = {
143 [0] = {
144 .start = 0x18000000,
145 .end = 0x18000000 + SZ_64K - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 [1] = {
149 .start = S3C_EINT(10),
150 .end = S3C_EINT(10),
151 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
152 },
153};
154
155static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
156 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
157 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
158 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
159 .phy_interface = PHY_INTERFACE_MODE_MII,
160};
161
162
163static struct platform_device smdk6410_smsc911x = {
164 .name = "smsc911x",
165 .id = -1,
166 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
167 .resource = &smdk6410_smsc911x_resources[0],
168 .dev = {
169 .platform_data = &smdk6410_smsc911x_pdata,
170 },
171};
172
132static struct map_desc smdk6410_iodesc[] = {}; 173static struct map_desc smdk6410_iodesc[] = {};
133 174
134static struct platform_device *smdk6410_devices[] __initdata = { 175static struct platform_device *smdk6410_devices[] __initdata = {
@@ -141,12 +182,155 @@ static struct platform_device *smdk6410_devices[] __initdata = {
141 &s3c_device_i2c0, 182 &s3c_device_i2c0,
142 &s3c_device_i2c1, 183 &s3c_device_i2c1,
143 &s3c_device_fb, 184 &s3c_device_fb,
185 &s3c_device_usb,
186 &s3c_device_usb_hsotg,
144 &smdk6410_lcd_powerdev, 187 &smdk6410_lcd_powerdev,
188
189 &smdk6410_smsc911x,
190};
191
192#ifdef CONFIG_SMDK6410_WM1190_EV1
193/* S3C64xx internal logic & PLL */
194static struct regulator_init_data wm8350_dcdc1_data = {
195 .constraints = {
196 .name = "PVDD_INT/PVDD_PLL",
197 .min_uV = 1200000,
198 .max_uV = 1200000,
199 .always_on = 1,
200 .apply_uV = 1,
201 },
202};
203
204/* Memory */
205static struct regulator_init_data wm8350_dcdc3_data = {
206 .constraints = {
207 .name = "PVDD_MEM",
208 .min_uV = 1800000,
209 .max_uV = 1800000,
210 .always_on = 1,
211 .state_mem = {
212 .uV = 1800000,
213 .mode = REGULATOR_MODE_NORMAL,
214 .enabled = 1,
215 },
216 .initial_state = PM_SUSPEND_MEM,
217 },
218};
219
220/* USB, EXT, PCM, ADC/DAC, USB, MMC */
221static struct regulator_init_data wm8350_dcdc4_data = {
222 .constraints = {
223 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
224 .min_uV = 3000000,
225 .max_uV = 3000000,
226 .always_on = 1,
227 },
228};
229
230/* ARM core */
231static struct regulator_consumer_supply dcdc6_consumers[] = {
232 {
233 .supply = "vddarm",
234 }
235};
236
237static struct regulator_init_data wm8350_dcdc6_data = {
238 .constraints = {
239 .name = "PVDD_ARM",
240 .min_uV = 1000000,
241 .max_uV = 1300000,
242 .always_on = 1,
243 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
244 },
245 .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
246 .consumer_supplies = dcdc6_consumers,
145}; 247};
146 248
249/* Alive */
250static struct regulator_init_data wm8350_ldo1_data = {
251 .constraints = {
252 .name = "PVDD_ALIVE",
253 .min_uV = 1200000,
254 .max_uV = 1200000,
255 .always_on = 1,
256 .apply_uV = 1,
257 },
258};
259
260/* OTG */
261static struct regulator_init_data wm8350_ldo2_data = {
262 .constraints = {
263 .name = "PVDD_OTG",
264 .min_uV = 3300000,
265 .max_uV = 3300000,
266 .always_on = 1,
267 },
268};
269
270/* LCD */
271static struct regulator_init_data wm8350_ldo3_data = {
272 .constraints = {
273 .name = "PVDD_LCD",
274 .min_uV = 3000000,
275 .max_uV = 3000000,
276 .always_on = 1,
277 },
278};
279
280/* OTGi/1190-EV1 HPVDD & AVDD */
281static struct regulator_init_data wm8350_ldo4_data = {
282 .constraints = {
283 .name = "PVDD_OTGI/HPVDD/AVDD",
284 .min_uV = 1200000,
285 .max_uV = 1200000,
286 .apply_uV = 1,
287 .always_on = 1,
288 },
289};
290
291static struct {
292 int regulator;
293 struct regulator_init_data *initdata;
294} wm1190_regulators[] = {
295 { WM8350_DCDC_1, &wm8350_dcdc1_data },
296 { WM8350_DCDC_3, &wm8350_dcdc3_data },
297 { WM8350_DCDC_4, &wm8350_dcdc4_data },
298 { WM8350_DCDC_6, &wm8350_dcdc6_data },
299 { WM8350_LDO_1, &wm8350_ldo1_data },
300 { WM8350_LDO_2, &wm8350_ldo2_data },
301 { WM8350_LDO_3, &wm8350_ldo3_data },
302 { WM8350_LDO_4, &wm8350_ldo4_data },
303};
304
305static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
306{
307 int i;
308
309 /* Instantiate the regulators */
310 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
311 wm8350_register_regulator(wm8350,
312 wm1190_regulators[i].regulator,
313 wm1190_regulators[i].initdata);
314
315 return 0;
316}
317
318static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
319 .init = smdk6410_wm8350_init,
320 .irq_high = 1,
321};
322#endif
323
147static struct i2c_board_info i2c_devs0[] __initdata = { 324static struct i2c_board_info i2c_devs0[] __initdata = {
148 { I2C_BOARD_INFO("24c08", 0x50), }, 325 { I2C_BOARD_INFO("24c08", 0x50), },
149 { I2C_BOARD_INFO("wm8580", 0x1b), }, 326 { I2C_BOARD_INFO("wm8580", 0x1b), },
327
328#ifdef CONFIG_SMDK6410_WM1190_EV1
329 { I2C_BOARD_INFO("wm8350", 0x1a),
330 .platform_data = &smdk6410_wm8350_pdata,
331 .irq = S3C_EINT(12),
332 },
333#endif
150}; 334};
151 335
152static struct i2c_board_info i2c_devs1[] __initdata = { 336static struct i2c_board_info i2c_devs1[] __initdata = {
@@ -155,9 +339,23 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
155 339
156static void __init smdk6410_map_io(void) 340static void __init smdk6410_map_io(void)
157{ 341{
342 u32 tmp;
343
158 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); 344 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
159 s3c24xx_init_clocks(12000000); 345 s3c24xx_init_clocks(12000000);
160 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); 346 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
347
348 /* set the LCD type */
349
350 tmp = __raw_readl(S3C64XX_SPCON);
351 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
352 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
353 __raw_writel(tmp, S3C64XX_SPCON);
354
355 /* remove the lcd bypass */
356 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
357 tmp &= ~MIFPCON_LCD_BYPASS;
358 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
161} 359}
162 360
163static void __init smdk6410_machine_init(void) 361static void __init smdk6410_machine_init(void)
diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
index 0b5788bd5985..20666f3bd478 100644
--- a/arch/arm/mach-s3c6410/setup-sdhci.c
+++ b/arch/arm/mach-s3c6410/setup-sdhci.c
@@ -21,8 +21,6 @@
21#include <linux/mmc/card.h> 21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h> 22#include <linux/mmc/host.h>
23 23
24#include <mach/gpio.h>
25#include <plat/gpio-cfg.h>
26#include <plat/regs-sdhci.h> 24#include <plat/regs-sdhci.h>
27#include <plat/sdhci.h> 25#include <plat/sdhci.h>
28 26
@@ -35,22 +33,6 @@ char *s3c6410_hsmmc_clksrcs[4] = {
35 /* [3] = "48m", - note not succesfully used yet */ 33 /* [3] = "48m", - note not succesfully used yet */
36}; 34};
37 35
38void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
39{
40 unsigned int gpio;
41 unsigned int end;
42
43 end = S3C64XX_GPG(2 + width);
44
45 /* Set all the necessary GPG pins to special-function 0 */
46 for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
47 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
48 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
49 }
50
51 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
52 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
53}
54 36
55void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, 37void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
56 void __iomem *r, 38 void __iomem *r,
@@ -84,19 +66,3 @@ void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
84 writel(ctrl3, r + S3C_SDHCI_CONTROL3); 66 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
85} 67}
86 68
87void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
88{
89 unsigned int gpio;
90 unsigned int end;
91
92 end = S3C64XX_GPH(2 + width);
93
94 /* Set all the necessary GPG pins to special-function 0 */
95 for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
96 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
97 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
98 }
99
100 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
101 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
102}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 04:39:25 -0500