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-rw-r--r--arch/arm/mach-s3c6400/Kconfig25
-rw-r--r--arch/arm/mach-s3c6400/Makefile10
-rw-r--r--arch/arm/mach-s3c6400/include/mach/dma.h59
-rw-r--r--arch/arm/mach-s3c6400/include/mach/map.h6
-rw-r--r--arch/arm/mach-s3c6400/include/mach/regs-clock.h16
-rw-r--r--arch/arm/mach-s3c6400/include/mach/system.h8
-rw-r--r--arch/arm/mach-s3c6400/mach-smdk6400.c96
-rw-r--r--arch/arm/mach-s3c6400/s3c6400.c89
-rw-r--r--arch/arm/mach-s3c6400/setup-sdhci.c63
9 files changed, 368 insertions, 4 deletions
diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig
index 6da82b5c09ba..f5af212066c3 100644
--- a/arch/arm/mach-s3c6400/Kconfig
+++ b/arch/arm/mach-s3c6400/Kconfig
@@ -5,4 +5,27 @@
5# 5#
6# Licensed under GPLv2 6# Licensed under GPLv2
7 7
8# Currently nothing here, this will be added later 8# Configuration options for the S3C6410 CPU
9
10config CPU_S3C6400
11 bool
12 select CPU_S3C6400_INIT
13 select CPU_S3C6400_CLOCK
14 help
15 Enable S3C6400 CPU support
16
17config S3C6400_SETUP_SDHCI
18 bool
19 help
20 Internal configuration for default SDHCI
21 setup for S3C6400.
22
23# S36400 Macchine support
24
25config MACH_SMDK6400
26 bool "SMDK6400"
27 select CPU_S3C6400
28 select S3C_DEV_HSMMC
29 select S3C6400_SETUP_SDHCI
30 help
31 Machine support for the Samsung SMDK6400
diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile
index 8f397db25b87..df1ce4aa03e5 100644
--- a/arch/arm/mach-s3c6400/Makefile
+++ b/arch/arm/mach-s3c6400/Makefile
@@ -12,4 +12,12 @@ obj- :=
12 12
13# Core support for S3C6400 system 13# Core support for S3C6400 system
14 14
15obj-n += blank.o 15obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
16
17# setup support
18
19obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o
20
21# Machine support
22
23obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h
index 9771ac2cb07e..1067619f0ba0 100644
--- a/arch/arm/mach-s3c6400/include/mach/dma.h
+++ b/arch/arm/mach-s3c6400/include/mach/dma.h
@@ -11,6 +11,63 @@
11#ifndef __ASM_ARCH_DMA_H 11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H __FILE__ 12#define __ASM_ARCH_DMA_H __FILE__
13 13
14/* currently nothing here, placeholder */ 14#define S3C_DMA_CHANNELS (16)
15
16/* see mach-s3c2410/dma.h for notes on dma channel numbers */
17
18/* Note, for the S3C64XX architecture we keep the DMACH_
19 * defines in the order they are allocated to [S]DMA0/[S]DMA1
20 * so that is easy to do DHACH_ -> DMA controller conversion
21 */
22enum dma_ch {
23 /* DMA0/SDMA0 */
24 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2,
26 DMACH_UART1,
27 DMACH_UART1_SRC2,
28 DMACH_UART2,
29 DMACH_UART2_SRC2,
30 DMACH_UART3,
31 DMACH_UART3_SRC2,
32 DMACH_PCM0_TX,
33 DMACH_PCM0_RX,
34 DMACH_I2S0_OUT,
35 DMACH_I2S0_IN,
36 DMACH_SPI0_TX,
37 DMACH_SPI0_RX,
38 DMACH_HSI_I2SV40_TX,
39 DMACH_HSI_I2SV40_RX,
40
41 /* DMA1/SDMA1 */
42 DMACH_PCM1_TX = 16,
43 DMACH_PCM1_RX,
44 DMACH_I2S1_OUT,
45 DMACH_I2S1_IN,
46 DMACH_SPI1_TX,
47 DMACH_SPI1_RX,
48 DMACH_AC97_PCMOUT,
49 DMACH_AC97_PCMIN,
50 DMACH_AC97_MICIN,
51 DMACH_PWM,
52 DMACH_IRDA,
53 DMACH_EXTERNAL,
54 DMACH_RES1,
55 DMACH_RES2,
56 DMACH_SECURITY_RX, /* SDMA1 only */
57 DMACH_SECURITY_TX, /* SDMA1 only */
58 DMACH_MAX /* the end */
59};
60
61static __inline__ int s3c_dma_has_circular(void)
62{
63 /* we will be supporting ciruclar buffers as soon as we have DMA
64 * engine support.
65 */
66 return 1;
67}
68
69#define S3C2410_DMAF_CIRCULAR (1 << 0)
70
71#include <plat/dma.h>
15 72
16#endif /* __ASM_ARCH_IRQ_H */ 73#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 8199972ed5bd..5057d9948d35 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -39,6 +39,8 @@
39#define S3C_VA_UART3 S3C_VA_UARTx(3) 39#define S3C_VA_UART3 S3C_VA_UARTx(3)
40 40
41#define S3C64XX_PA_FB (0x77100000) 41#define S3C64XX_PA_FB (0x77100000)
42#define S3C64XX_PA_USB_HSOTG (0x7C000000)
43#define S3C64XX_PA_WATCHDOG (0x7E004000)
42#define S3C64XX_PA_SYSCON (0x7E00F000) 44#define S3C64XX_PA_SYSCON (0x7E00F000)
43#define S3C64XX_PA_IIS0 (0x7F002000) 45#define S3C64XX_PA_IIS0 (0x7F002000)
44#define S3C64XX_PA_IIS1 (0x7F003000) 46#define S3C64XX_PA_IIS1 (0x7F003000)
@@ -57,6 +59,8 @@
57#define S3C64XX_PA_MODEM (0x74108000) 59#define S3C64XX_PA_MODEM (0x74108000)
58#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) 60#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
59 61
62#define S3C64XX_PA_USBHOST (0x74300000)
63
60/* place VICs close together */ 64/* place VICs close together */
61#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) 65#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
62#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) 66#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
@@ -69,5 +73,7 @@
69#define S3C_PA_IIC S3C64XX_PA_IIC0 73#define S3C_PA_IIC S3C64XX_PA_IIC0
70#define S3C_PA_IIC1 S3C64XX_PA_IIC1 74#define S3C_PA_IIC1 S3C64XX_PA_IIC1
71#define S3C_PA_FB S3C64XX_PA_FB 75#define S3C_PA_FB S3C64XX_PA_FB
76#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
77#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
72 78
73#endif /* __ASM_ARCH_6400_MAP_H */ 79#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
new file mode 100644
index 000000000000..a6c7f4eb3a1b
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - clock register compatibility with s3c24xx
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <plat/regs-clock.h>
16
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h
index 090cfd969bc7..2e58cb7a7147 100644
--- a/arch/arm/mach-s3c6400/include/mach/system.h
+++ b/arch/arm/mach-s3c6400/include/mach/system.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__ 12#define __ASM_ARCH_SYSTEM_H __FILE__
13 13
14#include <plat/watchdog-reset.h>
15
14static void arch_idle(void) 16static void arch_idle(void)
15{ 17{
16 /* nothing here yet */ 18 /* nothing here yet */
@@ -18,7 +20,11 @@ static void arch_idle(void)
18 20
19static void arch_reset(char mode, const char *cmd) 21static void arch_reset(char mode, const char *cmd)
20{ 22{
21 /* nothing here yet */ 23 if (mode != 's')
24 arch_wdt_reset();
25
26 /* if all else fails, or mode was for soft, jump to 0 */
27 cpu_reset(0);
22} 28}
23 29
24#endif /* __ASM_ARCH_IRQ_H */ 30#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c6400/mach-smdk6400.c
new file mode 100644
index 000000000000..ab19285389a7
--- /dev/null
+++ b/arch/arm/mach-s3c6400/mach-smdk6400.c
@@ -0,0 +1,96 @@
1/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/i2c.h>
21#include <linux/io.h>
22
23#include <asm/mach-types.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31
32#include <plat/regs-serial.h>
33
34#include <plat/s3c6400.h>
35#include <plat/clock.h>
36#include <plat/devs.h>
37#include <plat/cpu.h>
38#include <plat/iic.h>
39
40#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
41#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
42#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
43
44static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = {
45 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = 0x3c5,
49 .ulcon = 0x03,
50 .ufcon = 0x51,
51 },
52 [1] = {
53 .hwport = 1,
54 .flags = 0,
55 .ucon = 0x3c5,
56 .ulcon = 0x03,
57 .ufcon = 0x51,
58 },
59};
60
61static struct map_desc smdk6400_iodesc[] = {};
62
63static void __init smdk6400_map_io(void)
64{
65 s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
66 s3c24xx_init_clocks(12000000);
67 s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
68}
69
70static struct platform_device *smdk6400_devices[] __initdata = {
71 &s3c_device_hsmmc1,
72 &s3c_device_i2c0,
73};
74
75static struct i2c_board_info i2c_devs[] __initdata = {
76 { I2C_BOARD_INFO("wm8753", 0x1A), },
77 { I2C_BOARD_INFO("24c08", 0x50), },
78};
79
80static void __init smdk6400_machine_init(void)
81{
82 i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs));
83 platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
84}
85
86MACHINE_START(SMDK6400, "SMDK6400")
87 /* Maintainer: Ben Dooks <ben@fluff.org> */
88 .phys_io = S3C_PA_UART & 0xfff00000,
89 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
90 .boot_params = S3C64XX_PA_SDRAM + 0x100,
91
92 .init_irq = s3c6400_init_irq,
93 .map_io = smdk6400_map_io,
94 .init_machine = smdk6400_machine_init,
95 .timer = &s3c24xx_timer,
96MACHINE_END
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
new file mode 100644
index 000000000000..1ece887d90bb
--- /dev/null
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -0,0 +1,89 @@
1/* linux/arch/arm/mach-s3c6410/cpu.c
2 *
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/sysdev.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <mach/hardware.h>
29#include <asm/irq.h>
30
31#include <plat/cpu-freq.h>
32#include <plat/regs-serial.h>
33#include <plat/regs-clock.h>
34
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/clock.h>
38#include <plat/sdhci.h>
39#include <plat/iic-core.h>
40#include <plat/s3c6400.h>
41
42void __init s3c6400_map_io(void)
43{
44 /* setup SDHCI */
45
46 s3c6400_default_sdhci0();
47 s3c6400_default_sdhci1();
48
49 /* the i2c devices are directly compatible with s3c2440 */
50 s3c_i2c0_setname("s3c2440-i2c");
51}
52
53void __init s3c6400_init_clocks(int xtal)
54{
55 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
56 s3c24xx_register_baseclocks(xtal);
57 s3c64xx_register_clocks();
58 s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK);
59 s3c6400_setup_clocks();
60}
61
62void __init s3c6400_init_irq(void)
63{
64 /* VIC0 does not have IRQS 5..7,
65 * VIC1 is fully populated. */
66 s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
67}
68
69struct sysdev_class s3c6400_sysclass = {
70 .name = "s3c6400-core",
71};
72
73static struct sys_device s3c6400_sysdev = {
74 .cls = &s3c6400_sysclass,
75};
76
77static int __init s3c6400_core_init(void)
78{
79 return sysdev_class_register(&s3c6400_sysclass);
80}
81
82core_initcall(s3c6400_core_init);
83
84int __init s3c6400_init(void)
85{
86 printk("S3C6400: Initialising architecture\n");
87
88 return sysdev_register(&s3c6400_sysdev);
89}
diff --git a/arch/arm/mach-s3c6400/setup-sdhci.c b/arch/arm/mach-s3c6400/setup-sdhci.c
new file mode 100644
index 000000000000..b93dafbee1f4
--- /dev/null
+++ b/arch/arm/mach-s3c6400/setup-sdhci.c
@@ -0,0 +1,63 @@
1/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28
29char *s3c6400_hsmmc_clksrcs[4] = {
30 [0] = "hsmmc",
31 [1] = "hsmmc",
32 [2] = "mmc_bus",
33 /* [3] = "48m", - note not succesfully used yet */
34};
35
36void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
37 void __iomem *r,
38 struct mmc_ios *ios,
39 struct mmc_card *card)
40{
41 u32 ctrl2, ctrl3;
42
43 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
46 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
47 S3C_SDHCI_CTRL2_ENFBCLKRX |
48 S3C_SDHCI_CTRL2_DFCNT_NONE |
49 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
50
51 if (ios->clock < 25 * 1000000)
52 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
53 S3C_SDHCI_CTRL3_FCSEL2 |
54 S3C_SDHCI_CTRL3_FCSEL1 |
55 S3C_SDHCI_CTRL3_FCSEL0);
56 else
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
58
59 printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
60 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
61 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
62}
63
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 10:19:13 -0500