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-rw-r--r--arch/arm/mach-s3c24xx/Kconfig2
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2412.c56
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2443.c3
-rw-r--r--arch/arm/mach-s3c24xx/dma.c3
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/uncompress.h3
-rw-r--r--arch/arm/mach-s3c24xx/s3c2410.c3
-rw-r--r--arch/arm/mach-s3c24xx/s3c244x.c3
7 files changed, 26 insertions, 47 deletions
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index e52d5e42af4e..0adb2b85f830 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -31,6 +31,7 @@ config CPU_S3C2410
31 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX 31 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
32 select S3C2410_PM if PM 32 select S3C2410_PM if PM
33 select SAMSUNG_HRT 33 select SAMSUNG_HRT
34 select SAMSUNG_WDT_RESET
34 help 35 help
35 Support for S3C2410 and S3C2410A family from the S3C24XX line 36 Support for S3C2410 and S3C2410A family from the S3C24XX line
36 of Samsung Mobile CPUs. 37 of Samsung Mobile CPUs.
@@ -81,6 +82,7 @@ config CPU_S3C2442
81config CPU_S3C244X 82config CPU_S3C244X
82 def_bool y 83 def_bool y
83 depends on CPU_S3C2440 || CPU_S3C2442 84 depends on CPU_S3C2440 || CPU_S3C2442
85 select SAMSUNG_WDT_RESET
84 86
85config CPU_S3C2443 87config CPU_S3C2443
86 bool "SAMSUNG S3C2443" 88 bool "SAMSUNG S3C2443"
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index ab1700ec8e64..b7e094671522 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -35,121 +35,95 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
35 [DMACH_XD0] = { 35 [DMACH_XD0] = {
36 .name = "xdreq0", 36 .name = "xdreq0",
37 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), 37 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
38 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0),
39 }, 38 },
40 [DMACH_XD1] = { 39 [DMACH_XD1] = {
41 .name = "xdreq1", 40 .name = "xdreq1",
42 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), 41 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
43 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1),
44 }, 42 },
45 [DMACH_SDI] = { 43 [DMACH_SDI] = {
46 .name = "sdi", 44 .name = "sdi",
47 .channels = MAP(S3C2412_DMAREQSEL_SDI), 45 .channels = MAP(S3C2412_DMAREQSEL_SDI),
48 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
49 }, 46 },
50 [DMACH_SPI0] = { 47 [DMACH_SPI0_RX] = {
51 .name = "spi0", 48 .name = "spi0-rx",
49 .channels = MAP(S3C2412_DMAREQSEL_SPI0RX),
50 },
51 [DMACH_SPI0_TX] = {
52 .name = "spi0-tx",
52 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), 53 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
53 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
54 }, 54 },
55 [DMACH_SPI1] = { 55 [DMACH_SPI1_RX] = {
56 .name = "spi1", 56 .name = "spi1-rx",
57 .channels = MAP(S3C2412_DMAREQSEL_SPI1RX),
58 },
59 [DMACH_SPI1_TX] = {
60 .name = "spi1-tx",
57 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), 61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
58 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
59 }, 62 },
60 [DMACH_UART0] = { 63 [DMACH_UART0] = {
61 .name = "uart0", 64 .name = "uart0",
62 .channels = MAP(S3C2412_DMAREQSEL_UART0_0), 65 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
63 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
64 }, 66 },
65 [DMACH_UART1] = { 67 [DMACH_UART1] = {
66 .name = "uart1", 68 .name = "uart1",
67 .channels = MAP(S3C2412_DMAREQSEL_UART1_0), 69 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
68 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
69 }, 70 },
70 [DMACH_UART2] = { 71 [DMACH_UART2] = {
71 .name = "uart2", 72 .name = "uart2",
72 .channels = MAP(S3C2412_DMAREQSEL_UART2_0), 73 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
73 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
74 }, 74 },
75 [DMACH_UART0_SRC2] = { 75 [DMACH_UART0_SRC2] = {
76 .name = "uart0", 76 .name = "uart0",
77 .channels = MAP(S3C2412_DMAREQSEL_UART0_1), 77 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
78 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
79 }, 78 },
80 [DMACH_UART1_SRC2] = { 79 [DMACH_UART1_SRC2] = {
81 .name = "uart1", 80 .name = "uart1",
82 .channels = MAP(S3C2412_DMAREQSEL_UART1_1), 81 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
83 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
84 }, 82 },
85 [DMACH_UART2_SRC2] = { 83 [DMACH_UART2_SRC2] = {
86 .name = "uart2", 84 .name = "uart2",
87 .channels = MAP(S3C2412_DMAREQSEL_UART2_1), 85 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
88 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
89 }, 86 },
90 [DMACH_TIMER] = { 87 [DMACH_TIMER] = {
91 .name = "timer", 88 .name = "timer",
92 .channels = MAP(S3C2412_DMAREQSEL_TIMER), 89 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
93 .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER),
94 }, 90 },
95 [DMACH_I2S_IN] = { 91 [DMACH_I2S_IN] = {
96 .name = "i2s-sdi", 92 .name = "i2s-sdi",
97 .channels = MAP(S3C2412_DMAREQSEL_I2SRX), 93 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
98 .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX),
99 }, 94 },
100 [DMACH_I2S_OUT] = { 95 [DMACH_I2S_OUT] = {
101 .name = "i2s-sdo", 96 .name = "i2s-sdo",
102 .channels = MAP(S3C2412_DMAREQSEL_I2STX), 97 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
103 .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX),
104 }, 98 },
105 [DMACH_USB_EP1] = { 99 [DMACH_USB_EP1] = {
106 .name = "usb-ep1", 100 .name = "usb-ep1",
107 .channels = MAP(S3C2412_DMAREQSEL_USBEP1), 101 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
108 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1),
109 }, 102 },
110 [DMACH_USB_EP2] = { 103 [DMACH_USB_EP2] = {
111 .name = "usb-ep2", 104 .name = "usb-ep2",
112 .channels = MAP(S3C2412_DMAREQSEL_USBEP2), 105 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
113 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2),
114 }, 106 },
115 [DMACH_USB_EP3] = { 107 [DMACH_USB_EP3] = {
116 .name = "usb-ep3", 108 .name = "usb-ep3",
117 .channels = MAP(S3C2412_DMAREQSEL_USBEP3), 109 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
118 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3),
119 }, 110 },
120 [DMACH_USB_EP4] = { 111 [DMACH_USB_EP4] = {
121 .name = "usb-ep4", 112 .name = "usb-ep4",
122 .channels = MAP(S3C2412_DMAREQSEL_USBEP4), 113 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
123 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4),
124 }, 114 },
125}; 115};
126 116
127static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
128 struct s3c24xx_dma_map *map,
129 enum dma_data_direction dir)
130{
131 unsigned long chsel;
132
133 if (dir == DMA_FROM_DEVICE)
134 chsel = map->channels_rx[0];
135 else
136 chsel = map->channels[0];
137
138 chsel &= ~DMA_CH_VALID;
139 chsel |= S3C2412_DMAREQSEL_HW;
140
141 writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
142}
143
144static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, 117static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
145 struct s3c24xx_dma_map *map) 118 struct s3c24xx_dma_map *map)
146{ 119{
147 s3c2412_dma_direction(chan, map, chan->source); 120 unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
121 writel(chsel | S3C2412_DMAREQSEL_HW,
122 chan->regs + S3C2412_DMA_DMAREQSEL);
148} 123}
149 124
150static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { 125static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
151 .select = s3c2412_dma_select, 126 .select = s3c2412_dma_select,
152 .direction = s3c2412_dma_direction,
153 .dcon_mask = 0, 127 .dcon_mask = 0,
154 .map = s3c2412_dma_mappings, 128 .map = s3c2412_dma_mappings,
155 .map_size = ARRAY_SIZE(s3c2412_dma_mappings), 129 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 5fe3539dc2b5..95b9f759fe97 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -128,7 +128,8 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
128static void s3c2443_dma_select(struct s3c2410_dma_chan *chan, 128static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
129 struct s3c24xx_dma_map *map) 129 struct s3c24xx_dma_map *map)
130{ 130{
131 writel(map->channels[0] | S3C2443_DMAREQSEL_HW, 131 unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
132 writel(chsel | S3C2443_DMAREQSEL_HW,
132 chan->regs + S3C2443_DMA_DMAREQSEL); 133 chan->regs + S3C2443_DMA_DMAREQSEL);
133} 134}
134 135
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index aab64909e9a3..4a65cba3295d 100644
--- a/arch/arm/mach-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -1159,9 +1159,6 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
1159 return -EINVAL; 1159 return -EINVAL;
1160 } 1160 }
1161 1161
1162 if (dma_sel.direction != NULL)
1163 (dma_sel.direction)(chan, chan->map, source);
1164
1165 return 0; 1162 return 0;
1166} 1163}
1167 1164
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
index 8b283f847daa..7d2ce205dce8 100644
--- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
@@ -49,6 +49,9 @@ static void arch_detect_cpu(void)
49 fifo_mask = S3C2410_UFSTAT_TXMASK; 49 fifo_mask = S3C2410_UFSTAT_TXMASK;
50 fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; 50 fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
51 } 51 }
52
53 uart_base = (volatile u8 *) S3C_PA_UART +
54 (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
52} 55}
53 56
54#endif /* __ASM_ARCH_UNCOMPRESS_H */ 57#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5adac2..ff384acc65b2 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -138,6 +138,7 @@ void __init s3c2410_init_clocks(int xtal)
138 s3c2410_baseclk_add(); 138 s3c2410_baseclk_add();
139 s3c24xx_register_clock(&s3c2410_armclk); 139 s3c24xx_register_clock(&s3c2410_armclk);
140 clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup)); 140 clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
141 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
141} 142}
142 143
143struct bus_type s3c2410_subsys = { 144struct bus_type s3c2410_subsys = {
@@ -201,7 +202,7 @@ void s3c2410_restart(char mode, const char *cmd)
201 soft_restart(0); 202 soft_restart(0);
202 } 203 }
203 204
204 arch_wdt_reset(); 205 samsung_wdt_reset();
205 206
206 /* we'll take a jump through zero as a poor second */ 207 /* we'll take a jump through zero as a poor second */
207 soft_restart(0); 208 soft_restart(0);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb67354..d0423e2544c1 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -133,6 +133,7 @@ void __init s3c244x_init_clocks(int xtal)
133 s3c24xx_register_baseclocks(xtal); 133 s3c24xx_register_baseclocks(xtal);
134 s3c244x_setup_clocks(); 134 s3c244x_setup_clocks();
135 s3c2410_baseclk_add(); 135 s3c2410_baseclk_add();
136 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
136} 137}
137 138
138/* Since the S3C2442 and S3C2440 share items, put both subsystems here */ 139/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
@@ -202,7 +203,7 @@ void s3c244x_restart(char mode, const char *cmd)
202 if (mode == 's') 203 if (mode == 's')
203 soft_restart(0); 204 soft_restart(0);
204 205
205 arch_wdt_reset(); 206 samsung_wdt_reset();
206 207
207 /* we'll take a jump through zero as a poor second */ 208 /* we'll take a jump through zero as a poor second */
208 soft_restart(0); 209 soft_restart(0);