103 files changed, 6596 insertions, 1990 deletions

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 7079a70b1ab8..37f513d1588e 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -9,6 +9,15 @@
 
 if ARCH_S3C24XX
 
+config PLAT_S3C24XX
+        def_bool y
+        select ARCH_REQUIRE_GPIOLIB
+        select NO_IOPORT
+        select S3C_DEV_NAND
+        select IRQ_DOMAIN
+        help
+          Base platform code for any Samsung S3C24XX device
+
 menu "SAMSUNG S3C24XX SoCs Support"
 
 comment "S3C24XX SoCs"
@@ -83,6 +92,17 @@ config CPU_S3C2443
 
 # common code
 
+config S3C2410_CLOCK
+        bool
+        help
+          Clock code for the S3C2410, and similar processors which
+          is currently includes the S3C2410, S3C2440, S3C2442.
+
+config S3C24XX_DCLK
+        bool
+        help
+          Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
+
 config S3C24XX_SMDK
         bool
         help
@@ -111,6 +131,22 @@ config S3C24XX_SETUP_TS
         help
           Compile in platform device definition for Samsung TouchScreen.
 
+config S3C24XX_DMA
+        bool "S3C2410 DMA support"
+        depends on ARCH_S3C24XX
+        select S3C_DMA
+        help
+          S3C2410 DMA support. This is needed for drivers like sound which
+          use the S3C2410's DMA system to move data to and from the
+          peripheral blocks.
+
+config S3C2410_DMA_DEBUG
+        bool "S3C2410 DMA support debug"
+        depends on ARCH_S3C24XX && S3C2410_DMA
+        help
+          Enable debugging output for the DMA code. This option sends info
+          to the kernel log, at priority KERN_DEBUG.
+
 config S3C2410_DMA
         bool
         depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -123,10 +159,92 @@ config S3C2410_PM
         help
           Power Management code common to S3C2410 and better
 
+# low-level serial option nodes
+
+config CPU_LLSERIAL_S3C2410_ONLY
+        bool
+        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
+
+config CPU_LLSERIAL_S3C2440_ONLY
+        bool
+        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
+
+config CPU_LLSERIAL_S3C2410
+        bool
+        help
+          Selected if there is an S3C2410 (or register compatible) serial
+          low-level implementation needed
+
+config CPU_LLSERIAL_S3C2440
+        bool
+        help
+          Selected if there is an S3C2440 (or register compatible) serial
+          low-level implementation needed
+
+# gpio configurations
+
+config S3C24XX_GPIO_EXTRA
+        int
+        default 128 if S3C24XX_GPIO_EXTRA128
+        default 64 if S3C24XX_GPIO_EXTRA64
+        default 16 if ARCH_H1940
+        default 0
+
+config S3C24XX_GPIO_EXTRA64
+        bool
+        help
+          Add an extra 64 gpio numbers to the available GPIO pool. This is
+          available for boards that need extra gpios for external devices.
+
+config S3C24XX_GPIO_EXTRA128
+        bool
+        help
+          Add an extra 128 gpio numbers to the available GPIO pool. This is
+          available for boards that need extra gpios for external devices.
+
+# cpu frequency items common between s3c2410 and s3c2440/s3c2442
+
+config S3C2410_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select io timing code that is common to the s3c2410
+          and s3c2440/s3c2442 cpu frequency support.
+
+config S3C2410_CPUFREQ_UTILS
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select timing code that is common to the s3c2410
+          and s3c2440/s3c244 cpu frequency support.
+
+# cpu frequency support common to s3c2412, s3c2413 and s3c2442
+
+config S3C2412_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
+        help
+          Intel node to select io timing code that is common to the s3c2412
+          and the s3c2443.
+
 # cpu-specific sections
 
 if CPU_S3C2410
 
+config S3C2410_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2410
+
+config S3C2410_PLL
+        bool
+        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        default y
+        help
+          Select the PLL table for the S3C2410
+
 config S3C24XX_SIMTEC_NOR
         bool
         help
@@ -267,6 +385,14 @@ config CPU_S3C2412_ONLY
                    !CPU_S3C2443 && CPU_S3C2412
         default y
 
+config S3C2412_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        default y
+        select S3C2412_IOTIMING
+        help
+          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
+
 config S3C2412_DMA
         bool
         help
@@ -367,11 +493,45 @@ endif	# CPU_S3C2416
 
 if CPU_S3C2440
 
+config S3C2440_CPUFREQ
+        bool "S3C2440/S3C2442 CPU Frequency scaling support"
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
+        default y
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
+
 config S3C2440_DMA
         bool
         help
           Support for S3C2440 specific DMA code5A
 
+config S3C2440_XTAL_12000000
+        bool
+        help
+          Indicate that the build needs to support 12MHz system
+          crystal.
+
+config S3C2440_XTAL_16934400
+        bool
+        help
+          Indicate that the build needs to support 16.9344MHz system
+          crystal.
+
+config S3C2440_PLL_12000000
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
+
+config S3C2440_PLL_16934400
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
+
 comment "S3C2440 Boards"
 
 #
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 0ab6ab15da4c..af53d27d5c36 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,26 +14,32 @@ obj-				:=
 
 # core
 
-obj-y                           += common.o
+obj-y                           += common.o irq.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
+obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
 obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
+obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
 
-obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o irq-s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 
 obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
+obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
+obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
 
-obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o irq-s3c2443.o clock-s3c2443.o
+obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o clock-s3c2443.o
 
 # PM
 
@@ -41,9 +47,21 @@ obj-$(CONFIG_PM)		+= pm.o irq-pm.o sleep.o
 
 # common code
 
+obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
+obj-$(CONFIG_S3C24XX_DMA)       += dma.o
+
+obj-$(CONFIG_S3C2410_CLOCK)     += clock-s3c2410.o
+obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
+
+obj-$(CONFIG_S3C2410_IOTIMING)  += iotiming-s3c2410.o
+obj-$(CONFIG_S3C2412_IOTIMING)  += iotiming-s3c2412.o
+
 obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
 
+obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpufreq.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
+
 #
 # machine support
 # following is ordered alphabetically by option text.
diff --git a/arch/arm/mach-s3c24xx/anubis.h b/arch/arm/mach-s3c24xx/anubis.h
new file mode 100644
index 000000000000..2691665f27d9
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/anubis.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - CPLD control constants
+ * ANUBIS - IRQ Number definitions
+ * ANUBIS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_S3C24XX_ANUBIS_H
+#define __MACH_S3C24XX_ANUBIS_H __FILE__
+
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+
+#define ANUBIS_CTRL1_NANDSEL            (0x3)
+
+/* IDREG - revision */
+
+#define ANUBIS_IDREG_REVMASK            (0x7)
+
+/* irq */
+
+#define ANUBIS_IRQ_IDE0                 IRQ_EINT2
+#define ANUBIS_IRQ_IDE1                 IRQ_EINT3
+#define ANUBIS_IRQ_ASIX                 IRQ_EINT1
+
+/* map */
+
+/* start peripherals off after the S3C2410 */
+
+#define ANUBIS_IOADDR(x)                (S3C2410_ADDR((x) + 0x01800000))
+
+#define ANUBIS_PA_CPLD                  (S3C2410_CS1 | (1<<26))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define ANUBIS_VA_CTRL1                 ANUBIS_IOADDR(0x00000000)
+#define ANUBIS_PA_CTRL1                 ANUBIS_PA_CPLD
+
+#define ANUBIS_VA_IDREG                 ANUBIS_IOADDR(0x00300000)
+#define ANUBIS_PA_IDREG                 (ANUBIS_PA_CPLD + (3 << 23))
+
+#define ANUBIS_IDEPRI                   ANUBIS_IOADDR(0x01000000)
+#define ANUBIS_IDEPRIAUX                ANUBIS_IOADDR(0x01100000)
+#define ANUBIS_IDESEC                   ANUBIS_IOADDR(0x01200000)
+#define ANUBIS_IDESECAUX                ANUBIS_IOADDR(0x01300000)
+
+#endif /* __MACH_S3C24XX_ANUBIS_H */
diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c
index ba02cf8d80a2..3f0288f2f542 100644
--- a/arch/arm/mach-s3c24xx/bast-ide.c
+++ b/arch/arm/mach-s3c24xx/bast-ide.c
@@ -25,8 +25,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/map.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
+
+#include "bast.h"
 
 /* IDE ports */
 
@@ -34,12 +34,10 @@ static struct pata_platform_info bast_ide_platdata = {
         .ioport_shift   = 5,
 };
 
-#define IDE_CS  S3C2410_CS5
-
 static struct resource bast_ide0_resource[] = {
-        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
-        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
+        [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
 };
 
 static struct platform_device bast_device_ide0 = {
@@ -55,9 +53,9 @@ static struct platform_device bast_device_ide0 = {
 };
 
 static struct resource bast_ide1_resource[] = {
-        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
-        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE1),
+        [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
+        [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
 };
 
 static struct platform_device bast_device_ide1 = {
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index ac7b2ad5c405..c0daa9590b4c 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
@@ -27,27 +27,20 @@
 #include <linux/device.h>
 #include <linux/io.h>
 
-#include <asm/mach-types.h>
-
-#include <mach/hardware.h>
 #include <asm/irq.h>
-
+#include <asm/mach-types.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/regs-irq.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
 
 #include <plat/irq.h>
 
-#if 0
-#include <asm/debug-ll.h>
-#endif
+#include "bast.h"
 
 #define irqdbf(x...)
 #define irqdbf2(x...)
 
-
 /* handle PC104 ISA interrupts from the system CPLD */
 
 /* table of ISA irq nos to the relevant mask... zero means
@@ -87,7 +80,7 @@ bast_pc104_mask(struct irq_data *data)
 static void
 bast_pc104_maskack(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_desc + IRQ_ISA;
+        struct irq_desc *desc = irq_desc + BAST_IRQ_ISA;
 
         bast_pc104_mask(data);
         desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -122,7 +115,7 @@ bast_irq_pc104_demux(unsigned int irq,
         if (unlikely(stat == 0)) {
                 /* ack if we get an irq with nothing (ie, startup) */
 
-                desc = irq_desc + IRQ_ISA;
+                desc = irq_desc + BAST_IRQ_ISA;
                 desc->irq_data.chip->irq_ack(&desc->irq_data);
         } else {
                 /* handle the IRQ */
@@ -147,7 +140,7 @@ static __init int bast_irq_init(void)
 
                 __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
 
-                irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
+                irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
 
                 /* register our IRQs */
 
diff --git a/arch/arm/mach-s3c24xx/bast.h b/arch/arm/mach-s3c24xx/bast.h
new file mode 100644
index 000000000000..5c7534bae92d
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/bast.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2003-2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * BAST - CPLD control constants
+ * BAST - IRQ Number definitions
+ * BAST - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_S3C24XX_BAST_H
+#define __MACH_S3C24XX_BAST_H __FILE__
+
+/* CTRL1 - Audio LR routing */
+
+#define BAST_CPLD_CTRL1_LRCOFF          (0x00)
+#define BAST_CPLD_CTRL1_LRCADC          (0x01)
+#define BAST_CPLD_CTRL1_LRCDAC          (0x02)
+#define BAST_CPLD_CTRL1_LRCARM          (0x03)
+#define BAST_CPLD_CTRL1_LRMASK          (0x03)
+
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+
+#define BAST_CPLD_CTRL2_WNAND           (0x04)
+#define BAST_CPLD_CTLR2_IDERST          (0x08)
+
+/* CTRL3 - rom write control, CPLD identity */
+
+#define BAST_CPLD_CTRL3_IDMASK          (0x0e)
+#define BAST_CPLD_CTRL3_ROMWEN          (0x01)
+
+/* CTRL4 - 8bit LCD interface control/status */
+
+#define BAST_CPLD_CTRL4_LLAT            (0x01)
+#define BAST_CPLD_CTRL4_LCDRW           (0x02)
+#define BAST_CPLD_CTRL4_LCDCMD          (0x04)
+#define BAST_CPLD_CTRL4_LCDE2           (0x01)
+
+/* CTRL5 - DMA routing */
+
+#define BAST_CPLD_DMA0_PRIIDE           (0)
+#define BAST_CPLD_DMA0_SECIDE           (1)
+#define BAST_CPLD_DMA0_ISA15            (2)
+#define BAST_CPLD_DMA0_ISA36            (3)
+
+#define BAST_CPLD_DMA1_PRIIDE           (0 << 2)
+#define BAST_CPLD_DMA1_SECIDE           (1 << 2)
+#define BAST_CPLD_DMA1_ISA15            (2 << 2)
+#define BAST_CPLD_DMA1_ISA36            (3 << 2)
+
+/* irq numbers to onboard peripherals */
+
+#define BAST_IRQ_USBOC                  IRQ_EINT18
+#define BAST_IRQ_IDE0                   IRQ_EINT16
+#define BAST_IRQ_IDE1                   IRQ_EINT17
+#define BAST_IRQ_PCSERIAL1              IRQ_EINT15
+#define BAST_IRQ_PCSERIAL2              IRQ_EINT14
+#define BAST_IRQ_PCPARALLEL             IRQ_EINT13
+#define BAST_IRQ_ASIX                   IRQ_EINT11
+#define BAST_IRQ_DM9000                 IRQ_EINT10
+#define BAST_IRQ_ISA                    IRQ_EINT9
+#define BAST_IRQ_SMALERT                IRQ_EINT8
+
+/* map */
+
+/*
+ * ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+
+#define BAST_IOADDR(x)                  (S3C2410_ADDR((x) + 0x01300000))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define BAST_VA_CTRL1                   BAST_IOADDR(0x00000000)
+#define BAST_PA_CTRL1                   (S3C2410_CS5 | 0x7800000)
+
+#define BAST_VA_CTRL2                   BAST_IOADDR(0x00100000)
+#define BAST_PA_CTRL2                   (S3C2410_CS1 | 0x6000000)
+
+#define BAST_VA_CTRL3                   BAST_IOADDR(0x00200000)
+#define BAST_PA_CTRL3                   (S3C2410_CS1 | 0x6800000)
+
+#define BAST_VA_CTRL4                   BAST_IOADDR(0x00300000)
+#define BAST_PA_CTRL4                   (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define BAST_PA_PC104_IRQREQ            (S3C2410_CS5 | 0x6000000)
+#define BAST_VA_PC104_IRQREQ            BAST_IOADDR(0x00400000)
+
+#define BAST_PA_PC104_IRQRAW            (S3C2410_CS5 | 0x6800000)
+#define BAST_VA_PC104_IRQRAW            BAST_IOADDR(0x00500000)
+
+#define BAST_PA_PC104_IRQMASK           (S3C2410_CS5 | 0x7000000)
+#define BAST_VA_PC104_IRQMASK           BAST_IOADDR(0x00600000)
+
+#define BAST_PA_LCD_RCMD1               (0x8800000)
+#define BAST_VA_LCD_RCMD1               BAST_IOADDR(0x00700000)
+
+#define BAST_PA_LCD_WCMD1               (0x8000000)
+#define BAST_VA_LCD_WCMD1               BAST_IOADDR(0x00800000)
+
+#define BAST_PA_LCD_RDATA1              (0x9800000)
+#define BAST_VA_LCD_RDATA1              BAST_IOADDR(0x00900000)
+
+#define BAST_PA_LCD_WDATA1              (0x9000000)
+#define BAST_VA_LCD_WDATA1              BAST_IOADDR(0x00A00000)
+
+#define BAST_PA_LCD_RCMD2               (0xA800000)
+#define BAST_VA_LCD_RCMD2               BAST_IOADDR(0x00B00000)
+
+#define BAST_PA_LCD_WCMD2               (0xA000000)
+#define BAST_VA_LCD_WCMD2               BAST_IOADDR(0x00C00000)
+
+#define BAST_PA_LCD_RDATA2              (0xB800000)
+#define BAST_VA_LCD_RDATA2              BAST_IOADDR(0x00D00000)
+
+#define BAST_PA_LCD_WDATA2              (0xB000000)
+#define BAST_VA_LCD_WDATA2              BAST_IOADDR(0x00E00000)
+
+
+/*
+ * 0xE0000000 contains the IO space that is split by speed and
+ * whether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x00000000 to 0x01000000 16MB ISA IO space
+ * 0x01000000 to 0x02000000 16MB ISA memory space
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
+ * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define BAST_VA_MULTISPACE              (0xE0000000)
+
+#define BAST_VA_ISAIO                   (BAST_VA_MULTISPACE + 0x00000000)
+#define BAST_VA_ISAMEM                  (BAST_VA_MULTISPACE + 0x01000000)
+#define BAST_VA_IDEPRI                  (BAST_VA_MULTISPACE + 0x02000000)
+#define BAST_VA_IDEPRIAUX               (BAST_VA_MULTISPACE + 0x02100000)
+#define BAST_VA_IDESEC                  (BAST_VA_MULTISPACE + 0x02200000)
+#define BAST_VA_IDESECAUX               (BAST_VA_MULTISPACE + 0x02300000)
+#define BAST_VA_ASIXNET                 (BAST_VA_MULTISPACE + 0x02400000)
+#define BAST_VA_DM9000                  (BAST_VA_MULTISPACE + 0x02500000)
+#define BAST_VA_SUPERIO                 (BAST_VA_MULTISPACE + 0x02600000)
+
+#define BAST_VAM_CS2                    (0x00000000)
+#define BAST_VAM_CS3                    (0x04000000)
+#define BAST_VAM_CS4                    (0x08000000)
+#define BAST_VAM_CS5                    (0x0C000000)
+
+/* physical offset addresses for the peripherals */
+
+#define BAST_PA_ISAIO                   (0x00000000)
+#define BAST_PA_ASIXNET                 (0x01000000)
+#define BAST_PA_SUPERIO                 (0x01800000)
+#define BAST_PA_IDEPRI                  (0x02000000)
+#define BAST_PA_IDEPRIAUX               (0x02800000)
+#define BAST_PA_IDESEC                  (0x03000000)
+#define BAST_PA_IDESECAUX               (0x03800000)
+#define BAST_PA_ISAMEM                  (0x04000000)
+#define BAST_PA_DM9000                  (0x05000000)
+
+/* some configurations for the peripherals */
+
+#define BAST_PCSIO                      (BAST_VA_SUPERIO + BAST_VAM_CS2)
+
+#define BAST_ASIXNET_CS                 BAST_VAM_CS5
+#define BAST_DM9000_CS                  BAST_VAM_CS4
+
+#define BAST_IDE_CS     S3C2410_CS5
+
+#endif /* __MACH_S3C24XX_BAST_H */
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
new file mode 100644
index 000000000000..1edd9b2369c5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/clock-dclk.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2004-2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C24XX - definitions for DCLK and CLKOUT registers
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/* clocks that could be registered by external code */
+
+static int s3c24xx_dclk_enable(struct clk *clk, int enable)
+{
+        unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
+
+        if (enable)
+                dclkcon |= clk->ctrlbit;
+        else
+                dclkcon &= ~clk->ctrlbit;
+
+        __raw_writel(dclkcon, S3C24XX_DCLKCON);
+
+        return 0;
+}
+
+static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
+{
+        unsigned long dclkcon;
+        unsigned int uclk;
+
+        if (parent == &clk_upll)
+                uclk = 1;
+        else if (parent == &clk_p)
+                uclk = 0;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        dclkcon = __raw_readl(S3C24XX_DCLKCON);
+
+        if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
+                if (uclk)
+                        dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
+                else
+                        dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
+        } else {
+                if (uclk)
+                        dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
+                else
+                        dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
+        }
+
+        __raw_writel(dclkcon, S3C24XX_DCLKCON);
+
+        return 0;
+}
+static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
+{
+        unsigned long div;
+
+        if ((rate == 0) || !clk->parent)
+                return 0;
+
+        div = clk_get_rate(clk->parent) / rate;
+        if (div < 2)
+                div = 2;
+        else if (div > 16)
+                div = 16;
+
+        return div;
+}
+
+static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
+        unsigned long rate)
+{
+        unsigned long div = s3c24xx_calc_div(clk, rate);
+
+        if (div == 0)
+                return 0;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
+
+        if (div == 0)
+                return -EINVAL;
+
+        if (clk == &s3c24xx_dclk0) {
+                mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
+                        S3C2410_DCLKCON_DCLK0_CMP_MASK;
+                data = S3C2410_DCLKCON_DCLK0_DIV(div) |
+                        S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
+        } else if (clk == &s3c24xx_dclk1) {
+                mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
+                        S3C2410_DCLKCON_DCLK1_CMP_MASK;
+                data = S3C2410_DCLKCON_DCLK1_DIV(div) |
+                        S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
+        } else
+                return -EINVAL;
+
+        clk->rate = clk_get_rate(clk->parent) / div;
+        __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
+                S3C24XX_DCLKCON);
+        return clk->rate;
+}
+static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
+{
+        unsigned long mask;
+        unsigned long source;
+
+        /* calculate the MISCCR setting for the clock */
+
+        if (parent == &clk_mpll)
+                source = S3C2410_MISCCR_CLK0_MPLL;
+        else if (parent == &clk_upll)
+                source = S3C2410_MISCCR_CLK0_UPLL;
+        else if (parent == &clk_f)
+                source = S3C2410_MISCCR_CLK0_FCLK;
+        else if (parent == &clk_h)
+                source = S3C2410_MISCCR_CLK0_HCLK;
+        else if (parent == &clk_p)
+                source = S3C2410_MISCCR_CLK0_PCLK;
+        else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
+                source = S3C2410_MISCCR_CLK0_DCLK0;
+        else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
+                source = S3C2410_MISCCR_CLK0_DCLK0;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        if (clk == &s3c24xx_clkout0)
+                mask = S3C2410_MISCCR_CLK0_MASK;
+        else {
+                source <<= 4;
+                mask = S3C2410_MISCCR_CLK1_MASK;
+        }
+
+        s3c2410_modify_misccr(mask, source);
+        return 0;
+}
+
+/* external clock definitions */
+
+static struct clk_ops dclk_ops = {
+        .set_parent     = s3c24xx_dclk_setparent,
+        .set_rate       = s3c24xx_set_dclk_rate,
+        .round_rate     = s3c24xx_round_dclk_rate,
+};
+
+struct clk s3c24xx_dclk0 = {
+        .name           = "dclk0",
+        .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
+        .enable         = s3c24xx_dclk_enable,
+        .ops            = &dclk_ops,
+};
+
+struct clk s3c24xx_dclk1 = {
+        .name           = "dclk1",
+        .ctrlbit        = S3C2410_DCLKCON_DCLK1EN,
+        .enable         = s3c24xx_dclk_enable,
+        .ops            = &dclk_ops,
+};
+
+static struct clk_ops clkout_ops = {
+        .set_parent     = s3c24xx_clkout_setparent,
+};
+
+struct clk s3c24xx_clkout0 = {
+        .name           = "clkout0",
+        .ops            = &clkout_ops,
+};
+
+struct clk s3c24xx_clkout1 = {
+        .name           = "clkout1",
+        .ops            = &clkout_ops,
+};
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
new file mode 100644
index 000000000000..641266f3d152
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410,S3C2440,S3C2442 Clock control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/s3c2410.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+int s3c2410_clkcon_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->ctrlbit;
+        unsigned long clkcon;
+
+        clkcon = __raw_readl(S3C2410_CLKCON);
+
+        if (enable)
+                clkcon |= clocks;
+        else
+                clkcon &= ~clocks;
+
+        /* ensure none of the special function bits set */
+        clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
+
+        __raw_writel(clkcon, S3C2410_CLKCON);
+
+        return 0;
+}
+
+static int s3c2410_upll_enable(struct clk *clk, int enable)
+{
+        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
+        unsigned long orig = clkslow;
+
+        if (enable)
+                clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
+        else
+                clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
+
+        __raw_writel(clkslow, S3C2410_CLKSLOW);
+
+        /* if we started the UPLL, then allow to settle */
+
+        if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
+                udelay(200);
+
+        return 0;
+}
+
+/* standard clock definitions */
+
+static struct clk init_clocks_off[] = {
+        {
+                .name           = "nand",
+                .parent         = &clk_h,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_NAND,
+        }, {
+                .name           = "sdi",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_SDI,
+        }, {
+                .name           = "adc",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_ADC,
+        }, {
+                .name           = "i2c",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_IIC,
+        }, {
+                .name           = "iis",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_IIS,
+        }, {
+                .name           = "spi",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_SPI,
+        }
+};
+
+static struct clk init_clocks[] = {
+        {
+                .name           = "lcd",
+                .parent         = &clk_h,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_LCDC,
+        }, {
+                .name           = "gpio",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_GPIO,
+        }, {
+                .name           = "usb-host",
+                .parent         = &clk_h,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_USBH,
+        }, {
+                .name           = "usb-device",
+                .parent         = &clk_h,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_USBD,
+        }, {
+                .name           = "timers",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_PWMT,
+        }, {
+                .name           = "uart",
+                .devname        = "s3c2410-uart.0",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_UART0,
+        }, {
+                .name           = "uart",
+                .devname        = "s3c2410-uart.1",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_UART1,
+        }, {
+                .name           = "uart",
+                .devname        = "s3c2410-uart.2",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_UART2,
+        }, {
+                .name           = "rtc",
+                .parent         = &clk_p,
+                .enable         = s3c2410_clkcon_enable,
+                .ctrlbit        = S3C2410_CLKCON_RTC,
+        }, {
+                .name           = "watchdog",
+                .parent         = &clk_p,
+                .ctrlbit        = 0,
+        }, {
+                .name           = "usb-bus-host",
+                .parent         = &clk_usb_bus,
+        }, {
+                .name           = "usb-bus-gadget",
+                .parent         = &clk_usb_bus,
+        },
+};
+
+/* s3c2410_baseclk_add()
+ *
+ * Add all the clocks used by the s3c2410 or compatible CPUs
+ * such as the S3C2440 and S3C2442.
+ *
+ * We cannot use a system device as we are needed before any
+ * of the init-calls that initialise the devices are actually
+ * done.
+*/
+
+int __init s3c2410_baseclk_add(void)
+{
+        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
+        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
+        struct clk *clkp;
+        struct clk *xtal;
+        int ret;
+        int ptr;
+
+        clk_upll.enable = s3c2410_upll_enable;
+
+        if (s3c24xx_register_clock(&clk_usb_bus) < 0)
+                printk(KERN_ERR "failed to register usb bus clock\n");
+
+        /* register clocks from clock array */
+
+        clkp = init_clocks;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+                /* ensure that we note the clock state */
+
+                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+
+        /* We must be careful disabling the clocks we are not intending to
+         * be using at boot time, as subsystems such as the LCD which do
+         * their own DMA requests to the bus can cause the system to lockup
+         * if they where in the middle of requesting bus access.
+         *
+         * Disabling the LCD clock if the LCD is active is very dangerous,
+         * and therefore the bootloader should be careful to not enable
+         * the LCD clock if it is not needed.
+        */
+
+        /* install (and disable) the clocks we do not need immediately */
+
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+        /* show the clock-slow value */
+
+        xtal = clk_get(NULL, "xtal");
+
+        printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
+               print_mhz(clk_get_rate(xtal) /
+                         ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
+               (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
+               (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
+               (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
+
+        s3c_pwmclk_init();
+        return 0;
+}
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index c2f596e7bc2d..ed6276fcaa3b 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -15,4 +15,6 @@
 void s3c2410_restart(char mode, const char *cmd);
 void s3c244x_restart(char mode, const char *cmd);
 
+extern struct syscore_ops s3c24xx_irq_syscore_ops;
+
 #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
new file mode 100644
index 000000000000..9b7b4289d66c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - debugfs status support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/export.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/err.h>
+
+#include <plat/cpu-freq-core.h>
+
+static struct dentry *dbgfs_root;
+static struct dentry *dbgfs_file_io;
+static struct dentry *dbgfs_file_info;
+static struct dentry *dbgfs_file_board;
+
+#define print_ns(x) ((x) / 10), ((x) % 10)
+
+static void show_max(struct seq_file *seq, struct s3c_freq *f)
+{
+        seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
+                   f->fclk, f->hclk, f->pclk, f->armclk);
+}
+
+static int board_show(struct seq_file *seq, void *p)
+{
+        struct s3c_cpufreq_config *cfg;
+        struct s3c_cpufreq_board *brd;
+
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+
+        brd = cfg->board;
+        if (!brd) {
+                seq_printf(seq, "no board definition set?\n");
+                return 0;
+        }
+
+        seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
+        seq_printf(seq, "auto_io=%u\n", brd->auto_io);
+        seq_printf(seq, "need_io=%u\n", brd->need_io);
+
+        show_max(seq, &brd->max);
+
+
+        return 0;
+}
+
+static int fops_board_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, board_show, NULL);
+}
+
+static const struct file_operations fops_board = {
+        .open           = fops_board_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+
+static int info_show(struct seq_file *seq, void *p)
+{
+        struct s3c_cpufreq_config *cfg;
+
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+
+        seq_printf(seq, "  FCLK %ld Hz\n", cfg->freq.fclk);
+        seq_printf(seq, "  HCLK %ld Hz (%lu.%lu ns)\n",
+                   cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
+        seq_printf(seq, "  PCLK %ld Hz\n", cfg->freq.hclk);
+        seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
+        seq_printf(seq, "\n");
+
+        show_max(seq, &cfg->max);
+
+        seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
+                   cfg->divs.h_divisor, cfg->divs.p_divisor,
+                   cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
+        seq_printf(seq, "\n");
+
+        seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
+
+        return 0;
+}
+
+static int fops_info_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, info_show, NULL);
+}
+
+static const struct file_operations fops_info = {
+        .open           = fops_info_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+
+static int io_show(struct seq_file *seq, void *p)
+{
+        void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
+        struct s3c_cpufreq_config *cfg;
+        struct s3c_iotimings *iot;
+        union s3c_iobank *iob;
+        int bank;
+
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+
+        show_bank = cfg->info->debug_io_show;
+        if (!show_bank) {
+                seq_printf(seq, "no code to show bank timing\n");
+                return 0;
+        }
+
+        iot = s3c_cpufreq_getiotimings();
+        if (!iot) {
+                seq_printf(seq, "no io timings registered\n");
+                return 0;
+        }
+
+        seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                iob = &iot->bank[bank];
+
+                seq_printf(seq, "bank %d: ", bank);
+
+                if (!iob->io_2410) {
+                        seq_printf(seq, "nothing set\n");
+                        continue;
+                }
+
+                show_bank(seq, cfg, iob);
+        }
+
+        return 0;
+}
+
+static int fops_io_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, io_show, NULL);
+}
+
+static const struct file_operations fops_io = {
+        .open           = fops_io_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+
+
+static int __init s3c_freq_debugfs_init(void)
+{
+        dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
+        if (IS_ERR(dbgfs_root)) {
+                printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
+                return PTR_ERR(dbgfs_root);
+        }
+
+        dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
+                                            NULL, &fops_io);
+
+        dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
+                                              NULL, &fops_info);
+
+        dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
+                                               NULL, &fops_board);
+
+        return 0;
+}
+
+late_initcall(s3c_freq_debugfs_init);
+
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
new file mode 100644
index 000000000000..cfa0dd8723ec
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
+
+static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        u32 clkdiv = 0;
+
+        if (cfg->divs.h_divisor == 2)
+                clkdiv |= S3C2410_CLKDIVN_HDIVN;
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2410_CLKDIVN_PDIVN;
+
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+}
+
+static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long hclk, fclk, pclk;
+        unsigned int hdiv, pdiv;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        hclk_max = cfg->max.hclk;
+
+        cfg->freq.armclk = fclk;
+
+        s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
+                      __func__, fclk, hclk_max);
+
+        hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
+        hclk = fclk / hdiv;
+
+        if (hclk > cfg->max.hclk) {
+                s3c_freq_dbg("%s: hclk too big\n", __func__);
+                return -EINVAL;
+        }
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+        pclk = hclk / pdiv;
+
+        if (pclk > cfg->max.pclk) {
+                s3c_freq_dbg("%s: pclk too big\n", __func__);
+                return -EINVAL;
+        }
+
+        pdiv *= hdiv;
+
+        /* record the result */
+        cfg->divs.p_divisor = pdiv;
+        cfg->divs.h_divisor = hdiv;
+
+        return 0;
+}
+
+static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+
+        /* transition latency is about 5ms worst-case, so
+         * set 10ms to be sure */
+        .latency        = 10000000,
+
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 12,
+
+        .need_pll       = 1,
+
+        .name           = "s3c2410",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .resume_clocks  = s3c2410_setup_clocks,
+
+        .set_fvco       = s3c2410_set_fvco,
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2410_cpufreq_setdivs,
+        .calc_divs      = s3c2410_cpufreq_calcdivs,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+
+static int s3c2410_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
+{
+        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
+}
+
+static struct subsys_interface s3c2410_cpufreq_interface = {
+        .name           = "s3c2410_cpufreq",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_cpufreq_add,
+};
+
+static int __init s3c2410_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2410_cpufreq_interface);
+}
+arch_initcall(s3c2410_cpufreq_init);
+
+static int s3c2410a_cpufreq_add(struct device *dev,
+                                struct subsys_interface *sif)
+{
+        /* alter the maximum freq settings for S3C2410A. If a board knows
+         * it only has a maximum of 200, then it should register its own
+         * limits. */
+
+        s3c2410_cpufreq_info.max.fclk = 266000000;
+        s3c2410_cpufreq_info.max.hclk = 133000000;
+        s3c2410_cpufreq_info.max.pclk =  66500000;
+        s3c2410_cpufreq_info.name = "s3c2410a";
+
+        return s3c2410_cpufreq_add(dev, sif);
+}
+
+static struct subsys_interface s3c2410a_cpufreq_interface = {
+        .name           = "s3c2410a_cpufreq",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410a_cpufreq_add,
+};
+
+static int __init s3c2410a_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2410a_cpufreq_interface);
+}
+arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
new file mode 100644
index 000000000000..8bf0f3a77476
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 CPU Frequency scalling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+#include "s3c2412.h"
+
+/* our clock resources. */
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+
+static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv, armdiv, dvs;
+        unsigned long hclk, fclk, armclk, armdiv_clk;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+
+        /* We can't run hclk above armclk as at the best we have to
+         * have armclk and hclk in dvs mode. */
+
+        if (hclk_max > armclk)
+                hclk_max = armclk;
+
+        s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
+                     __func__, fclk, armclk, hclk_max);
+        s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
+                     __func__, cfg->freq.fclk, cfg->freq.armclk,
+                     cfg->freq.hclk, cfg->freq.pclk);
+
+        armdiv = fclk / armclk;
+
+        if (armdiv < 1)
+                armdiv = 1;
+        if (armdiv > 2)
+                armdiv = 2;
+
+        cfg->divs.arm_divisor = armdiv;
+        armdiv_clk = fclk / armdiv;
+
+        hdiv = armdiv_clk / hclk_max;
+        if (hdiv < 1)
+                hdiv = 1;
+
+        cfg->freq.hclk = hclk = armdiv_clk / hdiv;
+
+        /* set dvs depending on whether we reached armclk or not. */
+        cfg->divs.dvs = dvs = armclk < armdiv_clk;
+
+        /* update the actual armclk we achieved. */
+        cfg->freq.armclk = dvs ? hclk : armdiv_clk;
+
+        s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
+                     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
+
+        if (hdiv > 4)
+                goto invalid;
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+
+        cfg->freq.pclk = hclk / pdiv;
+
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+
+        if (pdiv > 2)
+                goto invalid;
+
+        pdiv *= hdiv;
+
+        /* store the result, and then return */
+
+        cfg->divs.h_divisor = hdiv * armdiv;
+        cfg->divs.p_divisor = pdiv * armdiv;
+
+        return 0;
+
+invalid:
+        return -EINVAL;
+}
+
+static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv;
+        unsigned long olddiv;
+
+        olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
+
+        /* clear off current clock info */
+
+        clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
+        clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
+        clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
+
+        if (cfg->divs.arm_divisor == 2)
+                clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
+
+        clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2412_CLKDIVN_PDIVN;
+
+        s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+
+static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        unsigned long refresh;
+
+        s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
+                     board->refresh, cfg->freq.hclk);
+
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * by 10 each to ensure that we do not overflow 32 bit numbers. This
+         * should work for HCLK up to 133MHz and refresh period up to 30usec.
+         */
+
+        refresh = (board->refresh / 10);
+        refresh *= (cfg->freq.hclk / 100);
+        refresh /= (1 * 1000 * 1000);   /* 10^6 */
+
+        s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
+        __raw_writel(refresh, S3C2412_REFRESH);
+}
+
+/* set the default cpu frequency information, based on an 200MHz part
+ * as we have no other way of detecting the speed rating in software.
+ */
+
+static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+
+        .latency        = 5000000, /* 5ms */
+
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 16,
+
+        .name           = "s3c2412",
+        .set_refresh    = s3c2412_cpufreq_setrefresh,
+        .set_divs       = s3c2412_cpufreq_setdivs,
+        .calc_divs      = s3c2412_cpufreq_calcdivs,
+
+        .calc_iotiming  = s3c2412_iotiming_calc,
+        .set_iotiming   = s3c2412_iotiming_set,
+        .get_iotiming   = s3c2412_iotiming_get,
+
+        .resume_clocks  = s3c2412_setup_clocks,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
+};
+
+static int s3c2412_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
+{
+        unsigned long fclk_rate;
+
+        hclk = clk_get(NULL, "hclk");
+        if (IS_ERR(hclk)) {
+                printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
+                return -ENOENT;
+        }
+
+        fclk = clk_get(NULL, "fclk");
+        if (IS_ERR(fclk)) {
+                printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
+                goto err_fclk;
+        }
+
+        fclk_rate = clk_get_rate(fclk);
+        if (fclk_rate > 200000000) {
+                printk(KERN_INFO
+                       "%s: fclk %ld MHz, assuming 266MHz capable part\n",
+                       __func__, fclk_rate / 1000000);
+                s3c2412_cpufreq_info.max.fclk = 266000000;
+                s3c2412_cpufreq_info.max.hclk = 133000000;
+                s3c2412_cpufreq_info.max.pclk =  66000000;
+        }
+
+        armclk = clk_get(NULL, "armclk");
+        if (IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
+                goto err_armclk;
+        }
+
+        xtal = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal)) {
+                printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
+                goto err_xtal;
+        }
+
+        return s3c_cpufreq_register(&s3c2412_cpufreq_info);
+
+err_xtal:
+        clk_put(armclk);
+err_armclk:
+        clk_put(fclk);
+err_fclk:
+        clk_put(hclk);
+
+        return -ENOENT;
+}
+
+static struct subsys_interface s3c2412_cpufreq_interface = {
+        .name           = "s3c2412_cpufreq",
+        .subsys         = &s3c2412_subsys,
+        .add_dev        = s3c2412_cpufreq_add,
+};
+
+static int s3c2412_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2412_cpufreq_interface);
+}
+arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
new file mode 100644
index 000000000000..72b2cc8a5a85
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
@@ -0,0 +1,312 @@
+/*
+ * Copyright (c) 2006-2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@simtec.co.uk>
+ *
+ * S3C2440/S3C2442 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+#include <plat/clock.h>
+
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+
+static inline int within_khz(unsigned long a, unsigned long b)
+{
+        long diff = a - b;
+
+        return (diff >= -1000 && diff <= 1000);
+}
+
+/**
+ * s3c2440_cpufreq_calcdivs - calculate divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Calcualte the divider values for the given frequency settings
+ * specified in @cfg. The values are stored in @cfg for later use
+ * by the relevant set routine if the request settings can be reached.
+ */
+int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv;
+        unsigned long hclk, fclk, armclk;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+
+        s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
+                     __func__, fclk, armclk, hclk_max);
+
+        if (armclk > fclk) {
+                printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
+                armclk = fclk;
+        }
+
+        /* if we are in DVS, we need HCLK to be <= ARMCLK */
+        if (armclk < fclk && armclk < hclk_max)
+                hclk_max = armclk;
+
+        for (hdiv = 1; hdiv < 9; hdiv++) {
+                if (hdiv == 5 || hdiv == 7)
+                        hdiv++;
+
+                hclk = (fclk / hdiv);
+                if (hclk <= hclk_max || within_khz(hclk, hclk_max))
+                        break;
+        }
+
+        s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
+
+        if (hdiv > 8)
+                goto invalid;
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+
+        if (pdiv > 2)
+                goto invalid;
+
+        pdiv *= hdiv;
+
+        /* calculate a valid armclk */
+
+        if (armclk < hclk)
+                armclk = hclk;
+
+        /* if we're running armclk lower than fclk, this really means
+         * that the system should go into dvs mode, which means that
+         * armclk is connected to hclk. */
+        if (armclk < fclk) {
+                cfg->divs.dvs = 1;
+                armclk = hclk;
+        } else
+                cfg->divs.dvs = 0;
+
+        cfg->freq.armclk = armclk;
+
+        /* store the result, and then return */
+
+        cfg->divs.h_divisor = hdiv;
+        cfg->divs.p_divisor = pdiv;
+
+        return 0;
+
+ invalid:
+        return -EINVAL;
+}
+
+#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
+                           S3C2440_CAMDIVN_HCLK4_HALF)
+
+/**
+ * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Set the divisors from the settings in @cfg, which where generated
+ * during the calculation phase by s3c2440_cpufreq_calcdivs().
+ */
+static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv, camdiv;
+
+        s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
+                     cfg->divs.h_divisor, cfg->divs.p_divisor);
+
+        clkdiv = __raw_readl(S3C2410_CLKDIVN);
+        camdiv = __raw_readl(S3C2440_CAMDIVN);
+
+        clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
+        camdiv &= ~CAMDIVN_HCLK_HALF;
+
+        switch (cfg->divs.h_divisor) {
+        case 1:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
+                break;
+
+        case 2:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
+                break;
+
+        case 6:
+                camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
+        case 3:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
+                break;
+
+        case 8:
+                camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
+        case 4:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
+                break;
+
+        default:
+                BUG();  /* we don't expect to get here. */
+        }
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2440_CLKDIVN_PDIVN;
+
+        /* todo - set pclk. */
+
+        /* Write the divisors first with hclk intentionally halved so that
+         * when we write clkdiv we will under-frequency instead of over. We
+         * then make a short delay and remove the hclk halving if necessary.
+         */
+
+        __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        ndelay(20);
+        __raw_writel(camdiv, S3C2440_CAMDIVN);
+
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+
+static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
+                        int *divs,
+                        struct cpufreq_frequency_table *table,
+                        size_t table_size)
+{
+        unsigned long freq;
+        int index = 0;
+        int div;
+
+        for (div = *divs; div > 0; div = *divs++) {
+                freq = fclk / div;
+
+                if (freq > max_hclk && div != 1)
+                        continue;
+
+                freq /= 1000; /* table is in kHz */
+                index = s3c_cpufreq_addfreq(table, index, table_size, freq);
+                if (index < 0)
+                        break;
+        }
+
+        return index;
+}
+
+static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
+
+static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
+                                     struct cpufreq_frequency_table *table,
+                                     size_t table_size)
+{
+        int ret;
+
+        WARN_ON(cfg->info == NULL);
+        WARN_ON(cfg->board == NULL);
+
+        ret = run_freq_for(cfg->info->max.hclk,
+                           cfg->info->max.fclk,
+                           hclk_divs,
+                           table, table_size);
+
+        s3c_freq_dbg("%s: returning %d\n", __func__, ret);
+
+        return ret;
+}
+
+struct s3c_cpufreq_info s3c2440_cpufreq_info = {
+        .max            = {
+                .fclk   = 400000000,
+                .hclk   = 133333333,
+                .pclk   =  66666666,
+        },
+
+        .locktime_m     = 300,
+        .locktime_u     = 300,
+        .locktime_bits  = 16,
+
+        .name           = "s3c244x",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .set_fvco       = s3c2410_set_fvco,
+
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2440_cpufreq_setdivs,
+        .calc_divs      = s3c2440_cpufreq_calcdivs,
+        .calc_freqtable = s3c2440_cpufreq_calctable,
+
+        .resume_clocks  = s3c244x_setup_clocks,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+
+static int s3c2440_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
+{
+        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
+        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+        fclk = s3c_cpufreq_clk_get(NULL, "fclk");
+        armclk = s3c_cpufreq_clk_get(NULL, "armclk");
+
+        if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: failed to get clocks\n", __func__);
+                return -ENOENT;
+        }
+
+        return s3c_cpufreq_register(&s3c2440_cpufreq_info);
+}
+
+static struct subsys_interface s3c2440_cpufreq_interface = {
+        .name           = "s3c2440_cpufreq",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_cpufreq_add,
+};
+
+static int s3c2440_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2440_cpufreq_interface);
+}
+
+/* arch_initcall adds the clocks we need, so use subsys_initcall. */
+subsys_initcall(s3c2440_cpufreq_init);
+
+static struct subsys_interface s3c2442_cpufreq_interface = {
+        .name           = "s3c2442_cpufreq",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_cpufreq_add,
+};
+
+static int s3c2442_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2442_cpufreq_interface);
+}
+subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
new file mode 100644
index 000000000000..ddd8280e3875
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu-freq-core.h>
+
+#include "regs-mem.h"
+
+/**
+ * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
+ * @cfg: The frequency configuration
+ *
+ * Set the SDRAM refresh value appropriately for the configured
+ * frequency.
+ */
+void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        unsigned long refresh;
+        unsigned long refval;
+
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * down to ensure that we do not overflow 32 bit numbers.
+         *
+         * This should work for HCLK up to 133MHz and refresh period up
+         * to 30usec.
+         */
+
+        refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
+        refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
+        refresh = (1 << 11) + 1 - refresh;
+
+        s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
+
+        refval = __raw_readl(S3C2410_REFRESH);
+        refval &= ~((1 << 12) - 1);
+        refval |= refresh;
+        __raw_writel(refval, S3C2410_REFRESH);
+}
+
+/**
+ * s3c2410_set_fvco - set the PLL value
+ * @cfg: The frequency configuration
+ */
+void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
+{
+        __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
+}
diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c
new file mode 100644
index 000000000000..5f181e733eee
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq.c
@@ -0,0 +1,715 @@
+/*
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/cpu.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/sysfs.h>
+#include <linux/slab.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+#include <mach/regs-clock.h>
+
+/* note, cpufreq support deals in kHz, no Hz */
+
+static struct cpufreq_driver s3c24xx_driver;
+static struct s3c_cpufreq_config cpu_cur;
+static struct s3c_iotimings s3c24xx_iotiming;
+static struct cpufreq_frequency_table *pll_reg;
+static unsigned int last_target = ~0;
+static unsigned int ftab_size;
+static struct cpufreq_frequency_table *ftab;
+
+static struct clk *_clk_mpll;
+static struct clk *_clk_xtal;
+static struct clk *clk_fclk;
+static struct clk *clk_hclk;
+static struct clk *clk_pclk;
+static struct clk *clk_arm;
+
+#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
+struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
+{
+        return &cpu_cur;
+}
+
+struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
+{
+        return &s3c24xx_iotiming;
+}
+#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
+
+static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long fclk, pclk, hclk, armclk;
+
+        cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
+        cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
+        cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
+        cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
+
+        cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
+        cfg->pll.frequency = fclk;
+
+        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
+
+        cfg->divs.h_divisor = fclk / hclk;
+        cfg->divs.p_divisor = fclk / pclk;
+}
+
+static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long pll = cfg->pll.frequency;
+
+        cfg->freq.fclk = pll;
+        cfg->freq.hclk = pll / cfg->divs.h_divisor;
+        cfg->freq.pclk = pll / cfg->divs.p_divisor;
+
+        /* convert hclk into 10ths of nanoseconds for io calcs */
+        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
+}
+
+static inline int closer(unsigned int target, unsigned int n, unsigned int c)
+{
+        int diff_cur = abs(target - c);
+        int diff_new = abs(target - n);
+
+        return (diff_new < diff_cur);
+}
+
+static void s3c_cpufreq_show(const char *pfx,
+                                 struct s3c_cpufreq_config *cfg)
+{
+        s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
+                     pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
+                     cfg->freq.hclk, cfg->divs.h_divisor,
+                     cfg->freq.pclk, cfg->divs.p_divisor);
+}
+
+/* functions to wrapper the driver info calls to do the cpu specific work */
+
+static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
+{
+        if (cfg->info->set_iotiming)
+                (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
+}
+
+static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
+{
+        if (cfg->info->calc_iotiming)
+                return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
+
+        return 0;
+}
+
+static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_refresh)(cfg);
+}
+
+static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_divs)(cfg);
+}
+
+static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        return (cfg->info->calc_divs)(cfg);
+}
+
+static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_fvco)(cfg);
+}
+
+static inline void s3c_cpufreq_resume_clocks(void)
+{
+        cpu_cur.info->resume_clocks();
+}
+
+static inline void s3c_cpufreq_updateclk(struct clk *clk,
+                                         unsigned int freq)
+{
+        clk_set_rate(clk, freq);
+}
+
+static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
+                                 unsigned int target_freq,
+                                 struct cpufreq_frequency_table *pll)
+{
+        struct s3c_cpufreq_freqs freqs;
+        struct s3c_cpufreq_config cpu_new;
+        unsigned long flags;
+
+        cpu_new = cpu_cur;  /* copy new from current */
+
+        s3c_cpufreq_show("cur", &cpu_cur);
+
+        /* TODO - check for DMA currently outstanding */
+
+        cpu_new.pll = pll ? *pll : cpu_cur.pll;
+
+        if (pll)
+                freqs.pll_changing = 1;
+
+        /* update our frequencies */
+
+        cpu_new.freq.armclk = target_freq;
+        cpu_new.freq.fclk = cpu_new.pll.frequency;
+
+        if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
+                printk(KERN_ERR "no divisors for %d\n", target_freq);
+                goto err_notpossible;
+        }
+
+        s3c_freq_dbg("%s: got divs\n", __func__);
+
+        s3c_cpufreq_calc(&cpu_new);
+
+        s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
+
+        if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
+                if (s3c_cpufreq_calcio(&cpu_new) < 0) {
+                        printk(KERN_ERR "%s: no IO timings\n", __func__);
+                        goto err_notpossible;
+                }
+        }
+
+        s3c_cpufreq_show("new", &cpu_new);
+
+        /* setup our cpufreq parameters */
+
+        freqs.old = cpu_cur.freq;
+        freqs.new = cpu_new.freq;
+
+        freqs.freqs.cpu = 0;
+        freqs.freqs.old = cpu_cur.freq.armclk / 1000;
+        freqs.freqs.new = cpu_new.freq.armclk / 1000;
+
+        /* update f/h/p clock settings before we issue the change
+         * notification, so that drivers do not need to do anything
+         * special if they want to recalculate on CPUFREQ_PRECHANGE. */
+
+        s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
+        s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
+        s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
+        s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
+
+        /* start the frequency change */
+
+        if (policy)
+                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
+
+        /* If hclk is staying the same, then we do not need to
+         * re-write the IO or the refresh timings whilst we are changing
+         * speed. */
+
+        local_irq_save(flags);
+
+        /* is our memory clock slowing down? */
+        if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
+                s3c_cpufreq_setrefresh(&cpu_new);
+                s3c_cpufreq_setio(&cpu_new);
+        }
+
+        if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
+                /* not changing PLL, just set the divisors */
+
+                s3c_cpufreq_setdivs(&cpu_new);
+        } else {
+                if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
+                        /* slow the cpu down, then set divisors */
+
+                        s3c_cpufreq_setfvco(&cpu_new);
+                        s3c_cpufreq_setdivs(&cpu_new);
+                } else {
+                        /* set the divisors, then speed up */
+
+                        s3c_cpufreq_setdivs(&cpu_new);
+                        s3c_cpufreq_setfvco(&cpu_new);
+                }
+        }
+
+        /* did our memory clock speed up */
+        if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
+                s3c_cpufreq_setrefresh(&cpu_new);
+                s3c_cpufreq_setio(&cpu_new);
+        }
+
+        /* update our current settings */
+        cpu_cur = cpu_new;
+
+        local_irq_restore(flags);
+
+        /* notify everyone we've done this */
+        if (policy)
+                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
+
+        s3c_freq_dbg("%s: finished\n", __func__);
+        return 0;
+
+ err_notpossible:
+        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
+        return -EINVAL;
+}
+
+/* s3c_cpufreq_target
+ *
+ * called by the cpufreq core to adjust the frequency that the CPU
+ * is currently running at.
+ */
+
+static int s3c_cpufreq_target(struct cpufreq_policy *policy,
+                              unsigned int target_freq,
+                              unsigned int relation)
+{
+        struct cpufreq_frequency_table *pll;
+        unsigned int index;
+
+        /* avoid repeated calls which cause a needless amout of duplicated
+         * logging output (and CPU time as the calculation process is
+         * done) */
+        if (target_freq == last_target)
+                return 0;
+
+        last_target = target_freq;
+
+        s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
+                     __func__, policy, target_freq, relation);
+
+        if (ftab) {
+                if (cpufreq_frequency_table_target(policy, ftab,
+                                                   target_freq, relation,
+                                                   &index)) {
+                        s3c_freq_dbg("%s: table failed\n", __func__);
+                        return -EINVAL;
+                }
+
+                s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
+                             target_freq, index, ftab[index].frequency);
+                target_freq = ftab[index].frequency;
+        }
+
+        target_freq *= 1000;  /* convert target to Hz */
+
+        /* find the settings for our new frequency */
+
+        if (!pll_reg || cpu_cur.lock_pll) {
+                /* either we've not got any PLL values, or we've locked
+                 * to the current one. */
+                pll = NULL;
+        } else {
+                struct cpufreq_policy tmp_policy;
+                int ret;
+
+                /* we keep the cpu pll table in Hz, to ensure we get an
+                 * accurate value for the PLL output. */
+
+                tmp_policy.min = policy->min * 1000;
+                tmp_policy.max = policy->max * 1000;
+                tmp_policy.cpu = policy->cpu;
+
+                /* cpufreq_frequency_table_target uses a pointer to 'index'
+                 * which is the number of the table entry, not the value of
+                 * the table entry's index field. */
+
+                ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
+                                                     target_freq, relation,
+                                                     &index);
+
+                if (ret < 0) {
+                        printk(KERN_ERR "%s: no PLL available\n", __func__);
+                        goto err_notpossible;
+                }
+
+                pll = pll_reg + index;
+
+                s3c_freq_dbg("%s: target %u => %u\n",
+                             __func__, target_freq, pll->frequency);
+
+                target_freq = pll->frequency;
+        }
+
+        return s3c_cpufreq_settarget(policy, target_freq, pll);
+
+ err_notpossible:
+        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
+        return -EINVAL;
+}
+
+static unsigned int s3c_cpufreq_get(unsigned int cpu)
+{
+        return clk_get_rate(clk_arm) / 1000;
+}
+
+struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
+{
+        struct clk *clk;
+
+        clk = clk_get(dev, name);
+        if (IS_ERR(clk))
+                printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
+
+        return clk;
+}
+
+static int s3c_cpufreq_init(struct cpufreq_policy *policy)
+{
+        printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
+
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        policy->cur = s3c_cpufreq_get(0);
+        policy->min = policy->cpuinfo.min_freq = 0;
+        policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+        /* feed the latency information from the cpu driver */
+        policy->cpuinfo.transition_latency = cpu_cur.info->latency;
+
+        if (ftab)
+                cpufreq_frequency_table_cpuinfo(policy, ftab);
+
+        return 0;
+}
+
+static __init int s3c_cpufreq_initclks(void)
+{
+        _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
+        _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
+        clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
+        clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+        clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
+        clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
+
+        if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
+            IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
+                printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
+                return -ENOENT;
+        }
+
+        printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
+               clk_get_rate(clk_fclk) / 1000,
+               clk_get_rate(clk_hclk) / 1000,
+               clk_get_rate(clk_pclk) / 1000,
+               clk_get_rate(clk_arm) / 1000);
+
+        return 0;
+}
+
+static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
+{
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static struct cpufreq_frequency_table suspend_pll;
+static unsigned int suspend_freq;
+
+static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
+{
+        suspend_pll.frequency = clk_get_rate(_clk_mpll);
+        suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
+        suspend_freq = s3c_cpufreq_get(0) * 1000;
+
+        return 0;
+}
+
+static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
+{
+        int ret;
+
+        s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
+
+        last_target = ~0;       /* invalidate last_target setting */
+
+        /* first, find out what speed we resumed at. */
+        s3c_cpufreq_resume_clocks();
+
+        /* whilst we will be called later on, we try and re-set the
+         * cpu frequencies as soon as possible so that we do not end
+         * up resuming devices and then immediately having to re-set
+         * a number of settings once these devices have restarted.
+         *
+         * as a note, it is expected devices are not used until they
+         * have been un-suspended and at that time they should have
+         * used the updated clock settings.
+         */
+
+        ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
+        if (ret) {
+                printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
+                return ret;
+        }
+
+        return 0;
+}
+#else
+#define s3c_cpufreq_resume NULL
+#define s3c_cpufreq_suspend NULL
+#endif
+
+static struct cpufreq_driver s3c24xx_driver = {
+        .flags          = CPUFREQ_STICKY,
+        .verify         = s3c_cpufreq_verify,
+        .target         = s3c_cpufreq_target,
+        .get            = s3c_cpufreq_get,
+        .init           = s3c_cpufreq_init,
+        .suspend        = s3c_cpufreq_suspend,
+        .resume         = s3c_cpufreq_resume,
+        .name           = "s3c24xx",
+};
+
+
+int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
+{
+        if (!info || !info->name) {
+                printk(KERN_ERR "%s: failed to pass valid information\n",
+                       __func__);
+                return -EINVAL;
+        }
+
+        printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
+               info->name);
+
+        /* check our driver info has valid data */
+
+        BUG_ON(info->set_refresh == NULL);
+        BUG_ON(info->set_divs == NULL);
+        BUG_ON(info->calc_divs == NULL);
+
+        /* info->set_fvco is optional, depending on whether there
+         * is a need to set the clock code. */
+
+        cpu_cur.info = info;
+
+        /* Note, driver registering should probably update locktime */
+
+        return 0;
+}
+
+int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
+{
+        struct s3c_cpufreq_board *ours;
+
+        if (!board) {
+                printk(KERN_INFO "%s: no board data\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Copy the board information so that each board can make this
+         * initdata. */
+
+        ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
+        if (ours == NULL) {
+                printk(KERN_ERR "%s: no memory\n", __func__);
+                return -ENOMEM;
+        }
+
+        *ours = *board;
+        cpu_cur.board = ours;
+
+        return 0;
+}
+
+int __init s3c_cpufreq_auto_io(void)
+{
+        int ret;
+
+        if (!cpu_cur.info->get_iotiming) {
+                printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
+                return -ENOENT;
+        }
+
+        printk(KERN_INFO "%s: working out IO settings\n", __func__);
+
+        ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
+        if (ret)
+                printk(KERN_ERR "%s: failed to get timings\n", __func__);
+
+        return ret;
+}
+
+/* if one or is zero, then return the other, otherwise return the min */
+#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
+
+/**
+ * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
+ * @dst: The destination structure
+ * @a: One argument.
+ * @b: The other argument.
+ *
+ * Create a minimum of each frequency entry in the 'struct s3c_freq',
+ * unless the entry is zero when it is ignored and the non-zero argument
+ * used.
+ */
+static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
+                                 struct s3c_freq *a, struct s3c_freq *b)
+{
+        dst->fclk = do_min(a->fclk, b->fclk);
+        dst->hclk = do_min(a->hclk, b->hclk);
+        dst->pclk = do_min(a->pclk, b->pclk);
+        dst->armclk = do_min(a->armclk, b->armclk);
+}
+
+static inline u32 calc_locktime(u32 freq, u32 time_us)
+{
+        u32 result;
+
+        result = freq * time_us;
+        result = DIV_ROUND_UP(result, 1000 * 1000);
+
+        return result;
+}
+
+static void s3c_cpufreq_update_loctkime(void)
+{
+        unsigned int bits = cpu_cur.info->locktime_bits;
+        u32 rate = (u32)clk_get_rate(_clk_xtal);
+        u32 val;
+
+        if (bits == 0) {
+                WARN_ON(1);
+                return;
+        }
+
+        val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
+        val |= calc_locktime(rate, cpu_cur.info->locktime_m);
+
+        printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
+        __raw_writel(val, S3C2410_LOCKTIME);
+}
+
+static int s3c_cpufreq_build_freq(void)
+{
+        int size, ret;
+
+        if (!cpu_cur.info->calc_freqtable)
+                return -EINVAL;
+
+        kfree(ftab);
+        ftab = NULL;
+
+        size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
+        size++;
+
+        ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
+        if (!ftab) {
+                printk(KERN_ERR "%s: no memory for tables\n", __func__);
+                return -ENOMEM;
+        }
+
+        ftab_size = size;
+
+        ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
+        s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
+
+        return 0;
+}
+
+static int __init s3c_cpufreq_initcall(void)
+{
+        int ret = 0;
+
+        if (cpu_cur.info && cpu_cur.board) {
+                ret = s3c_cpufreq_initclks();
+                if (ret)
+                        goto out;
+
+                /* get current settings */
+                s3c_cpufreq_getcur(&cpu_cur);
+                s3c_cpufreq_show("cur", &cpu_cur);
+
+                if (cpu_cur.board->auto_io) {
+                        ret = s3c_cpufreq_auto_io();
+                        if (ret) {
+                                printk(KERN_ERR "%s: failed to get io timing\n",
+                                       __func__);
+                                goto out;
+                        }
+                }
+
+                if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
+                        printk(KERN_ERR "%s: no IO support registered\n",
+                               __func__);
+                        ret = -EINVAL;
+                        goto out;
+                }
+
+                if (!cpu_cur.info->need_pll)
+                        cpu_cur.lock_pll = 1;
+
+                s3c_cpufreq_update_loctkime();
+
+                s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
+                                     &cpu_cur.info->max);
+
+                if (cpu_cur.info->calc_freqtable)
+                        s3c_cpufreq_build_freq();
+
+                ret = cpufreq_register_driver(&s3c24xx_driver);
+        }
+
+ out:
+        return ret;
+}
+
+late_initcall(s3c_cpufreq_initcall);
+
+/**
+ * s3c_plltab_register - register CPU PLL table.
+ * @plls: The list of PLL entries.
+ * @plls_no: The size of the PLL entries @plls.
+ *
+ * Register the given set of PLLs with the system.
+ */
+int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
+                               unsigned int plls_no)
+{
+        struct cpufreq_frequency_table *vals;
+        unsigned int size;
+
+        size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
+
+        vals = kmalloc(size, GFP_KERNEL);
+        if (vals) {
+                memcpy(vals, plls, size);
+                pll_reg = vals;
+
+                /* write a terminating entry, we don't store it in the
+                 * table that is stored in the kernel */
+                vals += plls_no;
+                vals->frequency = CPUFREQ_TABLE_END;
+
+                printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
+        } else
+                printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
+
+        return vals ? 0 : -ENOMEM;
+}
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 4803338cf56e..25d085adc93c 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index 38472ac920ff..d2408ba372cb 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 5f0a0c8ef84f..0b86e74d104f 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 2d94228d2866..05536254a3f8 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
new file mode 100644
index 000000000000..aab64909e9a3
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -0,0 +1,1468 @@
+/*
+ * Copyright 2003-2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 DMA core
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifdef CONFIG_S3C2410_DMA_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/syscore_ops.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
+#include <mach/map.h>
+
+#include <plat/dma-s3c24xx.h>
+#include <plat/regs-dma.h>
+
+/* io map for dma */
+static void __iomem *dma_base;
+static struct kmem_cache *dma_kmem;
+
+static int dma_channels;
+
+static struct s3c24xx_dma_selection dma_sel;
+
+
+/* debugging functions */
+
+#define BUF_MAGIC (0xcafebabe)
+
+#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
+
+#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
+
+#if 1
+#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
+#else
+static inline void
+dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
+{
+        pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
+        writel(val, dma_regaddr(chan, reg));
+}
+#endif
+
+#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
+
+/* captured register state for debug */
+
+struct s3c2410_dma_regstate {
+        unsigned long         dcsrc;
+        unsigned long         disrc;
+        unsigned long         dstat;
+        unsigned long         dcon;
+        unsigned long         dmsktrig;
+};
+
+#ifdef CONFIG_S3C2410_DMA_DEBUG
+
+/* dmadbg_showregs
+ *
+ * simple debug routine to print the current state of the dma registers
+*/
+
+static void
+dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
+{
+        regs->dcsrc    = dma_rdreg(chan, S3C2410_DMA_DCSRC);
+        regs->disrc    = dma_rdreg(chan, S3C2410_DMA_DISRC);
+        regs->dstat    = dma_rdreg(chan, S3C2410_DMA_DSTAT);
+        regs->dcon     = dma_rdreg(chan, S3C2410_DMA_DCON);
+        regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
+}
+
+static void
+dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
+                 struct s3c2410_dma_regstate *regs)
+{
+        printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
+               chan->number, fname, line,
+               regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
+               regs->dcon);
+}
+
+static void
+dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
+{
+        struct s3c2410_dma_regstate state;
+
+        dmadbg_capture(chan, &state);
+
+        printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
+               chan->number, fname, line, chan->load_state,
+               chan->curr, chan->next, chan->end);
+
+        dmadbg_dumpregs(fname, line, chan, &state);
+}
+
+static void
+dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
+{
+        struct s3c2410_dma_regstate state;
+
+        dmadbg_capture(chan, &state);
+        dmadbg_dumpregs(fname, line, chan, &state);
+}
+
+#define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
+#define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
+#else
+#define dbg_showregs(chan) do { } while(0)
+#define dbg_showchan(chan) do { } while(0)
+#endif /* CONFIG_S3C2410_DMA_DEBUG */
+
+/* s3c2410_dma_stats_timeout
+ *
+ * Update DMA stats from timeout info
+*/
+
+static void
+s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
+{
+        if (stats == NULL)
+                return;
+
+        if (val > stats->timeout_longest)
+                stats->timeout_longest = val;
+        if (val < stats->timeout_shortest)
+                stats->timeout_shortest = val;
+
+        stats->timeout_avg += val;
+}
+
+/* s3c2410_dma_waitforload
+ *
+ * wait for the DMA engine to load a buffer, and update the state accordingly
+*/
+
+static int
+s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
+{
+        int timeout = chan->load_timeout;
+        int took;
+
+        if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
+                printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
+                return 0;
+        }
+
+        if (chan->stats != NULL)
+                chan->stats->loads++;
+
+        while (--timeout > 0) {
+                if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
+                        took = chan->load_timeout - timeout;
+
+                        s3c2410_dma_stats_timeout(chan->stats, took);
+
+                        switch (chan->load_state) {
+                        case S3C2410_DMALOAD_1LOADED:
+                                chan->load_state = S3C2410_DMALOAD_1RUNNING;
+                                break;
+
+                        default:
+                                printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
+                        }
+
+                        return 1;
+                }
+        }
+
+        if (chan->stats != NULL) {
+                chan->stats->timeout_failed++;
+        }
+
+        return 0;
+}
+
+/* s3c2410_dma_loadbuffer
+ *
+ * load a buffer, and update the channel state
+*/
+
+static inline int
+s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
+                       struct s3c2410_dma_buf *buf)
+{
+        unsigned long reload;
+
+        if (buf == NULL) {
+                dmawarn("buffer is NULL\n");
+                return -EINVAL;
+        }
+
+        pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
+                 buf, (unsigned long)buf->data, buf->size);
+
+        /* check the state of the channel before we do anything */
+
+        if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
+                dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
+        }
+
+        if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
+                dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
+        }
+
+        /* it would seem sensible if we are the last buffer to not bother
+         * with the auto-reload bit, so that the DMA engine will not try
+         * and load another transfer after this one has finished...
+         */
+        if (chan->load_state == S3C2410_DMALOAD_NONE) {
+                pr_debug("load_state is none, checking for noreload (next=%p)\n",
+                         buf->next);
+                reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
+        } else {
+                //pr_debug("load_state is %d => autoreload\n", chan->load_state);
+                reload = S3C2410_DCON_AUTORELOAD;
+        }
+
+        if ((buf->data & 0xf0000000) != 0x30000000) {
+                dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
+        }
+
+        writel(buf->data, chan->addr_reg);
+
+        dma_wrreg(chan, S3C2410_DMA_DCON,
+                  chan->dcon | reload | (buf->size/chan->xfer_unit));
+
+        chan->next = buf->next;
+
+        /* update the state of the channel */
+
+        switch (chan->load_state) {
+        case S3C2410_DMALOAD_NONE:
+                chan->load_state = S3C2410_DMALOAD_1LOADED;
+                break;
+
+        case S3C2410_DMALOAD_1RUNNING:
+                chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
+                break;
+
+        default:
+                dmawarn("dmaload: unknown state %d in loadbuffer\n",
+                        chan->load_state);
+                break;
+        }
+
+        return 0;
+}
+
+/* s3c2410_dma_call_op
+ *
+ * small routine to call the op routine with the given op if it has been
+ * registered
+*/
+
+static void
+s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
+{
+        if (chan->op_fn != NULL) {
+                (chan->op_fn)(chan, op);
+        }
+}
+
+/* s3c2410_dma_buffdone
+ *
+ * small wrapper to check if callback routine needs to be called, and
+ * if so, call it
+*/
+
+static inline void
+s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
+                     enum s3c2410_dma_buffresult result)
+{
+#if 0
+        pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
+                 chan->callback_fn, buf, buf->id, buf->size, result);
+#endif
+
+        if (chan->callback_fn != NULL) {
+                (chan->callback_fn)(chan, buf->id, buf->size, result);
+        }
+}
+
+/* s3c2410_dma_start
+ *
+ * start a dma channel going
+*/
+
+static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
+{
+        unsigned long tmp;
+        unsigned long flags;
+
+        pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
+
+        local_irq_save(flags);
+
+        if (chan->state == S3C2410_DMA_RUNNING) {
+                pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
+                local_irq_restore(flags);
+                return 0;
+        }
+
+        chan->state = S3C2410_DMA_RUNNING;
+
+        /* check whether there is anything to load, and if not, see
+         * if we can find anything to load
+         */
+
+        if (chan->load_state == S3C2410_DMALOAD_NONE) {
+                if (chan->next == NULL) {
+                        printk(KERN_ERR "dma%d: channel has nothing loaded\n",
+                               chan->number);
+                        chan->state = S3C2410_DMA_IDLE;
+                        local_irq_restore(flags);
+                        return -EINVAL;
+                }
+
+                s3c2410_dma_loadbuffer(chan, chan->next);
+        }
+
+        dbg_showchan(chan);
+
+        /* enable the channel */
+
+        if (!chan->irq_enabled) {
+                enable_irq(chan->irq);
+                chan->irq_enabled = 1;
+        }
+
+        /* start the channel going */
+
+        tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
+        tmp &= ~S3C2410_DMASKTRIG_STOP;
+        tmp |= S3C2410_DMASKTRIG_ON;
+        dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
+
+        pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
+
+#if 0
+        /* the dma buffer loads should take care of clearing the AUTO
+         * reloading feature */
+        tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
+        tmp &= ~S3C2410_DCON_NORELOAD;
+        dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
+#endif
+
+        s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
+
+        dbg_showchan(chan);
+
+        /* if we've only loaded one buffer onto the channel, then chec
+         * to see if we have another, and if so, try and load it so when
+         * the first buffer is finished, the new one will be loaded onto
+         * the channel */
+
+        if (chan->next != NULL) {
+                if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
+
+                        if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+                                pr_debug("%s: buff not yet loaded, no more todo\n",
+                                         __func__);
+                        } else {
+                                chan->load_state = S3C2410_DMALOAD_1RUNNING;
+                                s3c2410_dma_loadbuffer(chan, chan->next);
+                        }
+
+                } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
+                        s3c2410_dma_loadbuffer(chan, chan->next);
+                }
+        }
+
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+/* s3c2410_dma_canload
+ *
+ * work out if we can queue another buffer into the DMA engine
+*/
+
+static int
+s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
+{
+        if (chan->load_state == S3C2410_DMALOAD_NONE ||
+            chan->load_state == S3C2410_DMALOAD_1RUNNING)
+                return 1;
+
+        return 0;
+}
+
+/* s3c2410_dma_enqueue
+ *
+ * queue an given buffer for dma transfer.
+ *
+ * id         the device driver's id information for this buffer
+ * data       the physical address of the buffer data
+ * size       the size of the buffer in bytes
+ *
+ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
+ * is checked, and if set, the channel is started. If this flag isn't set,
+ * then an error will be returned.
+ *
+ * It is possible to queue more than one DMA buffer onto a channel at
+ * once, and the code will deal with the re-loading of the next buffer
+ * when necessary.
+*/
+
+int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
+                        dma_addr_t data, int size)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        struct s3c2410_dma_buf *buf;
+        unsigned long flags;
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        pr_debug("%s: id=%p, data=%08x, size=%d\n",
+                 __func__, id, (unsigned int)data, size);
+
+        buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
+        if (buf == NULL) {
+                pr_debug("%s: out of memory (%ld alloc)\n",
+                         __func__, (long)sizeof(*buf));
+                return -ENOMEM;
+        }
+
+        //pr_debug("%s: new buffer %p\n", __func__, buf);
+        //dbg_showchan(chan);
+
+        buf->next  = NULL;
+        buf->data  = buf->ptr = data;
+        buf->size  = size;
+        buf->id    = id;
+        buf->magic = BUF_MAGIC;
+
+        local_irq_save(flags);
+
+        if (chan->curr == NULL) {
+                /* we've got nothing loaded... */
+                pr_debug("%s: buffer %p queued onto empty channel\n",
+                         __func__, buf);
+
+                chan->curr = buf;
+                chan->end  = buf;
+                chan->next = NULL;
+        } else {
+                pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
+                         chan->number, __func__, buf);
+
+                if (chan->end == NULL) {
+                        pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
+                                 chan->number, __func__, chan);
+                } else {
+                        chan->end->next = buf;
+                        chan->end = buf;
+                }
+        }
+
+        /* if necessary, update the next buffer field */
+        if (chan->next == NULL)
+                chan->next = buf;
+
+        /* check to see if we can load a buffer */
+        if (chan->state == S3C2410_DMA_RUNNING) {
+                if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
+                        if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+                                printk(KERN_ERR "dma%d: loadbuffer:"
+                                       "timeout loading buffer\n",
+                                       chan->number);
+                                dbg_showchan(chan);
+                                local_irq_restore(flags);
+                                return -EINVAL;
+                        }
+                }
+
+                while (s3c2410_dma_canload(chan) && chan->next != NULL) {
+                        s3c2410_dma_loadbuffer(chan, chan->next);
+                }
+        } else if (chan->state == S3C2410_DMA_IDLE) {
+                if (chan->flags & S3C2410_DMAF_AUTOSTART) {
+                        s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
+                                         S3C2410_DMAOP_START);
+                }
+        }
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_enqueue);
+
+static inline void
+s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
+{
+        int magicok = (buf->magic == BUF_MAGIC);
+
+        buf->magic = -1;
+
+        if (magicok) {
+                kmem_cache_free(dma_kmem, buf);
+        } else {
+                printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
+        }
+}
+
+/* s3c2410_dma_lastxfer
+ *
+ * called when the system is out of buffers, to ensure that the channel
+ * is prepared for shutdown.
+*/
+
+static inline void
+s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
+{
+#if 0
+        pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
+                 chan->number, chan->load_state);
+#endif
+
+        switch (chan->load_state) {
+        case S3C2410_DMALOAD_NONE:
+                break;
+
+        case S3C2410_DMALOAD_1LOADED:
+                if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+                                /* flag error? */
+                        printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
+                               chan->number, __func__);
+                        return;
+                }
+                break;
+
+        case S3C2410_DMALOAD_1LOADED_1RUNNING:
+                /* I believe in this case we do not have anything to do
+                 * until the next buffer comes along, and we turn off the
+                 * reload */
+                return;
+
+        default:
+                pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
+                         chan->number, chan->load_state);
+                return;
+
+        }
+
+        /* hopefully this'll shut the damned thing up after the transfer... */
+        dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
+}
+
+
+#define dmadbg2(x...)
+
+static irqreturn_t
+s3c2410_dma_irq(int irq, void *devpw)
+{
+        struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
+        struct s3c2410_dma_buf  *buf;
+
+        buf = chan->curr;
+
+        dbg_showchan(chan);
+
+        /* modify the channel state */
+
+        switch (chan->load_state) {
+        case S3C2410_DMALOAD_1RUNNING:
+                /* TODO - if we are running only one buffer, we probably
+                 * want to reload here, and then worry about the buffer
+                 * callback */
+
+                chan->load_state = S3C2410_DMALOAD_NONE;
+                break;
+
+        case S3C2410_DMALOAD_1LOADED:
+                /* iirc, we should go back to NONE loaded here, we
+                 * had a buffer, and it was never verified as being
+                 * loaded.
+                 */
+
+                chan->load_state = S3C2410_DMALOAD_NONE;
+                break;
+
+        case S3C2410_DMALOAD_1LOADED_1RUNNING:
+                /* we'll worry about checking to see if another buffer is
+                 * ready after we've called back the owner. This should
+                 * ensure we do not wait around too long for the DMA
+                 * engine to start the next transfer
+                 */
+
+                chan->load_state = S3C2410_DMALOAD_1LOADED;
+                break;
+
+        case S3C2410_DMALOAD_NONE:
+                printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
+                       chan->number);
+                break;
+
+        default:
+                printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
+                       chan->number, chan->load_state);
+                break;
+        }
+
+        if (buf != NULL) {
+                /* update the chain to make sure that if we load any more
+                 * buffers when we call the callback function, things should
+                 * work properly */
+
+                chan->curr = buf->next;
+                buf->next  = NULL;
+
+                if (buf->magic != BUF_MAGIC) {
+                        printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
+                               chan->number, __func__, buf);
+                        return IRQ_HANDLED;
+                }
+
+                s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
+
+                /* free resouces */
+                s3c2410_dma_freebuf(buf);
+        } else {
+        }
+
+        /* only reload if the channel is still running... our buffer done
+         * routine may have altered the state by requesting the dma channel
+         * to stop or shutdown... */
+
+        /* todo: check that when the channel is shut-down from inside this
+         * function, we cope with unsetting reload, etc */
+
+        if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
+                unsigned long flags;
+
+                switch (chan->load_state) {
+                case S3C2410_DMALOAD_1RUNNING:
+                        /* don't need to do anything for this state */
+                        break;
+
+                case S3C2410_DMALOAD_NONE:
+                        /* can load buffer immediately */
+                        break;
+
+                case S3C2410_DMALOAD_1LOADED:
+                        if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+                                /* flag error? */
+                                printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
+                                       chan->number, __func__);
+                                return IRQ_HANDLED;
+                        }
+
+                        break;
+
+                case S3C2410_DMALOAD_1LOADED_1RUNNING:
+                        goto no_load;
+
+                default:
+                        printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
+                               chan->number, chan->load_state);
+                        return IRQ_HANDLED;
+                }
+
+                local_irq_save(flags);
+                s3c2410_dma_loadbuffer(chan, chan->next);
+                local_irq_restore(flags);
+        } else {
+                s3c2410_dma_lastxfer(chan);
+
+                /* see if we can stop this channel.. */
+                if (chan->load_state == S3C2410_DMALOAD_NONE) {
+                        pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
+                                 chan->number, jiffies);
+                        s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
+                                         S3C2410_DMAOP_STOP);
+                }
+        }
+
+ no_load:
+        return IRQ_HANDLED;
+}
+
+static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
+
+/* s3c2410_request_dma
+ *
+ * get control of an dma channel
+*/
+
+int s3c2410_dma_request(enum dma_ch channel,
+                        struct s3c2410_dma_client *client,
+                        void *dev)
+{
+        struct s3c2410_dma_chan *chan;
+        unsigned long flags;
+        int err;
+
+        pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
+                 channel, client->name, dev);
+
+        local_irq_save(flags);
+
+        chan = s3c2410_dma_map_channel(channel);
+        if (chan == NULL) {
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+
+        dbg_showchan(chan);
+
+        chan->client = client;
+        chan->in_use = 1;
+
+        if (!chan->irq_claimed) {
+                pr_debug("dma%d: %s : requesting irq %d\n",
+                         channel, __func__, chan->irq);
+
+                chan->irq_claimed = 1;
+                local_irq_restore(flags);
+
+                err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
+                                  client->name, (void *)chan);
+
+                local_irq_save(flags);
+
+                if (err) {
+                        chan->in_use = 0;
+                        chan->irq_claimed = 0;
+                        local_irq_restore(flags);
+
+                        printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
+                               client->name, chan->irq, chan->number);
+                        return err;
+                }
+
+                chan->irq_enabled = 1;
+        }
+
+        local_irq_restore(flags);
+
+        /* need to setup */
+
+        pr_debug("%s: channel initialised, %p\n", __func__, chan);
+
+        return chan->number | DMACH_LOW_LEVEL;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_request);
+
+/* s3c2410_dma_free
+ *
+ * release the given channel back to the system, will stop and flush
+ * any outstanding transfers, and ensure the channel is ready for the
+ * next claimant.
+ *
+ * Note, although a warning is currently printed if the freeing client
+ * info is not the same as the registrant's client info, the free is still
+ * allowed to go through.
+*/
+
+int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned long flags;
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        local_irq_save(flags);
+
+        if (chan->client != client) {
+                printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
+                       channel, chan->client, client);
+        }
+
+        /* sort out stopping and freeing the channel */
+
+        if (chan->state != S3C2410_DMA_IDLE) {
+                pr_debug("%s: need to stop dma channel %p\n",
+                       __func__, chan);
+
+                /* possibly flush the channel */
+                s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
+        }
+
+        chan->client = NULL;
+        chan->in_use = 0;
+
+        if (chan->irq_claimed)
+                free_irq(chan->irq, (void *)chan);
+
+        chan->irq_claimed = 0;
+
+        if (!(channel & DMACH_LOW_LEVEL))
+                s3c_dma_chan_map[channel] = NULL;
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_free);
+
+static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
+{
+        unsigned long flags;
+        unsigned long tmp;
+
+        pr_debug("%s:\n", __func__);
+
+        dbg_showchan(chan);
+
+        local_irq_save(flags);
+
+        s3c2410_dma_call_op(chan,  S3C2410_DMAOP_STOP);
+
+        tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
+        tmp |= S3C2410_DMASKTRIG_STOP;
+        //tmp &= ~S3C2410_DMASKTRIG_ON;
+        dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
+
+#if 0
+        /* should also clear interrupts, according to WinCE BSP */
+        tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
+        tmp |= S3C2410_DCON_NORELOAD;
+        dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
+#endif
+
+        /* should stop do this, or should we wait for flush? */
+        chan->state      = S3C2410_DMA_IDLE;
+        chan->load_state = S3C2410_DMALOAD_NONE;
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
+{
+        unsigned long tmp;
+        unsigned int timeout = 0x10000;
+
+        while (timeout-- > 0) {
+                tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
+
+                if (!(tmp & S3C2410_DMASKTRIG_ON))
+                        return;
+        }
+
+        pr_debug("dma%d: failed to stop?\n", chan->number);
+}
+
+
+/* s3c2410_dma_flush
+ *
+ * stop the channel, and remove all current and pending transfers
+*/
+
+static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
+{
+        struct s3c2410_dma_buf *buf, *next;
+        unsigned long flags;
+
+        pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
+
+        dbg_showchan(chan);
+
+        local_irq_save(flags);
+
+        if (chan->state != S3C2410_DMA_IDLE) {
+                pr_debug("%s: stopping channel...\n", __func__ );
+                s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
+        }
+
+        buf = chan->curr;
+        if (buf == NULL)
+                buf = chan->next;
+
+        chan->curr = chan->next = chan->end = NULL;
+
+        if (buf != NULL) {
+                for ( ; buf != NULL; buf = next) {
+                        next = buf->next;
+
+                        pr_debug("%s: free buffer %p, next %p\n",
+                               __func__, buf, buf->next);
+
+                        s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
+                        s3c2410_dma_freebuf(buf);
+                }
+        }
+
+        dbg_showregs(chan);
+
+        s3c2410_dma_waitforstop(chan);
+
+#if 0
+        /* should also clear interrupts, according to WinCE BSP */
+        {
+                unsigned long tmp;
+
+                tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
+                tmp |= S3C2410_DCON_NORELOAD;
+                dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
+        }
+#endif
+
+        dbg_showregs(chan);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        dbg_showchan(chan);
+
+        /* if we've only loaded one buffer onto the channel, then chec
+         * to see if we have another, and if so, try and load it so when
+         * the first buffer is finished, the new one will be loaded onto
+         * the channel */
+
+        if (chan->next != NULL) {
+                if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
+
+                        if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+                                pr_debug("%s: buff not yet loaded, no more todo\n",
+                                         __func__);
+                        } else {
+                                chan->load_state = S3C2410_DMALOAD_1RUNNING;
+                                s3c2410_dma_loadbuffer(chan, chan->next);
+                        }
+
+                } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
+                        s3c2410_dma_loadbuffer(chan, chan->next);
+                }
+        }
+
+
+        local_irq_restore(flags);
+
+        return 0;
+
+}
+
+int
+s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        switch (op) {
+        case S3C2410_DMAOP_START:
+                return s3c2410_dma_start(chan);
+
+        case S3C2410_DMAOP_STOP:
+                return s3c2410_dma_dostop(chan);
+
+        case S3C2410_DMAOP_PAUSE:
+        case S3C2410_DMAOP_RESUME:
+                return -ENOENT;
+
+        case S3C2410_DMAOP_FLUSH:
+                return s3c2410_dma_flush(chan);
+
+        case S3C2410_DMAOP_STARTED:
+                return s3c2410_dma_started(chan);
+
+        case S3C2410_DMAOP_TIMEOUT:
+                return 0;
+
+        }
+
+        return -ENOENT;      /* unknown, don't bother */
+}
+
+EXPORT_SYMBOL(s3c2410_dma_ctrl);
+
+/* DMA configuration for each channel
+ *
+ * DISRCC -> source of the DMA (AHB,APB)
+ * DISRC  -> source address of the DMA
+ * DIDSTC -> destination of the DMA (AHB,APD)
+ * DIDST  -> destination address of the DMA
+*/
+
+/* s3c2410_dma_config
+ *
+ * xfersize:     size of unit in bytes (1,2,4)
+*/
+
+int s3c2410_dma_config(enum dma_ch channel,
+                       int xferunit)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned int dcon;
+
+        pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        dcon = chan->dcon & dma_sel.dcon_mask;
+        pr_debug("%s: dcon is %08x\n", __func__, dcon);
+
+        switch (chan->req_ch) {
+        case DMACH_I2S_IN:
+        case DMACH_I2S_OUT:
+        case DMACH_PCM_IN:
+        case DMACH_PCM_OUT:
+        case DMACH_MIC_IN:
+        default:
+                dcon |= S3C2410_DCON_HANDSHAKE;
+                dcon |= S3C2410_DCON_SYNC_PCLK;
+                break;
+
+        case DMACH_SDI:
+                /* note, ensure if need HANDSHAKE or not */
+                dcon |= S3C2410_DCON_SYNC_PCLK;
+                break;
+
+        case DMACH_XD0:
+        case DMACH_XD1:
+                dcon |= S3C2410_DCON_HANDSHAKE;
+                dcon |= S3C2410_DCON_SYNC_HCLK;
+                break;
+        }
+
+        switch (xferunit) {
+        case 1:
+                dcon |= S3C2410_DCON_BYTE;
+                break;
+
+        case 2:
+                dcon |= S3C2410_DCON_HALFWORD;
+                break;
+
+        case 4:
+                dcon |= S3C2410_DCON_WORD;
+                break;
+
+        default:
+                pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
+                return -EINVAL;
+        }
+
+        dcon |= S3C2410_DCON_HWTRIG;
+        dcon |= S3C2410_DCON_INTREQ;
+
+        pr_debug("%s: dcon now %08x\n", __func__, dcon);
+
+        chan->dcon = dcon;
+        chan->xfer_unit = xferunit;
+
+        return 0;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_config);
+
+
+/* s3c2410_dma_devconfig
+ *
+ * configure the dma source/destination hardware type and address
+ *
+ * source:    DMA_FROM_DEVICE: source is hardware
+ *            DMA_TO_DEVICE: source is memory
+ *
+ * devaddr:   physical address of the source
+*/
+
+int s3c2410_dma_devconfig(enum dma_ch channel,
+                          enum dma_data_direction source,
+                          unsigned long devaddr)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned int hwcfg;
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        pr_debug("%s: source=%d, devaddr=%08lx\n",
+                 __func__, (int)source, devaddr);
+
+        chan->source = source;
+        chan->dev_addr = devaddr;
+
+        switch (chan->req_ch) {
+        case DMACH_XD0:
+        case DMACH_XD1:
+                hwcfg = 0; /* AHB */
+                break;
+
+        default:
+                hwcfg = S3C2410_DISRCC_APB;
+        }
+
+        /* always assume our peripheral desintation is a fixed
+         * address in memory. */
+         hwcfg |= S3C2410_DISRCC_INC;
+
+        switch (source) {
+        case DMA_FROM_DEVICE:
+                /* source is hardware */
+                pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
+                         __func__, devaddr, hwcfg);
+                dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
+                dma_wrreg(chan, S3C2410_DMA_DISRC,  devaddr);
+                dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
+
+                chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
+                break;
+
+        case DMA_TO_DEVICE:
+                /* source is memory */
+                pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
+                         __func__, devaddr, hwcfg);
+                dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
+                dma_wrreg(chan, S3C2410_DMA_DIDST,  devaddr);
+                dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
+
+                chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
+                break;
+
+        default:
+                printk(KERN_ERR "dma%d: invalid source type (%d)\n",
+                       channel, source);
+
+                return -EINVAL;
+        }
+
+        if (dma_sel.direction != NULL)
+                (dma_sel.direction)(chan, chan->map, source);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_devconfig);
+
+/* s3c2410_dma_getposition
+ *
+ * returns the current transfer points for the dma source and destination
+*/
+
+int s3c2410_dma_getposition(enum dma_ch channel, dma_addr_t *src, dma_addr_t *dst)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        if (src != NULL)
+                *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
+
+        if (dst != NULL)
+                *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_getposition);
+
+/* system core operations */
+
+#ifdef CONFIG_PM
+
+static void s3c2410_dma_suspend_chan(struct s3c2410_dma_chan *cp)
+{
+        printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
+
+        if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
+                /* the dma channel is still working, which is probably
+                 * a bad thing to do over suspend/resume. We stop the
+                 * channel and assume that the client is either going to
+                 * retry after resume, or that it is broken.
+                 */
+
+                printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
+                       cp->number);
+
+                s3c2410_dma_dostop(cp);
+        }
+}
+
+static int s3c2410_dma_suspend(void)
+{
+        struct s3c2410_dma_chan *cp = s3c2410_chans;
+        int channel;
+
+        for (channel = 0; channel < dma_channels; cp++, channel++)
+                s3c2410_dma_suspend_chan(cp);
+
+        return 0;
+}
+
+static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
+{
+        unsigned int no = cp->number | DMACH_LOW_LEVEL;
+
+        /* restore channel's hardware configuration */
+
+        if (!cp->in_use)
+                return;
+
+        printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
+
+        s3c2410_dma_config(no, cp->xfer_unit);
+        s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
+
+        /* re-select the dma source for this channel */
+
+        if (cp->map != NULL)
+                dma_sel.select(cp, cp->map);
+}
+
+static void s3c2410_dma_resume(void)
+{
+        struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
+        int channel;
+
+        for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
+                s3c2410_dma_resume_chan(cp);
+}
+
+#else
+#define s3c2410_dma_suspend NULL
+#define s3c2410_dma_resume  NULL
+#endif /* CONFIG_PM */
+
+struct syscore_ops dma_syscore_ops = {
+        .suspend        = s3c2410_dma_suspend,
+        .resume         = s3c2410_dma_resume,
+};
+
+/* kmem cache implementation */
+
+static void s3c2410_dma_cache_ctor(void *p)
+{
+        memset(p, 0, sizeof(struct s3c2410_dma_buf));
+}
+
+/* initialisation code */
+
+static int __init s3c24xx_dma_syscore_init(void)
+{
+        register_syscore_ops(&dma_syscore_ops);
+
+        return 0;
+}
+
+late_initcall(s3c24xx_dma_syscore_init);
+
+int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
+                            unsigned int stride)
+{
+        struct s3c2410_dma_chan *cp;
+        int channel;
+        int ret;
+
+        printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
+
+        dma_channels = channels;
+
+        dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
+        if (dma_base == NULL) {
+                printk(KERN_ERR "dma failed to remap register block\n");
+                return -ENOMEM;
+        }
+
+        dma_kmem = kmem_cache_create("dma_desc",
+                                     sizeof(struct s3c2410_dma_buf), 0,
+                                     SLAB_HWCACHE_ALIGN,
+                                     s3c2410_dma_cache_ctor);
+
+        if (dma_kmem == NULL) {
+                printk(KERN_ERR "dma failed to make kmem cache\n");
+                ret = -ENOMEM;
+                goto err;
+        }
+
+        for (channel = 0; channel < channels;  channel++) {
+                cp = &s3c2410_chans[channel];
+
+                memset(cp, 0, sizeof(struct s3c2410_dma_chan));
+
+                /* dma channel irqs are in order.. */
+                cp->number = channel;
+                cp->irq    = channel + irq;
+                cp->regs   = dma_base + (channel * stride);
+
+                /* point current stats somewhere */
+                cp->stats  = &cp->stats_store;
+                cp->stats_store.timeout_shortest = LONG_MAX;
+
+                /* basic channel configuration */
+
+                cp->load_timeout = 1<<18;
+
+                printk("DMA channel %d at %p, irq %d\n",
+                       cp->number, cp->regs, cp->irq);
+        }
+
+        return 0;
+
+ err:
+        kmem_cache_destroy(dma_kmem);
+        iounmap(dma_base);
+        dma_base = NULL;
+        return ret;
+}
+
+int __init s3c2410_dma_init(void)
+{
+        return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
+}
+
+static inline int is_channel_valid(unsigned int channel)
+{
+        return (channel & DMA_CH_VALID);
+}
+
+static struct s3c24xx_dma_order *dma_order;
+
+
+/* s3c2410_dma_map_channel()
+ *
+ * turn the virtual channel number into a real, and un-used hardware
+ * channel.
+ *
+ * first, try the dma ordering given to us by either the relevant
+ * dma code, or the board. Then just find the first usable free
+ * channel
+*/
+
+static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
+{
+        struct s3c24xx_dma_order_ch *ord = NULL;
+        struct s3c24xx_dma_map *ch_map;
+        struct s3c2410_dma_chan *dmach;
+        int ch;
+
+        if (dma_sel.map == NULL || channel > dma_sel.map_size)
+                return NULL;
+
+        ch_map = dma_sel.map + channel;
+
+        /* first, try the board mapping */
+
+        if (dma_order) {
+                ord = &dma_order->channels[channel];
+
+                for (ch = 0; ch < dma_channels; ch++) {
+                        int tmp;
+                        if (!is_channel_valid(ord->list[ch]))
+                                continue;
+
+                        tmp = ord->list[ch] & ~DMA_CH_VALID;
+                        if (s3c2410_chans[tmp].in_use == 0) {
+                                ch = tmp;
+                                goto found;
+                        }
+                }
+
+                if (ord->flags & DMA_CH_NEVER)
+                        return NULL;
+        }
+
+        /* second, search the channel map for first free */
+
+        for (ch = 0; ch < dma_channels; ch++) {
+                if (!is_channel_valid(ch_map->channels[ch]))
+                        continue;
+
+                if (s3c2410_chans[ch].in_use == 0) {
+                        printk("mapped channel %d to %d\n", channel, ch);
+                        break;
+                }
+        }
+
+        if (ch >= dma_channels)
+                return NULL;
+
+        /* update our channel mapping */
+
+ found:
+        dmach = &s3c2410_chans[ch];
+        dmach->map = ch_map;
+        dmach->req_ch = channel;
+        s3c_dma_chan_map[channel] = dmach;
+
+        /* select the channel */
+
+        (dma_sel.select)(dmach, ch_map);
+
+        return dmach;
+}
+
+static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
+{
+        return 0;
+}
+
+int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
+{
+        struct s3c24xx_dma_map *nmap;
+        size_t map_sz = sizeof(*nmap) * sel->map_size;
+        int ptr;
+
+        nmap = kmemdup(sel->map, map_sz, GFP_KERNEL);
+        if (nmap == NULL)
+                return -ENOMEM;
+
+        memcpy(&dma_sel, sel, sizeof(*sel));
+
+        dma_sel.map = nmap;
+
+        for (ptr = 0; ptr < sel->map_size; ptr++)
+                s3c24xx_dma_check_entry(nmap+ptr, ptr);
+
+        return 0;
+}
+
+int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
+{
+        struct s3c24xx_dma_order *nord = dma_order;
+
+        if (nord == NULL)
+                nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
+
+        if (nord == NULL) {
+                printk(KERN_ERR "no memory to store dma channel order\n");
+                return -ENOMEM;
+        }
+
+        dma_order = nord;
+        memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
+        return 0;
+}
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/gta02.h
index 217393482153..9430a71e9184 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gta02.h
+++ b/arch/arm/mach-s3c24xx/gta02.h
@@ -1,5 +1,13 @@
-#ifndef _GTA02_H
-#define _GTA02_H
+/*
+ * GTA02 header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_S3C24XX_GTA02_H
+#define __MACH_S3C24XX_GTA02_H __FILE__
 
 #include <mach/regs-gpio.h>
 
@@ -12,4 +20,4 @@
 
 #define GTA02_IRQ_PCF50633      IRQ_EINT9
 
-#endif /* _GTA02_H */
+#endif /* __MACH_S3C24XX_GTA02_H */
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index 3f40c61b6e02..5b98bfd1df43 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -19,10 +19,10 @@
 #include <linux/gpio.h>
 #include <linux/rfkill.h>
 
-#include <mach/regs-gpio.h>
 #include <mach/hardware.h>
-#include <mach/h1940-latch.h>
-#include <mach/h1940.h>
+#include <mach/regs-gpio.h>
+
+#include "h1940.h"
 
 #define DRV_NAME "h1940-bt"
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h b/arch/arm/mach-s3c24xx/h1940.h
index fc897d3a056c..2950cc466840 100644
--- a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
+++ b/arch/arm/mach-s3c24xx/h1940.h
@@ -1,20 +1,30 @@
-/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+/*
+ * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
  *
  * Copyright (c) 2005 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
- *  iPAQ H1940 series - latch definitions
+ * iPAQ H1940 series definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM_ARCH_H1940_LATCH_H
-#define __ASM_ARCH_H1940_LATCH_H
+#ifndef __MACH_S3C24XX_H1940_H
+#define __MACH_S3C24XX_H1940_H __FILE__
 
-#include <asm/gpio.h>
+#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
+#define H1940_SUSPEND_RESUMEAT          (0x30081000)
+#define H1940_SUSPEND_CHECK             (0x30080000)
+
+extern void h1940_pm_return(void);
+extern int h1940_led_blink_set(unsigned gpio, int state,
+                               unsigned long *delay_on,
+                               unsigned long *delay_off);
+
+#include <linux/gpio.h>
 
 #define H1940_LATCH_GPIO(x)             (S3C_GPIO_END + (x))
 
@@ -40,4 +50,4 @@
 #define H1940_LATCH_LED_GREEN           H1940_LATCH_GPIO(14)
 #define H1940_LATCH_LED_FLASH           H1940_LATCH_GPIO(15)
 
-#endif /* __ASM_ARCH_H1940_LATCH_H */
+#endif /* __MACH_S3C24XX_H1940_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
deleted file mode 100644
index 1b614d5a81f3..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_ANUBISCPLD_H
-#define __ASM_ARCH_ANUBISCPLD_H
-
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-
-#define ANUBIS_CTRL1_NANDSEL            (0x3)
-
-/* IDREG - revision */
-
-#define ANUBIS_IDREG_REVMASK            (0x7)
-
-#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
deleted file mode 100644
index a2a328134e34..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- *  ANUBIS - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_ANUBISIRQ_H
-#define __ASM_ARCH_ANUBISIRQ_H
-
-#define IRQ_IDE0       IRQ_EINT2
-#define IRQ_IDE1       IRQ_EINT3
-#define IRQ_ASIX       IRQ_EINT1
-
-#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
deleted file mode 100644
index c9deb3a5b2c3..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-#ifndef __ASM_ARCH_ANUBISMAP_H
-#define __ASM_ARCH_ANUBISMAP_H
-
-/* start peripherals off after the S3C2410 */
-
-#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x01800000))
-
-#define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01800000 */
-#define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
-
-#define ANUBIS_VA_IDREG     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
-#define ANUBIS_PA_IDREG     (ANUBIS_PA_CPLD + (3<<23))
-
-#define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
-#define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
-#define ANUBIS_IDESEC       ANUBIS_IOADDR(0x01200000)
-#define ANUBIS_IDESECAUX    ANUBIS_IOADDR(0x01300000)
-
-#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
deleted file mode 100644
index bee2a7a932a0..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * BAST - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_BASTCPLD_H
-#define __ASM_ARCH_BASTCPLD_H
-
-/* CTRL1 - Audio LR routing */
-
-#define BAST_CPLD_CTRL1_LRCOFF      (0x00)
-#define BAST_CPLD_CTRL1_LRCADC      (0x01)
-#define BAST_CPLD_CTRL1_LRCDAC      (0x02)
-#define BAST_CPLD_CTRL1_LRCARM      (0x03)
-#define BAST_CPLD_CTRL1_LRMASK      (0x03)
-
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-
-#define BAST_CPLD_CTRL2_WNAND       (0x04)
-#define BAST_CPLD_CTLR2_IDERST      (0x08)
-
-/* CTRL3 - rom write control, CPLD identity */
-
-#define BAST_CPLD_CTRL3_IDMASK      (0x0e)
-#define BAST_CPLD_CTRL3_ROMWEN      (0x01)
-
-/* CTRL4 - 8bit LCD interface control/status */
-
-#define BAST_CPLD_CTRL4_LLAT        (0x01)
-#define BAST_CPLD_CTRL4_LCDRW       (0x02)
-#define BAST_CPLD_CTRL4_LCDCMD      (0x04)
-#define BAST_CPLD_CTRL4_LCDE2       (0x01)
-
-/* CTRL5 - DMA routing */
-
-#define BAST_CPLD_DMA0_PRIIDE      (0<<0)
-#define BAST_CPLD_DMA0_SECIDE      (1<<0)
-#define BAST_CPLD_DMA0_ISA15       (2<<0)
-#define BAST_CPLD_DMA0_ISA36       (3<<0)
-
-#define BAST_CPLD_DMA1_PRIIDE      (0<<2)
-#define BAST_CPLD_DMA1_SECIDE      (1<<2)
-#define BAST_CPLD_DMA1_ISA15       (2<<2)
-#define BAST_CPLD_DMA1_ISA36       (3<<2)
-
-#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
deleted file mode 100644
index cac428c42e7f..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_BASTIRQ_H
-#define __ASM_ARCH_BASTIRQ_H
-
-/* irq numbers to onboard peripherals */
-
-#define IRQ_USBOC      IRQ_EINT18
-#define IRQ_IDE0       IRQ_EINT16
-#define IRQ_IDE1       IRQ_EINT17
-#define IRQ_PCSERIAL1  IRQ_EINT15
-#define IRQ_PCSERIAL2  IRQ_EINT14
-#define IRQ_PCPARALLEL IRQ_EINT13
-#define IRQ_ASIX       IRQ_EINT11
-#define IRQ_DM9000     IRQ_EINT10
-#define IRQ_ISA        IRQ_EINT9
-#define IRQ_SMALERT    IRQ_EINT8
-
-#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
deleted file mode 100644
index eecea2a50f8f..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-map.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-map.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-
-#ifndef __ASM_ARCH_BASTMAP_H
-#define __ASM_ARCH_BASTMAP_H
-
-#define BAST_IOADDR(x)     (S3C2410_ADDR((x) + 0x01300000))
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define BAST_VA_CTRL1       BAST_IOADDR(0x00000000)      /* 0x01300000 */
-#define BAST_PA_CTRL1       (S3C2410_CS5 | 0x7800000)
-
-#define BAST_VA_CTRL2       BAST_IOADDR(0x00100000)      /* 0x01400000 */
-#define BAST_PA_CTRL2       (S3C2410_CS1 | 0x6000000)
-
-#define BAST_VA_CTRL3       BAST_IOADDR(0x00200000)      /* 0x01500000 */
-#define BAST_PA_CTRL3       (S3C2410_CS1 | 0x6800000)
-
-#define BAST_VA_CTRL4       BAST_IOADDR(0x00300000)      /* 0x01600000 */
-#define BAST_PA_CTRL4       (S3C2410_CS1 | 0x7000000)
-
-/* next, we have the PC104 ISA interrupt registers */
-
-#define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
-
-#define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
-
-#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
-
-#define BAST_PA_LCD_RCMD1     (0x8800000)
-#define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
-
-#define BAST_PA_LCD_WCMD1     (0x8000000)
-#define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
-
-#define BAST_PA_LCD_RDATA1    (0x9800000)
-#define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
-
-#define BAST_PA_LCD_WDATA1    (0x9000000)
-#define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
-
-#define BAST_PA_LCD_RCMD2     (0xA800000)
-#define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
-
-#define BAST_PA_LCD_WCMD2     (0xA000000)
-#define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
-
-#define BAST_PA_LCD_RDATA2    (0xB800000)
-#define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
-
-#define BAST_PA_LCD_WDATA2    (0xB000000)
-#define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
-
-
-/* 0xE0000000 contains the IO space that is split by speed and
- * whether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x00000000 to 0x01000000 16MB ISA IO space
- * 0x01000000 to 0x02000000 16MB ISA memory space
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
- * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-
-#define BAST_VA_MULTISPACE (0xE0000000)
-
-#define BAST_VA_ISAIO      (BAST_VA_MULTISPACE + 0x00000000)
-#define BAST_VA_ISAMEM     (BAST_VA_MULTISPACE + 0x01000000)
-#define BAST_VA_IDEPRI     (BAST_VA_MULTISPACE + 0x02000000)
-#define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
-#define BAST_VA_IDESEC     (BAST_VA_MULTISPACE + 0x02200000)
-#define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
-#define BAST_VA_ASIXNET    (BAST_VA_MULTISPACE + 0x02400000)
-#define BAST_VA_DM9000     (BAST_VA_MULTISPACE + 0x02500000)
-#define BAST_VA_SUPERIO    (BAST_VA_MULTISPACE + 0x02600000)
-
-#define BAST_VA_MULTISPACE (0xE0000000)
-
-#define BAST_VAM_CS2 (0x00000000)
-#define BAST_VAM_CS3 (0x04000000)
-#define BAST_VAM_CS4 (0x08000000)
-#define BAST_VAM_CS5 (0x0C000000)
-
-/* physical offset addresses for the peripherals */
-
-#define BAST_PA_ISAIO     (0x00000000)
-#define BAST_PA_ASIXNET   (0x01000000)
-#define BAST_PA_SUPERIO   (0x01800000)
-#define BAST_PA_IDEPRI    (0x02000000)
-#define BAST_PA_IDEPRIAUX (0x02800000)
-#define BAST_PA_IDESEC    (0x03000000)
-#define BAST_PA_IDESECAUX (0x03800000)
-#define BAST_PA_ISAMEM    (0x04000000)
-#define BAST_PA_DM9000    (0x05000000)
-
-/* some configurations for the peripherals */
-
-#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
-/*  */
-
-#define BAST_ASIXNET_CS  BAST_VAM_CS5
-#define BAST_IDE_CS      BAST_VAM_CS5
-#define BAST_DM9000_CS   BAST_VAM_CS4
-
-#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
deleted file mode 100644
index c53ad34c6579..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <plat/gpio-fns.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
deleted file mode 100644
index 3890a05948fb..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - GPIO bank numbering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_GPIONRS_H
-#define __MACH_GPIONRS_H
-
-#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
-
-#define S3C2410_GPIO_BANKG   (32*6)
-#define S3C2410_GPIO_BANKH   (32*7)
-
-/* GPIO sizes for various SoCs:
- *
- *             2442
- *   2410 2412 2440 2443 2416
- *   ---- ---- ---- ---- ----
- * A 23   22   25   16   25
- * B 11   11   11   11   9
- * C 16   15   16   16   16
- * D 16   16   16   16   16
- * E 16   16   16   16   16
- * F 8    8    8    8    8
- * G 16   16   16   16   8
- * H 11   11   9    15   15
- * J --   --   13   16   --
- * K --   --   --   --   16
- * L --   --   --   15   7
- * M --   --   --   2    2
- */
-
-/* GPIO bank sizes */
-#define S3C2410_GPIO_A_NR       (32)
-#define S3C2410_GPIO_B_NR       (32)
-#define S3C2410_GPIO_C_NR       (32)
-#define S3C2410_GPIO_D_NR       (32)
-#define S3C2410_GPIO_E_NR       (32)
-#define S3C2410_GPIO_F_NR       (32)
-#define S3C2410_GPIO_G_NR       (32)
-#define S3C2410_GPIO_H_NR       (32)
-#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
-#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
-#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
-#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
-
-#if CONFIG_S3C_GPIO_SPACE != 0
-#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
-#endif
-
-#define S3C2410_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
-
-#ifndef __ASSEMBLY__
-
-enum s3c_gpio_number {
-        S3C2410_GPIO_A_START = 0,
-        S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
-        S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
-        S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
-        S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
-        S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
-        S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
-        S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
-        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
-        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
-        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
-        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
-};
-
-#endif /* __ASSEMBLY__ */
-
-/* S3C2410 GPIO number definitions. */
-
-#define S3C2410_GPA(_nr)        (S3C2410_GPIO_A_START + (_nr))
-#define S3C2410_GPB(_nr)        (S3C2410_GPIO_B_START + (_nr))
-#define S3C2410_GPC(_nr)        (S3C2410_GPIO_C_START + (_nr))
-#define S3C2410_GPD(_nr)        (S3C2410_GPIO_D_START + (_nr))
-#define S3C2410_GPE(_nr)        (S3C2410_GPIO_E_START + (_nr))
-#define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
-#define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
-#define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
-#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
-#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
-#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
-#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
-
-#endif /* __MACH_GPIONRS_H */
-
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
deleted file mode 100644
index c410a078622c..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C2410 - GPIO core support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_CORE_H
-#define __ASM_ARCH_GPIO_CORE_H __FILE__
-
-#include <mach/regs-gpio.h>
-
-extern struct samsung_gpio_chip s3c24xx_gpios[];
-
-static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
-{
-        struct samsung_gpio_chip *chip;
-
-        if (pin > S3C_GPIO_END)
-                return NULL;
-
-        chip = &s3c24xx_gpios[pin/32];
-        return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
-}
-
-#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
index 6fac70f3484e..14591563ca70 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio.h
- *
+/*
  * Copyright (c) 2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
@@ -15,6 +14,9 @@
  * devices that need GPIO.
  */
 
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H __FILE__
+
 #ifdef CONFIG_CPU_S3C244X
 #define ARCH_NR_GPIOS   (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
 #elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
@@ -23,8 +25,83 @@
 #define ARCH_NR_GPIOS   (256 + CONFIG_S3C24XX_GPIO_EXTRA)
 #endif
 
-#include <mach/gpio-nrs.h>
-#include <mach/gpio-fns.h>
+/*
+ * GPIO sizes for various SoCs:
+ *
+ *   2410 2412 2440 2443 2416
+ *             2442
+ *   ---- ---- ---- ---- ----
+ * A  23   22   25   16   25
+ * B  11   11   11   11   9
+ * C  16   15   16   16   16
+ * D  16   16   16   16   16
+ * E  16   16   16   16   16
+ * F  8    8    8    8    8
+ * G  16   16   16   16   8
+ * H  11   11   9    15   15
+ * J  --   --   13   16   --
+ * K  --   --   --   --   16
+ * L  --   --   --   15   7
+ * M  --   --   --   2    2
+ */
+
+/* GPIO bank sizes */
+
+#define S3C2410_GPIO_A_NR       (32)
+#define S3C2410_GPIO_B_NR       (32)
+#define S3C2410_GPIO_C_NR       (32)
+#define S3C2410_GPIO_D_NR       (32)
+#define S3C2410_GPIO_E_NR       (32)
+#define S3C2410_GPIO_F_NR       (32)
+#define S3C2410_GPIO_G_NR       (32)
+#define S3C2410_GPIO_H_NR       (32)
+#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
+#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
+
+#if CONFIG_S3C_GPIO_SPACE != 0
+#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
+#endif
+
+#define S3C2410_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
+
+#ifndef __ASSEMBLY__
+
+enum s3c_gpio_number {
+        S3C2410_GPIO_A_START = 0,
+        S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
+        S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
+        S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
+        S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
+        S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
+        S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
+        S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
+        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
+        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
+        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
+        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
+};
+
+#endif /* __ASSEMBLY__ */
+
+/* S3C2410 GPIO number definitions. */
+
+#define S3C2410_GPA(_nr)        (S3C2410_GPIO_A_START + (_nr))
+#define S3C2410_GPB(_nr)        (S3C2410_GPIO_B_START + (_nr))
+#define S3C2410_GPC(_nr)        (S3C2410_GPIO_C_START + (_nr))
+#define S3C2410_GPD(_nr)        (S3C2410_GPIO_D_START + (_nr))
+#define S3C2410_GPE(_nr)        (S3C2410_GPIO_E_START + (_nr))
+#define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
+#define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
+#define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
+#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
+#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
+#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
+#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
+
+#include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_CPU_S3C244X
 #define S3C_GPIO_END    (S3C2410_GPJ(0) + 32)
@@ -33,3 +110,5 @@
 #else
 #define S3C_GPIO_END    (S3C2410_GPH(0) + 32)
 #endif
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940.h b/arch/arm/mach-s3c24xx/include/mach/h1940.h
deleted file mode 100644
index 2aa683c8d3d6..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/h1940.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/h1940.h
- *
- * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
- *
- * H1940 definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_H1940_H
-#define __ASM_ARCH_H1940_H
-
-#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
-#define H1940_SUSPEND_RESUMEAT          (0x30081000)
-#define H1940_SUSPEND_CHECK             (0x30080000)
-
-extern void h1940_pm_return(void);
-extern int h1940_led_blink_set(unsigned gpio, int state,
-        unsigned long *delay_on, unsigned long *delay_off);
-
-
-#endif /* __ASM_ARCH_H1940_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index aef5631eac58..a6cc14a092fc 100644
--- a/arch/arm/mach-s3c24xx/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
@@ -23,12 +23,6 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
 
 #endif /* CONFIG_CPU_S3C2440 */
 
-#ifdef CONFIG_CPU_S3C2412
-
-extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
-
-#endif /* CONFIG_CPU_S3C2412 */
-
 #endif /* __ASSEMBLY__ */
 
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/idle.h b/arch/arm/mach-s3c24xx/include/mach/idle.h
deleted file mode 100644
index e9ddd706b16e..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/idle.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/idle.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 CPU Idle controls
-*/
-
-#ifndef __ASM_ARCH_IDLE_H
-#define __ASM_ARCH_IDLE_H __FILE__
-
-/* This allows the over-ride of the default idle code, in case there
- * is any other things to be done over idle (like DVS)
-*/
-
-extern void (*s3c24xx_idle)(void);
-
-extern void s3c24xx_default_idle(void);
-
-#endif /* __ASM_ARCH_IDLE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
deleted file mode 100644
index e9e36b0abbac..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
- *
- * Copyright 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * OSIRIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_OSIRISCPLD_H
-#define __ASM_ARCH_OSIRISCPLD_H
-
-/* CTRL0 - NAND WP control */
-
-#define OSIRIS_CTRL0_NANDSEL            (0x3)
-#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
-#define OSIRIS_CTRL0_PCMCIA             (1<<4)
-#define OSIRIS_CTRL0_FIX8               (1<<5)
-#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
-#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
-
-#define OSIRIS_CTRL1_FIX8               (1<<0)
-
-#define OSIRIS_ID_REVMASK               (0x7)
-
-#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index a11a638bd599..c2ef016032ab 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -14,8 +14,6 @@
 #ifndef __ASM_ARCH_REGS_GPIO_H
 #define __ASM_ARCH_REGS_GPIO_H
 
-#include <mach/gpio-nrs.h>
-
 #define S3C24XX_MISCCR          S3C24XX_GPIOREG2(0x80)
 
 /* general configuration options */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
deleted file mode 100644
index e0c67b0163d8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Memory Control register definitions
-*/
-
-#ifndef __ASM_ARM_MEMREGS_H
-#define __ASM_ARM_MEMREGS_H
-
-#ifndef S3C2410_MEMREG
-#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-
-/* bus width, and wait state control */
-#define S3C2410_BWSCON                  S3C2410_MEMREG(0x0000)
-
-/* bank zero config - note, pinstrapped from OM pins! */
-#define S3C2410_BWSCON_DW0_16           (1<<1)
-#define S3C2410_BWSCON_DW0_32           (2<<1)
-
-/* bank one configs */
-#define S3C2410_BWSCON_DW1_8            (0<<4)
-#define S3C2410_BWSCON_DW1_16           (1<<4)
-#define S3C2410_BWSCON_DW1_32           (2<<4)
-#define S3C2410_BWSCON_WS1              (1<<6)
-#define S3C2410_BWSCON_ST1              (1<<7)
-
-/* bank 2 configurations */
-#define S3C2410_BWSCON_DW2_8            (0<<8)
-#define S3C2410_BWSCON_DW2_16           (1<<8)
-#define S3C2410_BWSCON_DW2_32           (2<<8)
-#define S3C2410_BWSCON_WS2              (1<<10)
-#define S3C2410_BWSCON_ST2              (1<<11)
-
-/* bank 3 configurations */
-#define S3C2410_BWSCON_DW3_8            (0<<12)
-#define S3C2410_BWSCON_DW3_16           (1<<12)
-#define S3C2410_BWSCON_DW3_32           (2<<12)
-#define S3C2410_BWSCON_WS3              (1<<14)
-#define S3C2410_BWSCON_ST3              (1<<15)
-
-/* bank 4 configurations */
-#define S3C2410_BWSCON_DW4_8            (0<<16)
-#define S3C2410_BWSCON_DW4_16           (1<<16)
-#define S3C2410_BWSCON_DW4_32           (2<<16)
-#define S3C2410_BWSCON_WS4              (1<<18)
-#define S3C2410_BWSCON_ST4              (1<<19)
-
-/* bank 5 configurations */
-#define S3C2410_BWSCON_DW5_8            (0<<20)
-#define S3C2410_BWSCON_DW5_16           (1<<20)
-#define S3C2410_BWSCON_DW5_32           (2<<20)
-#define S3C2410_BWSCON_WS5              (1<<22)
-#define S3C2410_BWSCON_ST5              (1<<23)
-
-/* bank 6 configurations */
-#define S3C2410_BWSCON_DW6_8            (0<<24)
-#define S3C2410_BWSCON_DW6_16           (1<<24)
-#define S3C2410_BWSCON_DW6_32           (2<<24)
-#define S3C2410_BWSCON_WS6              (1<<26)
-#define S3C2410_BWSCON_ST6              (1<<27)
-
-/* bank 7 configurations */
-#define S3C2410_BWSCON_DW7_8            (0<<28)
-#define S3C2410_BWSCON_DW7_16           (1<<28)
-#define S3C2410_BWSCON_DW7_32           (2<<28)
-#define S3C2410_BWSCON_WS7              (1<<30)
-#define S3C2410_BWSCON_ST7              (1<<31)
-
-/* accesor functions for getting BANK(n) configuration. (n != 0) */
-
-#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
-
-#define S3C2410_BWSCON_DW8              (0)
-#define S3C2410_BWSCON_DW16             (1)
-#define S3C2410_BWSCON_DW32             (2)
-#define S3C2410_BWSCON_WS               (1 << 2)
-#define S3C2410_BWSCON_ST               (1 << 3)
-
-/* memory set (rom, ram) */
-#define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
-#define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
-#define S3C2410_BANKCON2                S3C2410_MEMREG(0x000C)
-#define S3C2410_BANKCON3                S3C2410_MEMREG(0x0010)
-#define S3C2410_BANKCON4                S3C2410_MEMREG(0x0014)
-#define S3C2410_BANKCON5                S3C2410_MEMREG(0x0018)
-#define S3C2410_BANKCON6                S3C2410_MEMREG(0x001C)
-#define S3C2410_BANKCON7                S3C2410_MEMREG(0x0020)
-
-/* bank configuration registers */
-
-#define S3C2410_BANKCON_PMCnorm         (0x00)
-#define S3C2410_BANKCON_PMC4            (0x01)
-#define S3C2410_BANKCON_PMC8            (0x02)
-#define S3C2410_BANKCON_PMC16           (0x03)
-
-/* bank configurations for banks 0..7, note banks
- * 6 and 7 have different configurations depending on
- * the memory type bits */
-
-#define S3C2410_BANKCON_Tacp2           (0x0 << 2)
-#define S3C2410_BANKCON_Tacp3           (0x1 << 2)
-#define S3C2410_BANKCON_Tacp4           (0x2 << 2)
-#define S3C2410_BANKCON_Tacp6           (0x3 << 2)
-#define S3C2410_BANKCON_Tacp_SHIFT      (2)
-
-#define S3C2410_BANKCON_Tcah0           (0x0 << 4)
-#define S3C2410_BANKCON_Tcah1           (0x1 << 4)
-#define S3C2410_BANKCON_Tcah2           (0x2 << 4)
-#define S3C2410_BANKCON_Tcah4           (0x3 << 4)
-#define S3C2410_BANKCON_Tcah_SHIFT      (4)
-
-#define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
-#define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
-#define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
-#define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
-#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
-
-#define S3C2410_BANKCON_Tacc1           (0x0 << 8)
-#define S3C2410_BANKCON_Tacc2           (0x1 << 8)
-#define S3C2410_BANKCON_Tacc3           (0x2 << 8)
-#define S3C2410_BANKCON_Tacc4           (0x3 << 8)
-#define S3C2410_BANKCON_Tacc6           (0x4 << 8)
-#define S3C2410_BANKCON_Tacc8           (0x5 << 8)
-#define S3C2410_BANKCON_Tacc10          (0x6 << 8)
-#define S3C2410_BANKCON_Tacc14          (0x7 << 8)
-#define S3C2410_BANKCON_Tacc_SHIFT      (8)
-
-#define S3C2410_BANKCON_Tcos0           (0x0 << 11)
-#define S3C2410_BANKCON_Tcos1           (0x1 << 11)
-#define S3C2410_BANKCON_Tcos2           (0x2 << 11)
-#define S3C2410_BANKCON_Tcos4           (0x3 << 11)
-#define S3C2410_BANKCON_Tcos_SHIFT      (11)
-
-#define S3C2410_BANKCON_Tacs0           (0x0 << 13)
-#define S3C2410_BANKCON_Tacs1           (0x1 << 13)
-#define S3C2410_BANKCON_Tacs2           (0x2 << 13)
-#define S3C2410_BANKCON_Tacs4           (0x3 << 13)
-#define S3C2410_BANKCON_Tacs_SHIFT      (13)
-
-#define S3C2410_BANKCON_SRAM            (0x0 << 15)
-#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
-
-/* next bits only for SDRAM in 6,7 */
-#define S3C2410_BANKCON_Trcd2           (0x00 << 2)
-#define S3C2410_BANKCON_Trcd3           (0x01 << 2)
-#define S3C2410_BANKCON_Trcd4           (0x02 << 2)
-
-/* control column address select */
-#define S3C2410_BANKCON_SCANb8          (0x00 << 0)
-#define S3C2410_BANKCON_SCANb9          (0x01 << 0)
-#define S3C2410_BANKCON_SCANb10         (0x02 << 0)
-
-#define S3C2410_REFRESH                 S3C2410_MEMREG(0x0024)
-#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x0028)
-#define S3C2410_MRSRB6                  S3C2410_MEMREG(0x002C)
-#define S3C2410_MRSRB7                  S3C2410_MEMREG(0x0030)
-
-/* refresh control */
-
-#define S3C2410_REFRESH_REFEN           (1<<23)
-#define S3C2410_REFRESH_SELF            (1<<22)
-#define S3C2410_REFRESH_REFCOUNTER      ((1<<11)-1)
-
-#define S3C2410_REFRESH_TRP_MASK        (3<<20)
-#define S3C2410_REFRESH_TRP_2clk        (0<<20)
-#define S3C2410_REFRESH_TRP_3clk        (1<<20)
-#define S3C2410_REFRESH_TRP_4clk        (2<<20)
-
-#define S3C2410_REFRESH_TSRC_MASK       (3<<18)
-#define S3C2410_REFRESH_TSRC_4clk       (0<<18)
-#define S3C2410_REFRESH_TSRC_5clk       (1<<18)
-#define S3C2410_REFRESH_TSRC_6clk       (2<<18)
-#define S3C2410_REFRESH_TSRC_7clk       (3<<18)
-
-
-/* mode select register(s) */
-
-#define  S3C2410_MRSRB_CL1              (0x00 << 4)
-#define  S3C2410_MRSRB_CL2              (0x02 << 4)
-#define  S3C2410_MRSRB_CL3              (0x03 << 4)
-
-/* bank size register */
-#define S3C2410_BANKSIZE_128M           (0x2 << 0)
-#define S3C2410_BANKSIZE_64M            (0x1 << 0)
-#define S3C2410_BANKSIZE_32M            (0x0 << 0)
-#define S3C2410_BANKSIZE_16M            (0x7 << 0)
-#define S3C2410_BANKSIZE_8M             (0x6 << 0)
-#define S3C2410_BANKSIZE_4M             (0x5 << 0)
-#define S3C2410_BANKSIZE_2M             (0x4 << 0)
-#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
-#define S3C2410_BANKSIZE_SCLK_EN        (1<<4)
-#define S3C2410_BANKSIZE_SCKE_EN        (1<<5)
-#define S3C2410_BANKSIZE_BURST          (1<<7)
-
-#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
deleted file mode 100644
index 4932b87bdf3d..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-power.h
- *
- * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX power control register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_PWR
-#define __ASM_ARM_REGS_PWR __FILE__
-
-#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
-
-#define S3C2412_PWRMODECON      S3C24XX_PWRREG(0x20)
-#define S3C2412_PWRCFG          S3C24XX_PWRREG(0x24)
-
-#define S3C2412_INFORM0         S3C24XX_PWRREG(0x70)
-#define S3C2412_INFORM1         S3C24XX_PWRREG(0x74)
-#define S3C2412_INFORM2         S3C24XX_PWRREG(0x78)
-#define S3C2412_INFORM3         S3C24XX_PWRREG(0x7C)
-
-#define S3C2412_PWRCFG_BATF_IRQ                 (1<<0)
-#define S3C2412_PWRCFG_BATF_IGNORE              (2<<0)
-#define S3C2412_PWRCFG_BATF_SLEEP               (3<<0)
-#define S3C2412_PWRCFG_BATF_MASK                (3<<0)
-
-#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3<<6)
-
-#define S3C2412_PWRCFG_RTC_MASKIRQ              (1<<8)
-#define S3C2412_PWRCFG_NAND_NORST               (1<<9)
-
-#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
deleted file mode 100644
index fb6352515090..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 memory register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_S3C2412_MEM
-#define __ASM_ARM_REGS_S3C2412_MEM
-
-#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
-
-#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
-#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
-
-#define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
-#define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
-#define S3C2412_BANKCON2                S3C2412_MEMREG(0x08)
-#define S3C2412_BANKCON3                S3C2412_MEMREG(0x0C)
-
-#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
-#define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
-
-/* EBI control registers */
-
-#define S3C2412_EBI_PR                  S3C2412_EBIREG(0x00)
-#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x04)
-
-/* SSMC control registers */
-
-#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x00)
-#define S3C2412_SMIDCYR(x)              S3C2412_SSMC(x, 0x00)
-#define S3C2412_SMBWSTRD(x)             S3C2412_SSMC(x, 0x04)
-#define S3C2412_SMBWSTWRR(x)            S3C2412_SSMC(x, 0x08)
-#define S3C2412_SMBWSTOENR(x)           S3C2412_SSMC(x, 0x0C)
-#define S3C2412_SMBWSTWENR(x)           S3C2412_SSMC(x, 0x10)
-#define S3C2412_SMBCR(x)                S3C2412_SSMC(x, 0x14)
-#define S3C2412_SMBSR(x)                S3C2412_SSMC(x, 0x18)
-#define S3C2412_SMBWSTBRDR(x)           S3C2412_SSMC(x, 0x1C)
-
-#endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
deleted file mode 100644
index aa69dc79bc38..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
- *
- * Copyright 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 specific register definitions
-*/
-
-#ifndef __ASM_ARCH_REGS_S3C2412_H
-#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
-
-#define S3C2412_SWRST           (S3C24XX_VA_CLKPWR + 0x30)
-#define S3C2412_SWRST_RESET     (0x533C2412)
-
-/* see regs-power.h for the other registers in the power block. */
-
-#endif  /* __ASM_ARCH_REGS_S3C2412_H */
-
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
deleted file mode 100644
index 2f31b74974af..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2416 memory register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_S3C2416_MEM
-#define __ASM_ARM_REGS_S3C2416_MEM
-
-#ifndef S3C2416_MEMREG
-#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-
-#define S3C2416_BANKCFG                 S3C2416_MEMREG(0x00)
-#define S3C2416_BANKCON1                S3C2416_MEMREG(0x04)
-#define S3C2416_BANKCON2                S3C2416_MEMREG(0x08)
-#define S3C2416_BANKCON3                S3C2416_MEMREG(0x0C)
-
-#define S3C2416_REFRESH                 S3C2416_MEMREG(0x10)
-#define S3C2416_TIMEOUT                 S3C2416_MEMREG(0x14)
-
-#endif /*  __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
deleted file mode 100644
index e443167efb87..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2416 specific register definitions
-*/
-
-#ifndef __ASM_ARCH_REGS_S3C2416_H
-#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
-
-#define S3C2416_SWRST           (S3C24XX_VA_CLKPWR + 0x44)
-#define S3C2416_SWRST_RESET     (0x533C2416)
-
-/* see regs-power.h for the other registers in the power block. */
-
-#endif  /* __ASM_ARCH_REGS_S3C2416_H */
-
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
deleted file mode 100644
index e4119913d7c5..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * VR1000 - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_VR1000CPLD_H
-#define __ASM_ARCH_VR1000CPLD_H
-
-#define VR1000_CPLD_CTRL2_RAMWEN     (0x04)   /* SRAM Write Enable */
-
-#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
deleted file mode 100644
index 47add133b8ee..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_VR1000IRQ_H
-#define __ASM_ARCH_VR1000IRQ_H
-
-/* irq numbers to onboard peripherals */
-
-#define IRQ_USBOC            IRQ_EINT19
-#define IRQ_IDE0             IRQ_EINT16
-#define IRQ_IDE1             IRQ_EINT17
-#define IRQ_VR1000_SERIAL    IRQ_EINT12
-#define IRQ_VR1000_DM9000A   IRQ_EINT10
-#define IRQ_VR1000_DM9000N   IRQ_EINT9
-#define IRQ_SMALERT          IRQ_EINT8
-
-#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
deleted file mode 100644
index 28376e56dd3b..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-
-#ifndef __ASM_ARCH_VR1000MAP_H
-#define __ASM_ARCH_VR1000MAP_H
-
-#include <mach/bast-map.h>
-
-#define VR1000_IOADDR(x) BAST_IOADDR(x)
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define VR1000_VA_CTRL1     VR1000_IOADDR(0x00000000)    /* 0x01300000 */
-#define VR1000_PA_CTRL1     (S3C2410_CS5 | 0x7800000)
-
-#define VR1000_VA_CTRL2     VR1000_IOADDR(0x00100000)    /* 0x01400000 */
-#define VR1000_PA_CTRL2     (S3C2410_CS1 | 0x6000000)
-
-#define VR1000_VA_CTRL3     VR1000_IOADDR(0x00200000)    /* 0x01500000 */
-#define VR1000_PA_CTRL3     (S3C2410_CS1 | 0x6800000)
-
-#define VR1000_VA_CTRL4     VR1000_IOADDR(0x00300000)    /* 0x01600000 */
-#define VR1000_PA_CTRL4     (S3C2410_CS1 | 0x7000000)
-
-/* next, we have the PC104 ISA interrupt registers */
-
-#define VR1000_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define VR1000_VA_PC104_IRQREQ  VR1000_IOADDR(0x00400000)
-
-#define VR1000_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define VR1000_VA_PC104_IRQRAW  VR1000_IOADDR(0x00500000)
-
-#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
-
-/* 0xE0000000 contains the IO space that is split by speed and
- * whether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
- * 0x02600000 to 0x02700000 1MB
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-
-#define VR1000_VA_MULTISPACE (0xE0000000)
-
-#define VR1000_VA_ISAIO            (VR1000_VA_MULTISPACE + 0x00000000)
-#define VR1000_VA_ISAMEM           (VR1000_VA_MULTISPACE + 0x01000000)
-#define VR1000_VA_IDEPRI           (VR1000_VA_MULTISPACE + 0x02000000)
-#define VR1000_VA_IDEPRIAUX        (VR1000_VA_MULTISPACE + 0x02100000)
-#define VR1000_VA_IDESEC           (VR1000_VA_MULTISPACE + 0x02200000)
-#define VR1000_VA_IDESECAUX        (VR1000_VA_MULTISPACE + 0x02300000)
-#define VR1000_VA_ASIXNET          (VR1000_VA_MULTISPACE + 0x02400000)
-#define VR1000_VA_DM9000           (VR1000_VA_MULTISPACE + 0x02500000)
-#define VR1000_VA_SUPERIO          (VR1000_VA_MULTISPACE + 0x02600000)
-
-/* physical offset addresses for the peripherals */
-
-#define VR1000_PA_IDEPRI           (0x02000000)
-#define VR1000_PA_IDEPRIAUX        (0x02800000)
-#define VR1000_PA_IDESEC           (0x03000000)
-#define VR1000_PA_IDESECAUX        (0x03800000)
-#define VR1000_PA_DM9000           (0x05000000)
-
-#define VR1000_PA_SERIAL           (0x11800000)
-#define VR1000_VA_SERIAL           (VR1000_IOADDR(0x00700000))
-
-/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
-#define VR1000_PA_SRAM             (S3C2410_CS1 | 0x05000000)
-
-/* some configurations for the peripherals */
-
-#define VR1000_DM9000_CS         VR1000_VAM_CS4
-
-#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
new file mode 100644
index 000000000000..4cd13ab6496b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
@@ -0,0 +1,478 @@
+/*
+ * Copyright (c) 2006-2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+#include <linux/seq_file.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu-freq-core.h>
+
+#include "regs-mem.h"
+
+#define print_ns(x) ((x) / 10), ((x) % 10)
+
+/**
+ * s3c2410_print_timing - print bank timing data for debug purposes
+ * @pfx: The prefix to put on the output
+ * @timings: The timing inforamtion to print.
+*/
+static void s3c2410_print_timing(const char *pfx,
+                                 struct s3c_iotimings *timings)
+{
+        struct s3c2410_iobank_timing *bt;
+        int bank;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = timings->bank[bank].io_2410;
+                if (!bt)
+                        continue;
+
+                printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
+                       "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
+                       print_ns(bt->tacs),
+                       print_ns(bt->tcos),
+                       print_ns(bt->tacc),
+                       print_ns(bt->tcoh),
+                       print_ns(bt->tcah));
+        }
+}
+
+/**
+ * bank_reg - convert bank number to pointer to the control register.
+ * @bank: The IO bank number.
+ */
+static inline void __iomem *bank_reg(unsigned int bank)
+{
+        return S3C2410_BANKCON0 + (bank << 2);
+}
+
+/**
+ * bank_is_io - test whether bank is used for IO
+ * @bankcon: The bank control register.
+ *
+ * This is a simplistic test to see if any BANKCON[x] is not an IO
+ * bank. It currently does not take into account whether BWSCON has
+ * an illegal width-setting in it, or if the pin connected to nCS[x]
+ * is actually being handled as a chip-select.
+ */
+static inline int bank_is_io(unsigned long bankcon)
+{
+        return !(bankcon & S3C2410_BANKCON_SDRAM);
+}
+
+/**
+ * to_div - convert cycle time to divisor
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ *
+ * Convert the given cycle time into the divisor to use to obtain it from
+ * HCLK.
+*/
+static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
+{
+        if (cyc == 0)
+                return 0;
+
+        return DIV_ROUND_UP(cyc, hclk_tns);
+}
+
+/**
+ * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @v: Pointer to register to alter.
+ * @shift: The shift to get to the control bits.
+ *
+ * Calculate the divisor, and turn it into the correct control bits to
+ * set in the result, @v.
+ */
+static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
+                              unsigned long *v, int shift)
+{
+        unsigned int div = to_div(cyc, hclk_tns);
+        unsigned long val;
+
+        s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
+                       __func__, cyc, hclk_tns, shift, div);
+
+        switch (div) {
+        case 0:
+                val = 0;
+                break;
+        case 1:
+                val = 1;
+                break;
+        case 2:
+                val = 2;
+                break;
+        case 3:
+        case 4:
+                val = 3;
+                break;
+        default:
+                return -1;
+        }
+
+        *v |= val << shift;
+        return 0;
+}
+
+int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
+{
+        /* Currently no support for Tacp calculations. */
+        return 0;
+}
+
+/**
+ * calc_tacc - calculate divisor control for tacc.
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @nwait_en: IS nWAIT enabled for this bank.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @v: Pointer to register to alter.
+ *
+ * Calculate the divisor control for tACC, taking into account whether
+ * the bank has nWAIT enabled. The result is used to modify the value
+ * pointed to by @v.
+*/
+static int calc_tacc(unsigned int cyc, int nwait_en,
+                     unsigned long hclk_tns, unsigned long *v)
+{
+        unsigned int div = to_div(cyc, hclk_tns);
+        unsigned long val;
+
+        s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
+                       __func__, cyc, nwait_en, hclk_tns, div);
+
+        /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
+        if (nwait_en && div < 4)
+                div = 4;
+
+        switch (div) {
+        case 0:
+                val = 0;
+                break;
+
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+                val = div - 1;
+                break;
+
+        case 5:
+        case 6:
+                val = 4;
+                break;
+
+        case 7:
+        case 8:
+                val = 5;
+                break;
+
+        case 9:
+        case 10:
+                val = 6;
+                break;
+
+        case 11:
+        case 12:
+        case 13:
+        case 14:
+                val = 7;
+                break;
+
+        default:
+                return -1;
+        }
+
+        *v |= val << 8;
+        return 0;
+}
+
+/**
+ * s3c2410_calc_bank - calculate bank timing infromation
+ * @cfg: The configuration we need to calculate for.
+ * @bt: The bank timing information.
+ *
+ * Given the cycle timine for a bank @bt, calculate the new BANKCON
+ * setting for the @cfg timing. This updates the timing information
+ * ready for the cpu frequency change.
+ */
+static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
+                             struct s3c2410_iobank_timing *bt)
+{
+        unsigned long hclk = cfg->freq.hclk_tns;
+        unsigned long res;
+        int ret;
+
+        res  = bt->bankcon;
+        res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
+
+        /* tacp: 2,3,4,5 */
+        /* tcah: 0,1,2,4 */
+        /* tcoh: 0,1,2,4 */
+        /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
+        /* tcos: 0,1,2,4 */
+        /* tacs: 0,1,2,4 */
+
+        ret  = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
+        ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
+        ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
+        ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
+
+        if (ret)
+                return -EINVAL;
+
+        ret |= calc_tacp(bt->tacp, hclk, &res);
+        ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
+
+        if (ret)
+                return -EINVAL;
+
+        bt->bankcon = res;
+        return 0;
+}
+
+static unsigned int tacc_tab[] = {
+        [0]     = 1,
+        [1]     = 2,
+        [2]     = 3,
+        [3]     = 4,
+        [4]     = 6,
+        [5]     = 9,
+        [6]     = 10,
+        [7]     = 14,
+};
+
+/**
+ * get_tacc - turn tACC value into cycle time
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @val: The bank timing register value, shifed down.
+ */
+static unsigned int get_tacc(unsigned long hclk_tns,
+                             unsigned long val)
+{
+        val &= 7;
+        return hclk_tns * tacc_tab[val];
+}
+
+/**
+ * get_0124 - turn 0/1/2/4 divider into cycle time
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @val: The bank timing register value, shifed down.
+ */
+static unsigned int get_0124(unsigned long hclk_tns,
+                             unsigned long val)
+{
+        val &= 3;
+        return hclk_tns * ((val == 3) ? 4 : val);
+}
+
+/**
+ * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
+ * @cfg: The frequency configuration
+ * @bt: The bank timing to fill in (uses cached BANKCON)
+ *
+ * Given the BANKCON setting in @bt and the current frequency settings
+ * in @cfg, update the cycle timing information.
+ */
+void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
+                              struct s3c2410_iobank_timing *bt)
+{
+        unsigned long bankcon = bt->bankcon;
+        unsigned long hclk = cfg->freq.hclk_tns;
+
+        bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
+        bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
+        bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
+        bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
+        bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
+}
+
+/**
+ * s3c2410_iotiming_debugfs - debugfs show io bank timing information
+ * @seq: The seq_file to write output to using seq_printf().
+ * @cfg: The current configuration.
+ * @iob: The IO bank information to decode.
+ */
+void s3c2410_iotiming_debugfs(struct seq_file *seq,
+                              struct s3c_cpufreq_config *cfg,
+                              union s3c_iobank *iob)
+{
+        struct s3c2410_iobank_timing *bt = iob->io_2410;
+        unsigned long bankcon = bt->bankcon;
+        unsigned long hclk = cfg->freq.hclk_tns;
+        unsigned int tacs;
+        unsigned int tcos;
+        unsigned int tacc;
+        unsigned int tcoh;
+        unsigned int tcah;
+
+        seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
+
+        tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
+        tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
+        tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
+        tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
+        tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
+
+        seq_printf(seq,
+                   "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
+                   print_ns(bt->tacs),
+                   print_ns(bt->tcos),
+                   print_ns(bt->tacc),
+                   print_ns(bt->tcoh),
+                   print_ns(bt->tcah));
+
+        seq_printf(seq,
+                   "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
+                   print_ns(tacs),
+                   print_ns(tcos),
+                   print_ns(tacc),
+                   print_ns(tcoh),
+                   print_ns(tcah));
+}
+
+/**
+ * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
+ * @cfg: The frequency configuration
+ * @iot: The IO timing information to fill out.
+ *
+ * Calculate the new values for the banks in @iot based on the new
+ * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
+ * to update the timing when necessary.
+ */
+int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2410_iobank_timing *bt;
+        unsigned long bankcon;
+        int bank;
+        int ret;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bankcon = __raw_readl(bank_reg(bank));
+                bt = iot->bank[bank].io_2410;
+
+                if (!bt)
+                        continue;
+
+                bt->bankcon = bankcon;
+
+                ret = s3c2410_calc_bank(cfg, bt);
+                if (ret) {
+                        printk(KERN_ERR "%s: cannot calculate bank %d io\n",
+                               __func__, bank);
+                        goto err;
+                }
+
+                s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
+                               __func__, bank, bt->bankcon);
+        }
+
+        return 0;
+ err:
+        return ret;
+}
+
+/**
+ * s3c2410_iotiming_set - set the IO timings from the given setup.
+ * @cfg: The frequency configuration
+ * @iot: The IO timing information to use.
+ *
+ * Set all the currently used IO bank timing information generated
+ * by s3c2410_iotiming_calc() once the core has validated that all
+ * the new values are within permitted bounds.
+ */
+void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2410_iobank_timing *bt;
+        int bank;
+
+        /* set the io timings from the specifier */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2410;
+                if (!bt)
+                        continue;
+
+                __raw_writel(bt->bankcon, bank_reg(bank));
+        }
+}
+
+/**
+ * s3c2410_iotiming_get - Get the timing information from current registers.
+ * @cfg: The frequency configuration
+ * @timings: The IO timing information to fill out.
+ *
+ * Calculate the @timings timing information from the current frequency
+ * information in @cfg, and the new frequency configur
+ * through all the IO banks, reading the state and then updating @iot
+ * as necessary.
+ *
+ * This is used at the moment on initialisation to get the current
+ * configuration so that boards do not have to carry their own setup
+ * if the timings are correct on initialisation.
+ */
+
+int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
+                         struct s3c_iotimings *timings)
+{
+        struct s3c2410_iobank_timing *bt;
+        unsigned long bankcon;
+        unsigned long bwscon;
+        int bank;
+
+        bwscon = __raw_readl(S3C2410_BWSCON);
+
+        /* look through all banks to see what is currently set. */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bankcon = __raw_readl(bank_reg(bank));
+
+                if (!bank_is_io(bankcon))
+                        continue;
+
+                s3c_freq_iodbg("%s: bank %d: con %08lx\n",
+                               __func__, bank, bankcon);
+
+                bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
+                if (!bt) {
+                        printk(KERN_ERR "%s: no memory for bank\n", __func__);
+                        return -ENOMEM;
+                }
+
+                /* find out in nWait is enabled for bank. */
+
+                if (bank != 0) {
+                        unsigned long tmp  = S3C2410_BWSCON_GET(bwscon, bank);
+                        if (tmp & S3C2410_BWSCON_WS)
+                                bt->nwait_en = 1;
+                }
+
+                timings->bank[bank].io_2410 = bt;
+                bt->bankcon = bankcon;
+
+                s3c2410_iotiming_getbank(cfg, bt);
+        }
+
+        s3c2410_print_timing("get", timings);
+        return 0;
+}
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
new file mode 100644
index 000000000000..663436d9db01
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412/S3C2443 (PL093 based) IO timing support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/seq_file.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <linux/amba/pl093.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+#include <plat/clock.h>
+
+#include "s3c2412.h"
+
+#define print_ns(x) ((x) / 10), ((x) % 10)
+
+/**
+ * s3c2412_print_timing - print timing infromation via printk.
+ * @pfx: The prefix to print each line with.
+ * @iot: The IO timing information
+ */
+static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        unsigned int bank;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+
+                printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
+                       "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
+                       print_ns(bt->idcy),
+                       print_ns(bt->wstrd),
+                       print_ns(bt->wstwr),
+                       print_ns(bt->wstoen),
+                       print_ns(bt->wstwen),
+                       print_ns(bt->wstbrd));
+        }
+}
+
+/**
+ * to_div - turn a cycle length into a divisor setting.
+ * @cyc_tns: The cycle time in 10ths of nanoseconds.
+ * @clk_tns: The clock period in 10ths of nanoseconds.
+ */
+static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
+{
+        return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
+}
+
+/**
+ * calc_timing - calculate timing divisor value and check in range.
+ * @hwtm: The hardware timing in 10ths of nanoseconds.
+ * @clk_tns: The clock period in 10ths of nanoseconds.
+ * @err: Pointer to err variable to update in event of failure.
+ */
+static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
+                                unsigned int *err)
+{
+        unsigned int ret = to_div(hwtm, clk_tns);
+
+        if (ret > 0xf)
+                *err = -EINVAL;
+
+        return ret;
+}
+
+/**
+ * s3c2412_calc_bank - calculate the bank divisor settings.
+ * @cfg: The current frequency configuration.
+ * @bt: The bank timing.
+ */
+static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
+                             struct s3c2412_iobank_timing *bt)
+{
+        unsigned int hclk = cfg->freq.hclk_tns;
+        int err = 0;
+
+        bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
+        bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
+        bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
+        bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
+        bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
+        bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
+
+        return err;
+}
+
+/**
+ * s3c2412_iotiming_debugfs - debugfs show io bank timing information
+ * @seq: The seq_file to write output to using seq_printf().
+ * @cfg: The current configuration.
+ * @iob: The IO bank information to decode.
+*/
+void s3c2412_iotiming_debugfs(struct seq_file *seq,
+                              struct s3c_cpufreq_config *cfg,
+                              union s3c_iobank *iob)
+{
+        struct s3c2412_iobank_timing *bt = iob->io_2412;
+
+        seq_printf(seq,
+                   "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
+                   "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
+                   print_ns(bt->idcy),
+                   print_ns(bt->wstrd),
+                   print_ns(bt->wstwr),
+                   print_ns(bt->wstoen),
+                   print_ns(bt->wstwen),
+                   print_ns(bt->wstbrd));
+}
+
+/**
+ * s3c2412_iotiming_calc - calculate all the bank divisor settings.
+ * @cfg: The current frequency configuration.
+ * @iot: The bank timing information.
+ *
+ * Calculate the timing information for all the banks that are
+ * configured as IO, using s3c2412_calc_bank().
+ */
+int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        int bank;
+        int ret;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+
+                ret = s3c2412_calc_bank(cfg, bt);
+                if (ret) {
+                        printk(KERN_ERR "%s: cannot calculate bank %d io\n",
+                               __func__, bank);
+                        goto err;
+                }
+        }
+
+        return 0;
+ err:
+        return ret;
+}
+
+/**
+ * s3c2412_iotiming_set - set the timing information
+ * @cfg: The current frequency configuration.
+ * @iot: The bank timing information.
+ *
+ * Set the IO bank information from the details calculated earlier from
+ * calling s3c2412_iotiming_calc().
+ */
+void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        void __iomem *regs;
+        int bank;
+
+        /* set the io timings from the specifier */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+
+                regs = S3C2412_SSMC_BANK(bank);
+
+                __raw_writel(bt->smbidcyr, regs + SMBIDCYR);
+                __raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
+                __raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
+                __raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
+                __raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
+                __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
+        }
+}
+
+static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
+{
+        return (reg & 0xf) * clock;
+}
+
+static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
+                                     struct s3c2412_iobank_timing *bt,
+                                     unsigned int bank)
+{
+        unsigned long clk = cfg->freq.hclk_tns;  /* ssmc clock??? */
+        void __iomem *regs = S3C2412_SSMC_BANK(bank);
+
+        bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
+        bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
+        bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
+        bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
+        bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
+}
+
+/**
+ * bank_is_io - return true if bank is (possibly) IO.
+ * @bank: The bank number.
+ * @bankcfg: The value of S3C2412_EBI_BANKCFG.
+ */
+static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
+{
+        if (bank < 2)
+                return true;
+
+        return !(bankcfg & (1 << bank));
+}
+
+int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
+                         struct s3c_iotimings *timings)
+{
+        struct s3c2412_iobank_timing *bt;
+        u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
+        unsigned int bank;
+
+        /* look through all banks to see what is currently set. */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                if (!bank_is_io(bank, bankcfg))
+                        continue;
+
+                bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL);
+                if (!bt) {
+                        printk(KERN_ERR "%s: no memory for bank\n", __func__);
+                        return -ENOMEM;
+                }
+
+                timings->bank[bank].io_2412 = bt;
+                s3c2412_iotiming_getbank(cfg, bt, bank);
+        }
+
+        s3c2412_print_timing("get", timings);
+        return 0;
+}
+
+/* this is in here as it is so small, it doesn't currently warrant a file
+ * to itself. We expect that any s3c24xx needing this is going to also
+ * need the iotiming support.
+ */
+void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        u32 refresh;
+
+        WARN_ON(board == NULL);
+
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * down to ensure that we do not overflow 32 bit numbers.
+         *
+         * This should work for HCLK up to 133MHz and refresh period up
+         * to 30usec.
+         */
+
+        refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
+        refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
+        refresh &= ((1 << 16) - 1);
+
+        s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
+
+        __raw_writel(refresh, S3C2412_REFRESH);
+}
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index 0efb2e2848c8..e1199599873e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/syscore_ops.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -29,18 +30,18 @@
  * set bit to 1 in allow bitfield to enable the wakeup settings on it
 */
 
-unsigned long s3c_irqwake_intallow      = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
+unsigned long s3c_irqwake_intallow      = 1L << 30 | 0xfL;
 unsigned long s3c_irqwake_eintallow     = 0x0000fff0L;
 
 int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
-        unsigned long irqbit = 1 << (data->irq - IRQ_EINT0);
+        unsigned long irqbit = 1 << data->hwirq;
 
         if (!(s3c_irqwake_intallow & irqbit))
                 return -ENOENT;
 
-        printk(KERN_INFO "wake %s for irq %d\n",
-               state ? "enabled" : "disabled", data->irq);
+        pr_info("wake %s for hwirq %lu\n",
+                state ? "enabled" : "disabled", data->hwirq);
 
         if (!state)
                 s3c_irqwake_intmask |= irqbit;
@@ -64,7 +65,7 @@ static unsigned long save_extint[3];
 static unsigned long save_eintflt[4];
 static unsigned long save_eintmask;
 
-int s3c24xx_irq_suspend(void)
+static int s3c24xx_irq_suspend(void)
 {
         unsigned int i;
 
@@ -80,7 +81,7 @@ int s3c24xx_irq_suspend(void)
         return 0;
 }
 
-void s3c24xx_irq_resume(void)
+static void s3c24xx_irq_resume(void)
 {
         unsigned int i;
 
@@ -93,3 +94,31 @@ void s3c24xx_irq_resume(void)
         s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
         __raw_writel(save_eintmask, S3C24XX_EINTMASK);
 }
+
+struct syscore_ops s3c24xx_irq_syscore_ops = {
+        .suspend        = s3c24xx_irq_suspend,
+        .resume         = s3c24xx_irq_resume,
+};
+
+#ifdef CONFIG_CPU_S3C2416
+static struct sleep_save s3c2416_irq_save[] = {
+        SAVE_ITEM(S3C2416_INTMSK2),
+};
+
+static int s3c2416_irq_suspend(void)
+{
+        s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
+
+        return 0;
+}
+
+static void s3c2416_irq_resume(void)
+{
+        s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
+}
+
+struct syscore_ops s3c2416_irq_syscore_ops = {
+        .suspend        = s3c2416_irq_suspend,
+        .resume         = s3c2416_irq_resume,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
index e65619ddbccc..67d763178d3f 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2412.c
@@ -33,12 +33,13 @@
 
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-power.h>
 
 #include <plat/cpu.h>
 #include <plat/irq.h>
 #include <plat/pm.h>
 
+#include "s3c2412-power.h"
+
 #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
 #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
 
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
deleted file mode 100644
index ff141b0af26b..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/irq.c
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-
-static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
-{
-        unsigned int subsrc, submsk;
-        unsigned int end;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc  &= ~submsk;
-        subsrc >>= (irq - S3C2410_IRQSUB(0));
-        subsrc  &= (1 << len)-1;
-
-        end = len + irq;
-
-        for (; irq < end && subsrc; irq++) {
-                if (subsrc & 1)
-                        generic_handle_irq(irq);
-
-                subsrc >>= 1;
-        }
-}
-
-/* WDT/AC97 sub interrupts */
-
-static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
-}
-
-#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
-#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
-
-static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-
-static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
-}
-
-static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-
-static struct irq_chip s3c2416_irq_wdtac97 = {
-        .irq_mask       = s3c2416_irq_wdtac97_mask,
-        .irq_unmask     = s3c2416_irq_wdtac97_unmask,
-        .irq_ack        = s3c2416_irq_wdtac97_ack,
-};
-
-/* LCD sub interrupts */
-
-static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
-}
-
-#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
-#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
-
-static void s3c2416_irq_lcd_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-
-static void s3c2416_irq_lcd_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
-}
-
-static void s3c2416_irq_lcd_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-
-static struct irq_chip s3c2416_irq_lcd = {
-        .irq_mask       = s3c2416_irq_lcd_mask,
-        .irq_unmask     = s3c2416_irq_lcd_unmask,
-        .irq_ack        = s3c2416_irq_lcd_ack,
-};
-
-/* DMA sub interrupts */
-
-static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
-}
-
-#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
-#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
-
-
-static void s3c2416_irq_dma_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-
-static void s3c2416_irq_dma_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
-}
-
-static void s3c2416_irq_dma_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-
-static struct irq_chip s3c2416_irq_dma = {
-        .irq_mask       = s3c2416_irq_dma_mask,
-        .irq_unmask     = s3c2416_irq_dma_unmask,
-        .irq_ack        = s3c2416_irq_dma_ack,
-};
-
-/* UART3 sub interrupts */
-
-static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
-}
-
-#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
-#define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
-
-static void s3c2416_irq_uart3_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-
-static void s3c2416_irq_uart3_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
-}
-
-static void s3c2416_irq_uart3_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-
-static struct irq_chip s3c2416_irq_uart3 = {
-        .irq_mask       = s3c2416_irq_uart3_mask,
-        .irq_unmask     = s3c2416_irq_uart3_unmask,
-        .irq_ack        = s3c2416_irq_uart3_ack,
-};
-
-/* second interrupt register */
-
-static inline void s3c2416_irq_ack_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-
-        __raw_writel(bitval, S3C2416_SRCPND2);
-        __raw_writel(bitval, S3C2416_INTPND2);
-}
-
-static void s3c2416_irq_mask_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2416_INTMSK2);
-        mask |= bitval;
-        __raw_writel(mask, S3C2416_INTMSK2);
-}
-
-static void s3c2416_irq_unmask_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2416_INTMSK2);
-        mask &= ~bitval;
-        __raw_writel(mask, S3C2416_INTMSK2);
-}
-
-struct irq_chip s3c2416_irq_second = {
-        .irq_ack        = s3c2416_irq_ack_second,
-        .irq_mask       = s3c2416_irq_mask_second,
-        .irq_unmask     = s3c2416_irq_unmask_second,
-};
-
-
-/* IRQ initialisation code */
-
-static int s3c2416_add_sub(unsigned int base,
-                                   void (*demux)(unsigned int,
-                                                 struct irq_desc *),
-                                   struct irq_chip *chip,
-                                   unsigned int start, unsigned int end)
-{
-        unsigned int irqno;
-
-        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
-        irq_set_chained_handler(base, demux);
-
-        for (irqno = start; irqno <= end; irqno++) {
-                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static void s3c2416_irq_add_second(void)
-{
-        unsigned long pend;
-        unsigned long last;
-        int irqno;
-        int i;
-
-        /* first, clear all interrupts pending... */
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C2416_INTPND2);
-
-                if (pend == 0 || pend == last)
-                        break;
-
-                __raw_writel(pend, S3C2416_SRCPND2);
-                __raw_writel(pend, S3C2416_INTPND2);
-                printk(KERN_INFO "irq: clearing pending status %08x\n",
-                       (int)pend);
-                last = pend;
-        }
-
-        for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
-                switch (irqno) {
-                case IRQ_S3C2416_RESERVED2:
-                case IRQ_S3C2416_RESERVED3:
-                        /* no IRQ here */
-                        break;
-                default:
-                        irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
-                                                 handle_edge_irq);
-                        set_irq_flags(irqno, IRQF_VALID);
-                }
-        }
-}
-
-static int s3c2416_irq_add(struct device *dev,
-                                  struct subsys_interface *sif)
-{
-        printk(KERN_INFO "S3C2416: IRQ Support\n");
-
-        s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
-                        IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
-
-        s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
-                        &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
-
-        s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
-                        &s3c2416_irq_uart3,
-                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
-
-        s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
-                        &s3c2416_irq_wdtac97,
-                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
-
-        s3c2416_irq_add_second();
-
-        return 0;
-}
-
-static struct subsys_interface s3c2416_irq_interface = {
-        .name           = "s3c2416_irq",
-        .subsys         = &s3c2416_subsys,
-        .add_dev        = s3c2416_irq_add,
-};
-
-static int __init s3c2416_irq_init(void)
-{
-        return subsys_interface_register(&s3c2416_irq_interface);
-}
-
-arch_initcall(s3c2416_irq_init);
-
-#ifdef CONFIG_PM
-static struct sleep_save irq_save[] = {
-        SAVE_ITEM(S3C2416_INTMSK2),
-};
-
-int s3c2416_irq_suspend(void)
-{
-        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
-
-        return 0;
-}
-
-void s3c2416_irq_resume(void)
-{
-        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-}
-
-struct syscore_ops s3c2416_irq_syscore_ops = {
-        .suspend        = s3c2416_irq_suspend,
-        .resume         = s3c2416_irq_resume,
-};
-#endif
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
deleted file mode 100644
index 5e69109c0928..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* linux/arch/arm/mach-s3c2443/irq.c
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-
-static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
-{
-        unsigned int subsrc, submsk;
-        unsigned int end;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc  &= ~submsk;
-        subsrc >>= (irq - S3C2410_IRQSUB(0));
-        subsrc  &= (1 << len)-1;
-
-        end = len + irq;
-
-        for (; irq < end && subsrc; irq++) {
-                if (subsrc & 1)
-                        generic_handle_irq(irq);
-
-                subsrc >>= 1;
-        }
-}
-
-/* WDT/AC97 sub interrupts */
-
-static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
-}
-
-#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
-#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
-
-static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-
-static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
-}
-
-static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-
-static struct irq_chip s3c2443_irq_wdtac97 = {
-        .irq_mask       = s3c2443_irq_wdtac97_mask,
-        .irq_unmask     = s3c2443_irq_wdtac97_unmask,
-        .irq_ack        = s3c2443_irq_wdtac97_ack,
-};
-
-/* LCD sub interrupts */
-
-static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
-}
-
-#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
-#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
-
-static void s3c2443_irq_lcd_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-
-static void s3c2443_irq_lcd_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
-}
-
-static void s3c2443_irq_lcd_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-
-static struct irq_chip s3c2443_irq_lcd = {
-        .irq_mask       = s3c2443_irq_lcd_mask,
-        .irq_unmask     = s3c2443_irq_lcd_unmask,
-        .irq_ack        = s3c2443_irq_lcd_ack,
-};
-
-/* DMA sub interrupts */
-
-static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
-}
-
-#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
-#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
-
-static void s3c2443_irq_dma_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-
-static void s3c2443_irq_dma_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
-}
-
-static void s3c2443_irq_dma_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-
-static struct irq_chip s3c2443_irq_dma = {
-        .irq_mask       = s3c2443_irq_dma_mask,
-        .irq_unmask     = s3c2443_irq_dma_unmask,
-        .irq_ack        = s3c2443_irq_dma_ack,
-};
-
-/* UART3 sub interrupts */
-
-static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_RX3, 3);
-}
-
-#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
-#define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
-
-static void s3c2443_irq_uart3_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-
-static void s3c2443_irq_uart3_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
-}
-
-static void s3c2443_irq_uart3_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-
-static struct irq_chip s3c2443_irq_uart3 = {
-        .irq_mask       = s3c2443_irq_uart3_mask,
-        .irq_unmask     = s3c2443_irq_uart3_unmask,
-        .irq_ack        = s3c2443_irq_uart3_ack,
-};
-
-/* CAM sub interrupts */
-
-static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
-}
-
-#define INTMSK_CAM      (1UL << (IRQ_CAM - IRQ_EINT0))
-#define SUBMSK_CAM      INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
-
-static void s3c2443_irq_cam_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
-}
-
-static void s3c2443_irq_cam_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
-}
-
-static void s3c2443_irq_cam_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
-}
-
-static struct irq_chip s3c2443_irq_cam = {
-        .irq_mask       = s3c2443_irq_cam_mask,
-        .irq_unmask     = s3c2443_irq_cam_unmask,
-        .irq_ack        = s3c2443_irq_cam_ack,
-};
-
-/* IRQ initialisation code */
-
-static int s3c2443_add_sub(unsigned int base,
-                                   void (*demux)(unsigned int,
-                                                 struct irq_desc *),
-                                   struct irq_chip *chip,
-                                   unsigned int start, unsigned int end)
-{
-        unsigned int irqno;
-
-        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
-        irq_set_chained_handler(base, demux);
-
-        for (irqno = start; irqno <= end; irqno++) {
-                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static int s3c2443_irq_add(struct device *dev,
-                                  struct subsys_interface *sif)
-{
-        printk("S3C2443: IRQ Support\n");
-
-        s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
-                        IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
-
-        s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
-                        IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
-
-        s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
-                        &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
-
-        s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
-                        &s3c2443_irq_uart3,
-                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
-
-        s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
-                        &s3c2443_irq_wdtac97,
-                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
-
-        return 0;
-}
-
-static struct subsys_interface s3c2443_irq_interface = {
-        .name           = "s3c2443_irq",
-        .subsys         = &s3c2443_subsys,
-        .add_dev        = s3c2443_irq_add,
-};
-
-static int __init s3c2443_irq_init(void)
-{
-        return subsys_interface_register(&s3c2443_irq_interface);
-}
-
-arch_initcall(s3c2443_irq_init);
-
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
new file mode 100644
index 000000000000..cb9f5e011e73
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/irq.c
@@ -0,0 +1,822 @@
+/*
+ * S3C24XX IRQ handling
+ *
+ * Copyright (c) 2003-2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/irqdomain.h>
+
+#include <asm/mach/irq.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/cpu.h>
+#include <plat/regs-irqtype.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+
+#define S3C_IRQTYPE_NONE        0
+#define S3C_IRQTYPE_EINT        1
+#define S3C_IRQTYPE_EDGE        2
+#define S3C_IRQTYPE_LEVEL       3
+
+struct s3c_irq_data {
+        unsigned int type;
+        unsigned long parent_irq;
+
+        /* data gets filled during init */
+        struct s3c_irq_intc *intc;
+        unsigned long sub_bits;
+        struct s3c_irq_intc *sub_intc;
+};
+
+/*
+ * Sructure holding the controller data
+ * @reg_pending         register holding pending irqs
+ * @reg_intpnd          special register intpnd in main intc
+ * @reg_mask            mask register
+ * @domain              irq_domain of the controller
+ * @parent              parent controller for ext and sub irqs
+ * @irqs                irq-data, always s3c_irq_data[32]
+ */
+struct s3c_irq_intc {
+        void __iomem            *reg_pending;
+        void __iomem            *reg_intpnd;
+        void __iomem            *reg_mask;
+        struct irq_domain       *domain;
+        struct s3c_irq_intc     *parent;
+        struct s3c_irq_data     *irqs;
+};
+
+static void s3c_irq_mask(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
+        struct s3c_irq_data *parent_data;
+        unsigned long mask;
+        unsigned int irqno;
+
+        mask = __raw_readl(intc->reg_mask);
+        mask |= (1UL << data->hwirq);
+        __raw_writel(mask, intc->reg_mask);
+
+        if (parent_intc && irq_data->parent_irq) {
+                parent_data = &parent_intc->irqs[irq_data->parent_irq];
+
+                /* check to see if we need to mask the parent IRQ */
+                if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
+                        irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                        s3c_irq_mask(irq_get_irq_data(irqno));
+                }
+        }
+}
+
+static void s3c_irq_unmask(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
+        unsigned long mask;
+        unsigned int irqno;
+
+        mask = __raw_readl(intc->reg_mask);
+        mask &= ~(1UL << data->hwirq);
+        __raw_writel(mask, intc->reg_mask);
+
+        if (parent_intc && irq_data->parent_irq) {
+                irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                s3c_irq_unmask(irq_get_irq_data(irqno));
+        }
+}
+
+static inline void s3c_irq_ack(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        unsigned long bitval = 1UL << data->hwirq;
+
+        __raw_writel(bitval, intc->reg_pending);
+        if (intc->reg_intpnd)
+                __raw_writel(bitval, intc->reg_intpnd);
+}
+
+static int s3c_irqext_type_set(void __iomem *gpcon_reg,
+                               void __iomem *extint_reg,
+                               unsigned long gpcon_offset,
+                               unsigned long extint_offset,
+                               unsigned int type)
+{
+        unsigned long newvalue = 0, value;
+
+        /* Set the GPIO to external interrupt mode */
+        value = __raw_readl(gpcon_reg);
+        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
+        __raw_writel(value, gpcon_reg);
+
+        /* Set the external interrupt to pointed trigger type */
+        switch (type)
+        {
+                case IRQ_TYPE_NONE:
+                        pr_warn("No edge setting!\n");
+                        break;
+
+                case IRQ_TYPE_EDGE_RISING:
+                        newvalue = S3C2410_EXTINT_RISEEDGE;
+                        break;
+
+                case IRQ_TYPE_EDGE_FALLING:
+                        newvalue = S3C2410_EXTINT_FALLEDGE;
+                        break;
+
+                case IRQ_TYPE_EDGE_BOTH:
+                        newvalue = S3C2410_EXTINT_BOTHEDGE;
+                        break;
+
+                case IRQ_TYPE_LEVEL_LOW:
+                        newvalue = S3C2410_EXTINT_LOWLEV;
+                        break;
+
+                case IRQ_TYPE_LEVEL_HIGH:
+                        newvalue = S3C2410_EXTINT_HILEV;
+                        break;
+
+                default:
+                        pr_err("No such irq type %d", type);
+                        return -EINVAL;
+        }
+
+        value = __raw_readl(extint_reg);
+        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
+        __raw_writel(value, extint_reg);
+
+        return 0;
+}
+
+/* FIXME: make static when it's out of plat-samsung/irq.h */
+int s3c_irqext_type(struct irq_data *data, unsigned int type)
+{
+        void __iomem *extint_reg;
+        void __iomem *gpcon_reg;
+        unsigned long gpcon_offset, extint_offset;
+
+        if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
+                gpcon_reg = S3C2410_GPFCON;
+                extint_reg = S3C24XX_EXTINT0;
+                gpcon_offset = (data->hwirq) * 2;
+                extint_offset = (data->hwirq) * 4;
+        } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
+                gpcon_reg = S3C2410_GPGCON;
+                extint_reg = S3C24XX_EXTINT1;
+                gpcon_offset = (data->hwirq - 8) * 2;
+                extint_offset = (data->hwirq - 8) * 4;
+        } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
+                gpcon_reg = S3C2410_GPGCON;
+                extint_reg = S3C24XX_EXTINT2;
+                gpcon_offset = (data->hwirq - 8) * 2;
+                extint_offset = (data->hwirq - 16) * 4;
+        } else {
+                return -EINVAL;
+        }
+
+        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+                                   extint_offset, type);
+}
+
+static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
+{
+        void __iomem *extint_reg;
+        void __iomem *gpcon_reg;
+        unsigned long gpcon_offset, extint_offset;
+
+        if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
+                gpcon_reg = S3C2410_GPFCON;
+                extint_reg = S3C24XX_EXTINT0;
+                gpcon_offset = (data->hwirq) * 2;
+                extint_offset = (data->hwirq) * 4;
+        } else {
+                return -EINVAL;
+        }
+
+        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+                                   extint_offset, type);
+}
+
+struct irq_chip s3c_irq_chip = {
+        .name           = "s3c",
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake
+};
+
+struct irq_chip s3c_irq_level_chip = {
+        .name           = "s3c-level",
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_ack        = s3c_irq_ack,
+};
+
+static struct irq_chip s3c_irqext_chip = {
+        .name           = "s3c-ext",
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_ack        = s3c_irq_ack,
+        .irq_set_type   = s3c_irqext_type,
+        .irq_set_wake   = s3c_irqext_wake
+};
+
+static struct irq_chip s3c_irq_eint0t4 = {
+        .name           = "s3c-ext0",
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake,
+        .irq_set_type   = s3c_irqext0_type,
+};
+
+static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
+        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
+        struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
+        unsigned long src;
+        unsigned long msk;
+        unsigned int n;
+
+        chained_irq_enter(chip, desc);
+
+        src = __raw_readl(sub_intc->reg_pending);
+        msk = __raw_readl(sub_intc->reg_mask);
+
+        src &= ~msk;
+        src &= irq_data->sub_bits;
+
+        while (src) {
+                n = __ffs(src);
+                src &= ~(1 << n);
+                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
+        }
+
+        chained_irq_exit(chip, desc);
+}
+
+#ifdef CONFIG_FIQ
+/**
+ * s3c24xx_set_fiq - set the FIQ routing
+ * @irq: IRQ number to route to FIQ on processor.
+ * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
+ *
+ * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
+ * @on is true, the @irq is checked to see if it can be routed and the
+ * interrupt controller updated to route the IRQ. If @on is false, the FIQ
+ * routing is cleared, regardless of which @irq is specified.
+ */
+int s3c24xx_set_fiq(unsigned int irq, bool on)
+{
+        u32 intmod;
+        unsigned offs;
+
+        if (on) {
+                offs = irq - FIQ_START;
+                if (offs > 31)
+                        return -EINVAL;
+
+                intmod = 1 << offs;
+        } else {
+                intmod = 0;
+        }
+
+        __raw_writel(intmod, S3C2410_INTMOD);
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
+#endif
+
+static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        struct s3c_irq_intc *intc = h->host_data;
+        struct s3c_irq_data *irq_data = &intc->irqs[hw];
+        struct s3c_irq_intc *parent_intc;
+        struct s3c_irq_data *parent_irq_data;
+        unsigned int irqno;
+
+        if (!intc) {
+                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
+                return -EINVAL;
+        }
+
+        if (!irq_data) {
+                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
+                return -EINVAL;
+        }
+
+        /* attach controller pointer to irq_data */
+        irq_data->intc = intc;
+
+        /* set handler and flags */
+        switch (irq_data->type) {
+        case S3C_IRQTYPE_NONE:
+                return 0;
+        case S3C_IRQTYPE_EINT:
+                if (irq_data->parent_irq)
+                        irq_set_chip_and_handler(virq, &s3c_irqext_chip,
+                                                 handle_edge_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
+                                                 handle_edge_irq);
+                break;
+        case S3C_IRQTYPE_EDGE:
+                if (irq_data->parent_irq ||
+                    intc->reg_pending == S3C2416_SRCPND2)
+                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                                 handle_edge_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
+                                                 handle_edge_irq);
+                break;
+        case S3C_IRQTYPE_LEVEL:
+                if (irq_data->parent_irq)
+                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                                 handle_level_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
+                                                 handle_level_irq);
+                break;
+        default:
+                pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
+                return -EINVAL;
+        }
+        set_irq_flags(virq, IRQF_VALID);
+
+        if (irq_data->parent_irq) {
+                parent_intc = intc->parent;
+                if (!parent_intc) {
+                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
+                               hw);
+                        goto err;
+                }
+
+                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
+                if (!irq_data) {
+                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
+                               hw);
+                        goto err;
+                }
+
+                parent_irq_data->sub_intc = intc;
+                parent_irq_data->sub_bits |= (1UL << hw);
+
+                /* attach the demuxer to the parent irq */
+                irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                if (!irqno) {
+                        pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
+                               irq_data->parent_irq);
+                        goto err;
+                }
+                irq_set_chained_handler(irqno, s3c_irq_demux);
+        }
+
+        return 0;
+
+err:
+        set_irq_flags(virq, 0);
+
+        /* the only error can result from bad mapping data*/
+        return -EINVAL;
+}
+
+static struct irq_domain_ops s3c24xx_irq_ops = {
+        .map = s3c24xx_irq_map,
+        .xlate = irq_domain_xlate_twocell,
+};
+
+static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
+{
+        void __iomem *reg_source;
+        unsigned long pend;
+        unsigned long last;
+        int i;
+
+        /* if intpnd is set, read the next pending irq from there */
+        reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
+
+        last = 0;
+        for (i = 0; i < 4; i++) {
+                pend = __raw_readl(reg_source);
+
+                if (pend == 0 || pend == last)
+                        break;
+
+                __raw_writel(pend, intc->reg_pending);
+                if (intc->reg_intpnd)
+                        __raw_writel(pend, intc->reg_intpnd);
+
+                pr_info("irq: clearing pending status %08x\n", (int)pend);
+                last = pend;
+        }
+}
+
+struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
+                                       struct s3c_irq_data *irq_data,
+                                       struct s3c_irq_intc *parent,
+                                       unsigned long address)
+{
+        struct s3c_irq_intc *intc;
+        void __iomem *base = (void *)0xf6000000; /* static mapping */
+        int irq_num;
+        int irq_start;
+        int irq_offset;
+        int ret;
+
+        intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
+        if (!intc)
+                return ERR_PTR(-ENOMEM);
+
+        intc->irqs = irq_data;
+
+        if (parent)
+                intc->parent = parent;
+
+        /* select the correct data for the controller.
+         * Need to hard code the irq num start and offset
+         * to preserve the static mapping for now
+         */
+        switch (address) {
+        case 0x4a000000:
+                pr_debug("irq: found main intc\n");
+                intc->reg_pending = base;
+                intc->reg_mask = base + 0x08;
+                intc->reg_intpnd = base + 0x10;
+                irq_num = 32;
+                irq_start = S3C2410_IRQ(0);
+                irq_offset = 0;
+                break;
+        case 0x4a000018:
+                pr_debug("irq: found subintc\n");
+                intc->reg_pending = base + 0x18;
+                intc->reg_mask = base + 0x1c;
+                irq_num = 29;
+                irq_start = S3C2410_IRQSUB(0);
+                irq_offset = 0;
+                break;
+        case 0x4a000040:
+                pr_debug("irq: found intc2\n");
+                intc->reg_pending = base + 0x40;
+                intc->reg_mask = base + 0x48;
+                intc->reg_intpnd = base + 0x50;
+                irq_num = 8;
+                irq_start = S3C2416_IRQ(0);
+                irq_offset = 0;
+                break;
+        case 0x560000a4:
+                pr_debug("irq: found eintc\n");
+                base = (void *)0xfd000000;
+
+                intc->reg_mask = base + 0xa4;
+                intc->reg_pending = base + 0x08;
+                irq_num = 20;
+                irq_start = S3C2410_IRQ(32);
+                irq_offset = 4;
+                break;
+        default:
+                pr_err("irq: unsupported controller address\n");
+                ret = -EINVAL;
+                goto err;
+        }
+
+        /* now that all the data is complete, init the irq-domain */
+        s3c24xx_clear_intc(intc);
+        intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
+                                             irq_offset, &s3c24xx_irq_ops,
+                                             intc);
+        if (!intc->domain) {
+                pr_err("irq: could not create irq-domain\n");
+                ret = -EINVAL;
+                goto err;
+        }
+
+        return intc;
+
+err:
+        kfree(intc);
+        return ERR_PTR(ret);
+}
+
+/* s3c24xx_init_irq
+ *
+ * Initialise S3C2410 IRQ system
+*/
+
+static struct s3c_irq_data init_base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_eint[32] = {
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
+};
+
+static struct s3c_irq_data init_subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+};
+
+void __init s3c24xx_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+
+        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+
+        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+}
+
+#ifdef CONFIG_CPU_S3C2416
+static struct s3c_irq_data init_s3c2416base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_NONE, },
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2416subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+
+static struct s3c_irq_data init_s3c2416_second[32] = {
+        { .type = S3C_IRQTYPE_EDGE }, /* 2D */
+        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
+        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
+        { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
+        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
+};
+
+void __init s3c2416_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+
+        pr_info("S3C2416: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+
+        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
+
+        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
+}
+
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+static struct s3c_irq_data init_s3c2443base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+
+static struct s3c_irq_data init_s3c2443subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+
+void __init s3c2443_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+
+        pr_info("S3C2443: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+
+        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
+}
+#endif
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index f4ad99c1e476..0e0279e79150 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -237,6 +237,6 @@ MACHINE_START(AML_M5900, "AML_M5900")
         .map_io         = amlm5900_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = amlm5900_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 1ee8c4638743..bb595f15ce36 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -28,17 +28,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/anubis-map.h>
-#include <mach/anubis-irq.h>
-#include <mach/anubis-cpld.h>
-
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -55,8 +50,9 @@
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
 
-#include "simtec.h"
+#include "anubis.h"
 #include "common.h"
+#include "simtec.h"
 
 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
 
@@ -237,7 +233,7 @@ static struct pata_platform_info anubis_ide_platdata = {
 static struct resource anubis_ide0_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
         [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
-        [3] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
 };
 
 static struct platform_device anubis_device_ide0 = {
@@ -254,7 +250,7 @@ static struct platform_device anubis_device_ide0 = {
 static struct resource anubis_ide1_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
         [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
 };
 
 static struct platform_device anubis_device_ide1 = {
@@ -279,7 +275,7 @@ static struct ax_plat_data anubis_asix_platdata = {
 
 static struct resource anubis_asix_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
-        [1] = DEFINE_RES_IRQ(IRQ_ASIX),
+        [1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
 };
 
 static struct platform_device anubis_device_asix = {
@@ -448,6 +444,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
         .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 00381fe5de32..b4bc60c78ebb 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -14,6 +14,7 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
 #include <linux/timer.h>
@@ -34,7 +35,6 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -210,6 +210,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
         .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 6a30ce7e4aa7..ca6618081041 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -24,48 +24,41 @@
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/serial_8250.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <linux/platform_data/hwmon-s3c.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 
 #include <net/ax88796.h>
 
+#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
-#include <mach/bast-cpld.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
 #include <asm/mach-types.h>
 
-//#include <asm/debug-ll.h>
-#include <plat/regs-serial.h>
+#include <mach/fb.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 
-#include <linux/platform_data/hwmon-s3c.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/fb.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/partitions.h>
-
-#include <linux/serial_8250.h>
-
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
+#include <plat/devs.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/regs-serial.h>
 
-#include "simtec.h"
+#include "bast.h"
 #include "common.h"
+#include "simtec.h"
 
 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
 
@@ -312,7 +305,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
 static struct resource bast_dm9k_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
                                         | IORESOURCE_IRQ_HIGHLEVEL),
 };
 
@@ -343,7 +336,7 @@ static struct platform_device bast_device_dm9k = {
 static struct plat_serial8250_port bast_sio_data[] = {
         [0] = {
                 .mapbase        = SERIAL_BASE + 0x2f8,
-                .irq            = IRQ_PCSERIAL1,
+                .irq            = BAST_IRQ_PCSERIAL1,
                 .flags          = SERIAL_FLAGS,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -351,7 +344,7 @@ static struct plat_serial8250_port bast_sio_data[] = {
         },
         [1] = {
                 .mapbase        = SERIAL_BASE + 0x3f8,
-                .irq            = IRQ_PCSERIAL2,
+                .irq            = BAST_IRQ_PCSERIAL2,
                 .flags          = SERIAL_FLAGS,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -390,7 +383,7 @@ static struct ax_plat_data bast_asix_platdata = {
 static struct resource bast_asix_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
-        [2] = DEFINE_RES_IRQ(IRQ_ASIX),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
 };
 
 static struct platform_device bast_device_asix = {
@@ -612,6 +605,6 @@ MACHINE_START(BAST, "Simtec-BAST")
         .map_io         = bast_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = bast_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 973b87ca87f4..a25e8c5a7b4c 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/arm/mach-s3c2442/mach-gta02.c
- *
  * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner.
  *
  * Copyright (C) 2006-2009 by Openmoko, Inc.
@@ -23,7 +21,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
  */
 
 #include <linux/kernel.h>
@@ -34,62 +31,59 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/workqueue.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/s3c24xx.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
 
 #include <linux/mmc/host.h>
 
+#include <linux/mfd/pcf50633/adc.h>
+#include <linux/mfd/pcf50633/backlight.h>
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/mfd/pcf50633/pmic.h>
+
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
-#include <linux/io.h>
 
-#include <linux/i2c.h>
 #include <linux/regulator/machine.h>
 
-#include <linux/mfd/pcf50633/core.h>
-#include <linux/mfd/pcf50633/mbc.h>
-#include <linux/mfd/pcf50633/adc.h>
-#include <linux/mfd/pcf50633/gpio.h>
-#include <linux/mfd/pcf50633/pmic.h>
-#include <linux/mfd/pcf50633/backlight.h>
-
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/s3c24xx.h>
 
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/irq.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
 #include <mach/fb.h>
-
-#include <linux/platform_data/usb-ohci-s3c2410.h>
-#include <mach/regs-mem.h>
 #include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
 
-#include <mach/gta02.h>
-
-#include <plat/regs-serial.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/pm.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/devs.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <plat/pm.h>
+#include <plat/regs-serial.h>
 
 #include "common.h"
+#include "gta02.h"
 
 static struct pcf50633 *gta02_pcf;
 
@@ -595,6 +589,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         .map_io         = gta02_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = gta02_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index b23dd1b106e8..79bc0830d740 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-h1940.c
- *
+/*
  * Copyright (c) 2003-2005 Simtec Electronics
  *   Ben Dooks <ben@simtec.co.uk>
  *
@@ -37,40 +36,36 @@
 #include <linux/mmc/host.h>
 #include <linux/export.h>
 
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <plat/regs-serial.h>
-#include <mach/regs-lcd.h>
-#include <mach/regs-clock.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 
-#include <mach/regs-gpio.h>
-#include <mach/gpio-fns.h>
-#include <mach/gpio-nrs.h>
+#include <sound/uda1380.h>
 
-#include <mach/h1940.h>
-#include <mach/h1940-latch.h>
 #include <mach/fb.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <linux/platform_data/i2c-s3c2410.h>
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
-#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <plat/regs-serial.h>
 
-#include <sound/uda1380.h>
 
 #include "common.h"
+#include "h1940.h"
 
 #define H1940_LATCH             ((void __force __iomem *)0xF8000000)
 
@@ -746,6 +741,6 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .reserve        = h1940_reserve,
         .init_irq       = h1940_init_irq,
         .init_machine   = h1940_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index c9954e26b492..54e83c1f780c 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -35,9 +35,7 @@
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/fb.h>
 
@@ -56,6 +54,8 @@
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 
+#include "s3c2412-power.h"
+
 static struct map_desc jive_iodesc[] __initdata = {
 };
 
@@ -661,6 +661,6 @@ MACHINE_START(JIVE, "JIVE")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index a31d5b83e5f7..2865e5919f2c 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -40,7 +40,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/irqs.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
@@ -688,6 +687,6 @@ MACHINE_START(MINI2440, "MINI2440")
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
         .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index c53a9bfe1417..d9d04b240295 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -589,7 +589,7 @@ MACHINE_START(N30, "Acer-N30")
                                 Ben Dooks <ben-linux@fluff.org>
         */
         .atag_offset    = 0x100,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .init_machine   = n30_init,
         .init_irq       = s3c24xx_init_irq,
         .map_io         = n30_map_io,
@@ -600,7 +600,7 @@ MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
         .atag_offset    = 0x100,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .init_machine   = n30_init,
         .init_irq       = s3c24xx_init_irq,
         .map_io         = n30_map_io,
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index a2b92b0898e2..a454e2461860 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -153,6 +153,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
         .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index c52100ef2322..ae2cbdf3e3ca 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2440/mach-osiris.c
- *
+/*
  * Copyright (c) 2005-2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
@@ -26,22 +25,12 @@
 
 #include <linux/i2c/tps65010.h>
 
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-
-#include <mach/osiris-map.h>
-#include <mach/osiris-cpld.h>
-
-#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/mach-types.h>
 
-#include <plat/cpu-freq.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
-#include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
@@ -50,12 +39,20 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
-#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
 #include "common.h"
+#include "osiris.h"
+#include "regs-mem.h"
 
 /* onboard perihperal map */
 
@@ -429,6 +426,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         .map_io         = osiris_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = osiris_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index bca39f0232b3..40a47d6c6a85 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-otom.c
+/*
  *
  * Copyright (c) 2004 Nex Vision
  *   Guillaume GOURAT <guillaume.gourat@nexvision.fr>
@@ -6,7 +6,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
  */
 
 #include <linux/kernel.h>
@@ -19,26 +18,25 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
+#include <linux/platform_data/i2c-s3c2410.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/otom-map.h>
-
 #include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
-#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/regs-serial.h>
+#include <plat/s3c2410.h>
 
 #include "common.h"
+#include "otom.h"
 
 static struct map_desc otom11_iodesc[] __initdata = {
   /* Device area */
@@ -118,6 +116,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
         .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 7b6ba13d7285..56175f0941b1 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -343,6 +343,6 @@ MACHINE_START(QT2410, "QT2410")
         .map_io         = qt2410_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = qt2410_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 0606f2faaa5c..1f9ba2ae5288 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
- *
+/*
  * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
  * Copyright (c) 2007-2010 Vasily Khoruzhick
  *
@@ -37,31 +36,31 @@
 
 #include <linux/mmc/host.h>
 
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
 
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+
+#include <sound/uda1380.h>
+
+#include <mach/fb.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/h1940.h>
-#include <mach/fb.h>
 
 #include <plat/clock.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-iic.h>
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-
-#include <sound/uda1380.h>
+#include <plat/regs-iic.h>
+#include <plat/regs-serial.h>
 
 #include "common.h"
+#include "h1940.h"
 
 #define LCD_PWM_PERIOD 192960
 #define LCD_PWM_DUTY 127353
@@ -814,6 +813,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .reserve        = rx1950_reserve,
         .init_irq = s3c24xx_init_irq,
         .init_machine = rx1950_init_machine,
-        .timer = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index dacbb9a2122a..f20418a2fb1b 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -31,27 +31,27 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <plat/regs-serial.h>
+#include <mach/fb.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 
-#include <mach/h1940.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <mach/fb.h>
-
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
 #include <plat/pm.h>
+#include <plat/regs-serial.h>
 
 #include "common.h"
+#include "h1940.h"
 
 static struct map_desc rx3715_iodesc[] __initdata = {
         /* dump ISA space somewhere unused */
@@ -212,6 +212,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .reserve        = rx3715_reserve,
         .init_irq       = rx3715_init_irq,
         .init_machine   = rx3715_init_machine,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index 82796b97cb04..e184bfa9613a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -117,6 +117,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         .map_io         = smdk2410_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = smdk2410_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index ce99fd8bbbc5..86d7847c9d45 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -37,7 +37,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 
-#include <mach/idle.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
@@ -133,7 +132,7 @@ MACHINE_START(S3C2413, "S3C2413")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -145,7 +144,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -157,6 +156,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index f30d7fccbfee..ebb2e61f3d07 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -39,7 +39,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/regs-s3c2443-clock.h>
 
-#include <mach/idle.h>
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
@@ -251,9 +250,9 @@ MACHINE_START(SMDK2416, "SMDK2416")
         /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2416_init_irq,
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index b7ff882c6ce6..08cc38c8a4ae 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -35,7 +35,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
@@ -182,6 +181,6 @@ MACHINE_START(S3C2440, "SMDK2440")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 2568656f046f..fc65d74d3c73 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -35,7 +35,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
@@ -141,9 +140,9 @@ MACHINE_START(SMDK2443, "SMDK2443")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2443_init_irq,
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 495bf5cf52e9..24b3d79e7b2c 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -149,6 +149,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .map_io         = tct_hammer_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = tct_hammer_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 14d5b12e388c..ec42d1e4e465 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
- *
+/*
  * Copyright (c) 2003-2008 Simtec Electronics
  *   Ben Dooks <ben@simtec.co.uk>
  *
@@ -32,27 +31,25 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/bast-map.h>
-#include <mach/vr1000-map.h>
-#include <mach/vr1000-irq.h>
-#include <mach/vr1000-cpld.h>
-
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
 #include <linux/platform_data/leds-s3c24xx.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
 
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/devs.h>
+#include <plat/regs-serial.h>
 
-#include "simtec.h"
+#include "bast.h"
 #include "common.h"
+#include "simtec.h"
+#include "vr1000.h"
 
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -143,7 +140,7 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
 static struct plat_serial8250_port serial_platform_data[] = {
         [0] = {
                 .mapbase        = VR1000_SERIAL_MAPBASE(0),
-                .irq            = IRQ_VR1000_SERIAL + 0,
+                .irq            = VR1000_IRQ_SERIAL + 0,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -151,7 +148,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         },
         [1] = {
                 .mapbase        = VR1000_SERIAL_MAPBASE(1),
-                .irq            = IRQ_VR1000_SERIAL + 1,
+                .irq            = VR1000_IRQ_SERIAL + 1,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -159,7 +156,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         },
         [2] = {
                 .mapbase        = VR1000_SERIAL_MAPBASE(2),
-                .irq            = IRQ_VR1000_SERIAL + 2,
+                .irq            = VR1000_IRQ_SERIAL + 2,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -167,7 +164,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         },
         [3] = {
                 .mapbase        = VR1000_SERIAL_MAPBASE(3),
-                .irq            = IRQ_VR1000_SERIAL + 3,
+                .irq            = VR1000_IRQ_SERIAL + 3,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -189,14 +186,14 @@ static struct platform_device serial_device = {
 static struct resource vr1000_dm9k0_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4),
         [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000A, 1, NULL, IORESOURCE_IRQ \
                                                 | IORESOURCE_IRQ_HIGHLEVEL),
 };
 
 static struct resource vr1000_dm9k1_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4),
         [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000N, 1, NULL, IORESOURCE_IRQ \
                                                 | IORESOURCE_IRQ_HIGHLEVEL),
 };
 
@@ -357,6 +354,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
         .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index f1d44ae11833..3e2bfddc9df1 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -36,7 +36,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 
-#include <mach/idle.h>
 #include <mach/fb.h>
 
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -161,6 +160,6 @@ MACHINE_START(VSTMS, "VSTMS")
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h b/arch/arm/mach-s3c24xx/osiris.h
index 17380f848428..b8d56074abac 100644
--- a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
+++ b/arch/arm/mach-s3c24xx/osiris.h
@@ -1,9 +1,9 @@
-/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
- *
+/*
  * Copyright 2005 Simtec Electronics
  *      http://www.simtec.co.uk/products/
  *      Ben Dooks <ben@simtec.co.uk>
  *
+ * OSIRIS - CPLD control constants
  * OSIRIS - Memory map definitions
  *
  * This program is free software; you can redistribute it and/or modify
@@ -11,10 +11,21 @@
  * published by the Free Software Foundation.
 */
 
-/* needs arch/map.h including with this */
+#ifndef __MACH_S3C24XX_OSIRIS_H
+#define __MACH_S3C24XX_OSIRIS_H __FILE__
+
+/* CTRL0 - NAND WP control */
+
+#define OSIRIS_CTRL0_NANDSEL            (0x3)
+#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
+#define OSIRIS_CTRL0_PCMCIA             (1<<4)
+#define OSIRIS_CTRL0_FIX8               (1<<5)
+#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
+#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
+
+#define OSIRIS_CTRL1_FIX8               (1<<0)
 
-#ifndef __ASM_ARCH_OSIRISMAP_H
-#define __ASM_ARCH_OSIRISMAP_H
+#define OSIRIS_ID_REVMASK               (0x7)
 
 /* start peripherals off after the S3C2410 */
 
@@ -39,4 +50,4 @@
 #define OSIRIS_VA_IDREG         OSIRIS_IOADDR(0x00700000)
 #define OSIRIS_PA_IDREG         (OSIRIS_PA_CPLD + (7<<23))
 
-#endif /* __ASM_ARCH_OSIRISMAP_H */
+#endif /* __MACH_S3C24XX_OSIRIS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/otom-map.h b/arch/arm/mach-s3c24xx/otom.h
index f9277a52c145..321b7be1c0f7 100644
--- a/arch/arm/mach-s3c24xx/include/mach/otom-map.h
+++ b/arch/arm/mach-s3c24xx/otom.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/otom-map.h
- *
+/*
  * (c) 2005 Guillaume GOURAT / NexVision
  *          guillaume.gourat@nexvision.fr
  *
@@ -10,21 +9,20 @@
  * published by the Free Software Foundation.
 */
 
-/* needs arch/map.h including with this */
-
-/* ok, we've used up to 0x01300000, now we need to find space for the
+/*
+ * ok, we've used up to 0x01300000, now we need to find space for the
  * peripherals that live in the nGCS[x] areas, which are quite numerous
  * in their space.
  */
 
-#ifndef __ASM_ARCH_OTOMMAP_H
-#define __ASM_ARCH_OTOMMAP_H
+#ifndef __MACH_S3C24XX_OTOM_H
+#define __MACH_S3C24XX_OTOM_H __FILE__
 
-#define OTOM_PA_CS8900A_BASE       (S3C2410_CS3 + 0x01000000)   /* nGCS3 +0x01000000 */
-#define OTOM_VA_CS8900A_BASE       S3C2410_ADDR(0x04000000)             /* 0xF4000000 */
+#define OTOM_PA_CS8900A_BASE    (S3C2410_CS3 + 0x01000000)      /* nGCS3 +0x01000000 */
+#define OTOM_VA_CS8900A_BASE    S3C2410_ADDR(0x04000000)        /* 0xF4000000 */
 
 /* physical offset addresses for the peripherals */
 
-#define OTOM_PA_FLASH0_BASE        (S3C2410_CS0)                                /* Bank 0 */
+#define OTOM_PA_FLASH0_BASE     (S3C2410_CS0)
 
-#endif /* __ASM_ARCH_OTOMMAP_H */
+#endif /* __MACH_S3C24XX_OTOM_H */
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
new file mode 100644
index 000000000000..dcf3420a3271
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2410 CPU PLL tables
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table pll_vals_12MHz[] = {
+    { .frequency = 34000000,  .index = PLLVAL(82, 2, 3),   },
+    { .frequency = 45000000,  .index = PLLVAL(82, 1, 3),   },
+    { .frequency = 51000000,  .index = PLLVAL(161, 3, 3),  },
+    { .frequency = 48000000,  .index = PLLVAL(120, 2, 3),  },
+    { .frequency = 56000000,  .index = PLLVAL(142, 2, 3),  },
+    { .frequency = 68000000,  .index = PLLVAL(82, 2, 2),   },
+    { .frequency = 79000000,  .index = PLLVAL(71, 1, 2),   },
+    { .frequency = 85000000,  .index = PLLVAL(105, 2, 2),  },
+    { .frequency = 90000000,  .index = PLLVAL(112, 2, 2),  },
+    { .frequency = 101000000, .index = PLLVAL(127, 2, 2),  },
+    { .frequency = 113000000, .index = PLLVAL(105, 1, 2),  },
+    { .frequency = 118000000, .index = PLLVAL(150, 2, 2),  },
+    { .frequency = 124000000, .index = PLLVAL(116, 1, 2),  },
+    { .frequency = 135000000, .index = PLLVAL(82, 2, 1),   },
+    { .frequency = 147000000, .index = PLLVAL(90, 2, 1),   },
+    { .frequency = 152000000, .index = PLLVAL(68, 1, 1),   },
+    { .frequency = 158000000, .index = PLLVAL(71, 1, 1),   },
+    { .frequency = 170000000, .index = PLLVAL(77, 1, 1),   },
+    { .frequency = 180000000, .index = PLLVAL(82, 1, 1),   },
+    { .frequency = 186000000, .index = PLLVAL(85, 1, 1),   },
+    { .frequency = 192000000, .index = PLLVAL(88, 1, 1),   },
+    { .frequency = 203000000, .index = PLLVAL(161, 3, 1),  },
+
+    /* 2410A extras */
+
+    { .frequency = 210000000, .index = PLLVAL(132, 2, 1),  },
+    { .frequency = 226000000, .index = PLLVAL(105, 1, 1),  },
+    { .frequency = 266000000, .index = PLLVAL(125, 1, 1),  },
+    { .frequency = 268000000, .index = PLLVAL(126, 1, 1),  },
+    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
+};
+
+static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
+{
+        return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
+}
+
+static struct subsys_interface s3c2410_plls_interface = {
+        .name           = "s3c2410_plls",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_plls_add,
+};
+
+static int __init s3c2410_pll_init(void)
+{
+        return subsys_interface_register(&s3c2410_plls_interface);
+
+}
+arch_initcall(s3c2410_pll_init);
+
+static struct subsys_interface s3c2410a_plls_interface = {
+        .name           = "s3c2410a_plls",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410_plls_add,
+};
+
+static int __init s3c2410a_pll_init(void)
+{
+        return subsys_interface_register(&s3c2410a_plls_interface);
+}
+arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
new file mode 100644
index 000000000000..673781758319
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
+        { .frequency = 75000000,        .index = PLLVAL(0x75, 3, 3),  },        /* FVco 600.000000 */
+        { .frequency = 80000000,        .index = PLLVAL(0x98, 4, 3),  },        /* FVco 640.000000 */
+        { .frequency = 90000000,        .index = PLLVAL(0x70, 2, 3),  },        /* FVco 720.000000 */
+        { .frequency = 100000000,       .index = PLLVAL(0x5c, 1, 3),  },        /* FVco 800.000000 */
+        { .frequency = 110000000,       .index = PLLVAL(0x66, 1, 3),  },        /* FVco 880.000000 */
+        { .frequency = 120000000,       .index = PLLVAL(0x70, 1, 3),  },        /* FVco 960.000000 */
+        { .frequency = 150000000,       .index = PLLVAL(0x75, 3, 2),  },        /* FVco 600.000000 */
+        { .frequency = 160000000,       .index = PLLVAL(0x98, 4, 2),  },        /* FVco 640.000000 */
+        { .frequency = 170000000,       .index = PLLVAL(0x4d, 1, 2),  },        /* FVco 680.000000 */
+        { .frequency = 180000000,       .index = PLLVAL(0x70, 2, 2),  },        /* FVco 720.000000 */
+        { .frequency = 190000000,       .index = PLLVAL(0x57, 1, 2),  },        /* FVco 760.000000 */
+        { .frequency = 200000000,       .index = PLLVAL(0x5c, 1, 2),  },        /* FVco 800.000000 */
+        { .frequency = 210000000,       .index = PLLVAL(0x84, 2, 2),  },        /* FVco 840.000000 */
+        { .frequency = 220000000,       .index = PLLVAL(0x66, 1, 2),  },        /* FVco 880.000000 */
+        { .frequency = 230000000,       .index = PLLVAL(0x6b, 1, 2),  },        /* FVco 920.000000 */
+        { .frequency = 240000000,       .index = PLLVAL(0x70, 1, 2),  },        /* FVco 960.000000 */
+        { .frequency = 300000000,       .index = PLLVAL(0x75, 3, 1),  },        /* FVco 600.000000 */
+        { .frequency = 310000000,       .index = PLLVAL(0x93, 4, 1),  },        /* FVco 620.000000 */
+        { .frequency = 320000000,       .index = PLLVAL(0x98, 4, 1),  },        /* FVco 640.000000 */
+        { .frequency = 330000000,       .index = PLLVAL(0x66, 2, 1),  },        /* FVco 660.000000 */
+        { .frequency = 340000000,       .index = PLLVAL(0x4d, 1, 1),  },        /* FVco 680.000000 */
+        { .frequency = 350000000,       .index = PLLVAL(0xa7, 4, 1),  },        /* FVco 700.000000 */
+        { .frequency = 360000000,       .index = PLLVAL(0x70, 2, 1),  },        /* FVco 720.000000 */
+        { .frequency = 370000000,       .index = PLLVAL(0xb1, 4, 1),  },        /* FVco 740.000000 */
+        { .frequency = 380000000,       .index = PLLVAL(0x57, 1, 1),  },        /* FVco 760.000000 */
+        { .frequency = 390000000,       .index = PLLVAL(0x7a, 2, 1),  },        /* FVco 780.000000 */
+        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
+};
+
+static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        if (xtal == 12000000) {
+                printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_12,
+                                           ARRAY_SIZE(s3c2440_plls_12));
+        }
+
+        return 0;
+}
+
+static struct subsys_interface s3c2440_plls12_interface = {
+        .name           = "s3c2440_plls12",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_plls12_add,
+};
+
+static int __init s3c2440_pll_12mhz(void)
+{
+        return subsys_interface_register(&s3c2440_plls12_interface);
+
+}
+arch_initcall(s3c2440_pll_12mhz);
+
+static struct subsys_interface s3c2442_plls12_interface = {
+        .name           = "s3c2442_plls12",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_plls12_add,
+};
+
+static int __init s3c2442_pll_12mhz(void)
+{
+        return subsys_interface_register(&s3c2442_plls12_interface);
+
+}
+arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
new file mode 100644
index 000000000000..debfa106289b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
+        { .frequency = 78019200,        .index = PLLVAL(121, 5, 3),     },      /* FVco 624.153600 */
+        { .frequency = 84067200,        .index = PLLVAL(131, 5, 3),     },      /* FVco 672.537600 */
+        { .frequency = 90115200,        .index = PLLVAL(141, 5, 3),     },      /* FVco 720.921600 */
+        { .frequency = 96163200,        .index = PLLVAL(151, 5, 3),     },      /* FVco 769.305600 */
+        { .frequency = 102135600,       .index = PLLVAL(185, 6, 3),     },      /* FVco 817.084800 */
+        { .frequency = 108259200,       .index = PLLVAL(171, 5, 3),     },      /* FVco 866.073600 */
+        { .frequency = 114307200,       .index = PLLVAL(127, 3, 3),     },      /* FVco 914.457600 */
+        { .frequency = 120234240,       .index = PLLVAL(134, 3, 3),     },      /* FVco 961.873920 */
+        { .frequency = 126161280,       .index = PLLVAL(141, 3, 3),     },      /* FVco 1009.290240 */
+        { .frequency = 132088320,       .index = PLLVAL(148, 3, 3),     },      /* FVco 1056.706560 */
+        { .frequency = 138015360,       .index = PLLVAL(155, 3, 3),     },      /* FVco 1104.122880 */
+        { .frequency = 144789120,       .index = PLLVAL(163, 3, 3),     },      /* FVco 1158.312960 */
+        { .frequency = 150100363,       .index = PLLVAL(187, 9, 2),     },      /* FVco 600.401454 */
+        { .frequency = 156038400,       .index = PLLVAL(121, 5, 2),     },      /* FVco 624.153600 */
+        { .frequency = 162086400,       .index = PLLVAL(126, 5, 2),     },      /* FVco 648.345600 */
+        { .frequency = 168134400,       .index = PLLVAL(131, 5, 2),     },      /* FVco 672.537600 */
+        { .frequency = 174048000,       .index = PLLVAL(177, 7, 2),     },      /* FVco 696.192000 */
+        { .frequency = 180230400,       .index = PLLVAL(141, 5, 2),     },      /* FVco 720.921600 */
+        { .frequency = 186278400,       .index = PLLVAL(124, 4, 2),     },      /* FVco 745.113600 */
+        { .frequency = 192326400,       .index = PLLVAL(151, 5, 2),     },      /* FVco 769.305600 */
+        { .frequency = 198132480,       .index = PLLVAL(109, 3, 2),     },      /* FVco 792.529920 */
+        { .frequency = 204271200,       .index = PLLVAL(185, 6, 2),     },      /* FVco 817.084800 */
+        { .frequency = 210268800,       .index = PLLVAL(141, 4, 2),     },      /* FVco 841.075200 */
+        { .frequency = 216518400,       .index = PLLVAL(171, 5, 2),     },      /* FVco 866.073600 */
+        { .frequency = 222264000,       .index = PLLVAL(97, 2, 2),      },      /* FVco 889.056000 */
+        { .frequency = 228614400,       .index = PLLVAL(127, 3, 2),     },      /* FVco 914.457600 */
+        { .frequency = 234259200,       .index = PLLVAL(158, 4, 2),     },      /* FVco 937.036800 */
+        { .frequency = 240468480,       .index = PLLVAL(134, 3, 2),     },      /* FVco 961.873920 */
+        { .frequency = 246960000,       .index = PLLVAL(167, 4, 2),     },      /* FVco 987.840000 */
+        { .frequency = 252322560,       .index = PLLVAL(141, 3, 2),     },      /* FVco 1009.290240 */
+        { .frequency = 258249600,       .index = PLLVAL(114, 2, 2),     },      /* FVco 1032.998400 */
+        { .frequency = 264176640,       .index = PLLVAL(148, 3, 2),     },      /* FVco 1056.706560 */
+        { .frequency = 270950400,       .index = PLLVAL(120, 2, 2),     },      /* FVco 1083.801600 */
+        { .frequency = 276030720,       .index = PLLVAL(155, 3, 2),     },      /* FVco 1104.122880 */
+        { .frequency = 282240000,       .index = PLLVAL(92, 1, 2),      },      /* FVco 1128.960000 */
+        { .frequency = 289578240,       .index = PLLVAL(163, 3, 2),     },      /* FVco 1158.312960 */
+        { .frequency = 294235200,       .index = PLLVAL(131, 2, 2),     },      /* FVco 1176.940800 */
+        { .frequency = 300200727,       .index = PLLVAL(187, 9, 1),     },      /* FVco 600.401454 */
+        { .frequency = 306358690,       .index = PLLVAL(191, 9, 1),     },      /* FVco 612.717380 */
+        { .frequency = 312076800,       .index = PLLVAL(121, 5, 1),     },      /* FVco 624.153600 */
+        { .frequency = 318366720,       .index = PLLVAL(86, 3, 1),      },      /* FVco 636.733440 */
+        { .frequency = 324172800,       .index = PLLVAL(126, 5, 1),     },      /* FVco 648.345600 */
+        { .frequency = 330220800,       .index = PLLVAL(109, 4, 1),     },      /* FVco 660.441600 */
+        { .frequency = 336268800,       .index = PLLVAL(131, 5, 1),     },      /* FVco 672.537600 */
+        { .frequency = 342074880,       .index = PLLVAL(93, 3, 1),      },      /* FVco 684.149760 */
+        { .frequency = 348096000,       .index = PLLVAL(177, 7, 1),     },      /* FVco 696.192000 */
+        { .frequency = 355622400,       .index = PLLVAL(118, 4, 1),     },      /* FVco 711.244800 */
+        { .frequency = 360460800,       .index = PLLVAL(141, 5, 1),     },      /* FVco 720.921600 */
+        { .frequency = 366206400,       .index = PLLVAL(165, 6, 1),     },      /* FVco 732.412800 */
+        { .frequency = 372556800,       .index = PLLVAL(124, 4, 1),     },      /* FVco 745.113600 */
+        { .frequency = 378201600,       .index = PLLVAL(126, 4, 1),     },      /* FVco 756.403200 */
+        { .frequency = 384652800,       .index = PLLVAL(151, 5, 1),     },      /* FVco 769.305600 */
+        { .frequency = 391608000,       .index = PLLVAL(177, 6, 1),     },      /* FVco 783.216000 */
+        { .frequency = 396264960,       .index = PLLVAL(109, 3, 1),     },      /* FVco 792.529920 */
+        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
+};
+
+static int s3c2440_plls169344_add(struct device *dev,
+                                  struct subsys_interface *sif)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        if (xtal == 169344000) {
+                printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_169344,
+                                           ARRAY_SIZE(s3c2440_plls_169344));
+        }
+
+        return 0;
+}
+
+static struct subsys_interface s3c2440_plls169344_interface = {
+        .name           = "s3c2440_plls169344",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_plls169344_add,
+};
+
+static int __init s3c2440_pll_16934400(void)
+{
+        return subsys_interface_register(&s3c2440_plls169344_interface);
+}
+arch_initcall(s3c2440_pll_16934400);
+
+static struct subsys_interface s3c2442_plls169344_interface = {
+        .name           = "s3c2442_plls169344",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_plls169344_add,
+};
+
+static int __init s3c2442_pll_16934400(void)
+{
+        return subsys_interface_register(&s3c2442_plls169344_interface);
+}
+arch_initcall(s3c2442_pll_16934400);
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 949ae05e07c5..2d82c4f116cd 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -29,16 +29,16 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
-
 #include <asm/mach-types.h>
 
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/h1940.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
 
+#include "h1940.h"
+
 static void s3c2410_pm_prepare(void)
 {
         /* ensure at least GSTATUS3 has the resume address */
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index f5dc2b254a5a..668a78a8b195 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -21,19 +21,19 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/cacheflush.h>
 #include <asm/irq.h>
 
-#include <mach/regs-power.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-
 #include <plat/s3c2412.h>
 
+#include "regs-dsc.h"
+#include "s3c2412-power.h"
+
 extern void s3c2412_sleep_enter(void);
 
 static int s3c2412_cpu_suspend(unsigned long arg)
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index 1a9e8dd194ff..44923895f558 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
@@ -16,12 +16,13 @@
 
 #include <asm/cacheflush.h>
 
-#include <mach/regs-power.h>
 #include <mach/regs-s3c2443-clock.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
 
+#include "s3c2412-power.h"
+
 extern void s3c2412_sleep_enter(void);
 
 static int s3c2416_cpu_suspend(unsigned long arg)
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 724755f0b0f5..caa5b7211380 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -38,7 +38,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-irq.h>
 
 #include <asm/mach/time.h>
@@ -46,6 +45,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 
+#include "regs-mem.h"
+
 #define PFX "s3c24xx-pm: "
 
 static struct sleep_save core_save[] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h
index 98fd4a05587c..98fd4a05587c 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c24xx/regs-dsc.h
diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c24xx/regs-mem.h
new file mode 100644
index 000000000000..86b1258368c2
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/regs-mem.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Memory Control register definitions
+ */
+
+#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
+#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
+
+#define S3C2410_MEMREG(x)               (S3C24XX_VA_MEMCTRL + (x))
+
+#define S3C2410_BWSCON                  S3C2410_MEMREG(0x00)
+#define S3C2410_BANKCON0                S3C2410_MEMREG(0x04)
+#define S3C2410_BANKCON1                S3C2410_MEMREG(0x08)
+#define S3C2410_BANKCON2                S3C2410_MEMREG(0x0C)
+#define S3C2410_BANKCON3                S3C2410_MEMREG(0x10)
+#define S3C2410_BANKCON4                S3C2410_MEMREG(0x14)
+#define S3C2410_BANKCON5                S3C2410_MEMREG(0x18)
+#define S3C2410_BANKCON6                S3C2410_MEMREG(0x1C)
+#define S3C2410_BANKCON7                S3C2410_MEMREG(0x20)
+#define S3C2410_REFRESH                 S3C2410_MEMREG(0x24)
+#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x28)
+
+#define S3C2410_BWSCON_ST1              (1 << 7)
+#define S3C2410_BWSCON_ST2              (1 << 11)
+#define S3C2410_BWSCON_ST3              (1 << 15)
+#define S3C2410_BWSCON_ST4              (1 << 19)
+#define S3C2410_BWSCON_ST5              (1 << 23)
+
+#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
+
+#define S3C2410_BWSCON_WS               (1 << 2)
+
+#define S3C2410_BANKCON_PMC16           (0x3)
+
+#define S3C2410_BANKCON_Tacp_SHIFT      (2)
+#define S3C2410_BANKCON_Tcah_SHIFT      (4)
+#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
+#define S3C2410_BANKCON_Tacc_SHIFT      (8)
+#define S3C2410_BANKCON_Tcos_SHIFT      (11)
+#define S3C2410_BANKCON_Tacs_SHIFT      (13)
+
+#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
+
+#define S3C2410_REFRESH_SELF            (1 << 22)
+
+#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
+
+#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index a3c5cb086ee2..9ebef95da721 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -49,6 +49,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
 
+#include "common.h"
+
 /* Initial IO mappings */
 
 static struct map_desc s3c2410_iodesc[] __initdata = {
@@ -182,8 +184,8 @@ int __init s3c2410_init(void)
 
 #ifdef CONFIG_PM
         register_syscore_ops(&s3c2410_pm_syscore_ops);
-#endif
         register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
 
         return device_register(&s3c2410_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2412-power.h b/arch/arm/mach-s3c24xx/s3c2412-power.h
new file mode 100644
index 000000000000..1b02c5ddb31b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412-power.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
+#define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
+
+#define S3C24XX_PWRREG(x)                       ((x) + S3C24XX_VA_CLKPWR)
+
+#define S3C2412_PWRMODECON                      S3C24XX_PWRREG(0x20)
+#define S3C2412_PWRCFG                          S3C24XX_PWRREG(0x24)
+
+#define S3C2412_INFORM0                         S3C24XX_PWRREG(0x70)
+#define S3C2412_INFORM1                         S3C24XX_PWRREG(0x74)
+#define S3C2412_INFORM2                         S3C24XX_PWRREG(0x78)
+#define S3C2412_INFORM3                         S3C24XX_PWRREG(0x7C)
+
+#define S3C2412_PWRCFG_BATF_IRQ                 (1 << 0)
+#define S3C2412_PWRCFG_BATF_IGNORE              (2 << 0)
+#define S3C2412_PWRCFG_BATF_SLEEP               (3 << 0)
+#define S3C2412_PWRCFG_BATF_MASK                (3 << 0)
+
+#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3 << 6)
+
+#define S3C2412_PWRCFG_RTC_MASKIRQ              (1 << 8)
+#define S3C2412_PWRCFG_NAND_NORST               (1 << 9)
+
+#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 6c5f4031ff0c..0d592159a5c3 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2412/s3c2412.c
- *
+/*
  * Copyright (c) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
@@ -28,28 +27,31 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 
-#include <plat/cpu-freq.h>
-
+#include <mach/hardware.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
-#include <plat/regs-spi.h>
-#include <mach/regs-s3c2412.h>
 
-#include <plat/s3c2412.h>
+#include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/pm.h>
-#include <plat/pll.h>
 #include <plat/nand-core.h>
+#include <plat/pll.h>
+#include <plat/pm.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-spi.h>
+#include <plat/s3c2412.h>
+
+#include "common.h"
+#include "regs-dsc.h"
+#include "s3c2412-power.h"
+
+#define S3C2412_SWRST                   (S3C24XX_VA_CLKPWR + 0x30)
+#define S3C2412_SWRST_RESET             (0x533C2412)
 
 #ifndef CONFIG_CPU_S3C2412_ONLY
 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@@ -244,8 +246,8 @@ int __init s3c2412_init(void)
 
 #ifdef CONFIG_PM
         register_syscore_ops(&s3c2412_pm_syscore_ops);
-#endif
         register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
 
         return device_register(&s3c2412_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/s3c2412.h
new file mode 100644
index 000000000000..548ced42cbb7
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
+#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__
+
+#define S3C2412_MEMREG(x)               (S3C24XX_VA_MEMCTRL + (x))
+#define S3C2412_EBIREG(x)               (S3C2412_VA_EBI + (x))
+
+#define S3C2412_SSMCREG(x)              (S3C2412_VA_SSMC + (x))
+#define S3C2412_SSMC(x, o)              (S3C2412_SSMCREG((x * 0x20) + (o)))
+
+#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
+
+#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x4)
+
+#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x0)
+
+#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 77ee0b732237..e30476db0295 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -63,6 +63,8 @@
 #include <plat/rtc-core.h>
 #include <plat/spi-core.h>
 
+#include "common.h"
+
 static struct map_desc s3c2416_iodesc[] __initdata = {
         IODESC_ENT(WATCHDOG),
         IODESC_ENT(CLKPWR),
@@ -105,9 +107,9 @@ int __init s3c2416_init(void)
 
 #ifdef CONFIG_PM
         register_syscore_ops(&s3c2416_pm_syscore_ops);
-#endif
         register_syscore_ops(&s3c24xx_irq_syscore_ops);
         register_syscore_ops(&s3c2416_irq_syscore_ops);
+#endif
 
         return device_register(&s3c2416_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 2b3dddb49af7..559e394e8989 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -40,6 +40,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
 
+#include "common.h"
+
 static struct device s3c2440_dev = {
         .bus            = &s3c2440_subsys,
 };
@@ -57,9 +59,9 @@ int __init s3c2440_init(void)
 
 #ifdef CONFIG_PM
         register_syscore_ops(&s3c2410_pm_syscore_ops);
+        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
         register_syscore_ops(&s3c244x_pm_syscore_ops);
-        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 
         /* register our system device for everything else */
 
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 22cb7c94a8c8..f732826c2359 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -51,6 +51,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
 
+#include "common.h"
+
 /* S3C2442 extended clock support */
 
 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
@@ -172,9 +174,9 @@ int __init s3c2442_init(void)
 
 #ifdef CONFIG_PM
         register_syscore_ops(&s3c2410_pm_syscore_ops);
+        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
         register_syscore_ops(&s3c244x_pm_syscore_ops);
-        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 
         return device_register(&s3c2442_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index b0b60a1154d6..ad2671baa910 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -36,7 +36,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
 
 #include <plat/s3c2410.h>
 #include <plat/s3c244x.h>
@@ -48,6 +47,8 @@
 #include <plat/nand-core.h>
 #include <plat/watchdog-reset.h>
 
+#include "regs-dsc.h"
+
 static struct map_desc s3c244x_iodesc[] __initdata = {
         IODESC_ENT(CLKPWR),
         IODESC_ENT(TIMER),
diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index fd0ef05763a9..67cb5120dfeb 100644
--- a/arch/arm/mach-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -17,16 +17,13 @@
 #include <linux/device.h>
 #include <linux/io.h>
 
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
-#include <mach/bast-cpld.h>
-
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include <plat/devs.h>
 
+#include "bast.h"
 #include "simtec.h"
 
 /* platform ops for audio */
diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c24xx/simtec-nor.c
index 029744fcaacb..8884bffa619a 100644
--- a/arch/arm/mach-s3c24xx/simtec-nor.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -27,9 +27,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/map.h>
-#include <mach/bast-map.h>
-#include <mach/bast-cpld.h>
 
+#include "bast.h"
 #include "simtec.h"
 
 static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c24xx/simtec-pm.c
index 699f93171297..38a2f1fdebab 100644
--- a/arch/arm/mach-s3c24xx/simtec-pm.c
+++ b/arch/arm/mach-s3c24xx/simtec-pm.c
@@ -28,12 +28,13 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 
 #include <asm/mach-types.h>
 
 #include <plat/pm.h>
 
+#include "regs-mem.h"
+
 #define COPYRIGHT ", Copyright 2005 Simtec Electronics"
 
 /* pm_simtec_init
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index ddf7a3c743ac..2ed2e32430dc 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -28,15 +28,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
-
 #include <mach/hardware.h>
 #include <asm/irq.h>
 
 #include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/devs.h>
 
+#include "bast.h"
 #include "simtec.h"
 
 /* control power and monitor over-current events on various Simtec
@@ -79,7 +77,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
         int ret;
 
         if (on) {
-                ret = request_irq(IRQ_USBOC, usb_simtec_ocirq,
+                ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq,
                                   IRQF_DISABLED | IRQF_TRIGGER_RISING |
                                    IRQF_TRIGGER_FALLING,
                                   "USB Over-current", info);
@@ -87,7 +85,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
                         printk(KERN_ERR "failed to request usb oc irq\n");
                 }
         } else {
-                free_irq(IRQ_USBOC, info);
+                free_irq(BAST_IRQ_USBOC, info);
         }
 }
 
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index 65200ae72c90..dd47c8fa07fa 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -31,9 +31,10 @@
 
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
 #include <plat/regs-serial.h>
 
+#include "regs-mem.h"
+
         /* s3c2410_cpu_suspend
          *
          * put the cpu into sleep mode
diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S
index c56612569b40..7f378b662da6 100644
--- a/arch/arm/mach-s3c24xx/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep.S
@@ -31,7 +31,6 @@
 
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
 #include <plat/regs-serial.h>
 
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
diff --git a/arch/arm/mach-s3c24xx/vr1000.h b/arch/arm/mach-s3c24xx/vr1000.h
new file mode 100644
index 000000000000..7fcd2c2f183c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/vr1000.h
@@ -0,0 +1,118 @@
+
+/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * VR1000 - CPLD control constants
+ * Machine VR1000 - IRQ Number definitions
+ * Machine VR1000 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_S3C24XX_VR1000_H
+#define __MACH_S3C24XX_VR1000_H __FILE__
+
+#define VR1000_CPLD_CTRL2_RAMWEN        (0x04)  /* SRAM Write Enable */
+
+/* irq numbers to onboard peripherals */
+
+#define VR1000_IRQ_USBOC                IRQ_EINT19
+#define VR1000_IRQ_IDE0                 IRQ_EINT16
+#define VR1000_IRQ_IDE1                 IRQ_EINT17
+#define VR1000_IRQ_SERIAL               IRQ_EINT12
+#define VR1000_IRQ_DM9000A              IRQ_EINT10
+#define VR1000_IRQ_DM9000N              IRQ_EINT9
+#define VR1000_IRQ_SMALERT              IRQ_EINT8
+
+/* map */
+
+#define VR1000_IOADDR(x)                (S3C2410_ADDR((x) + 0x01300000))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define VR1000_VA_CTRL1                 VR1000_IOADDR(0x00000000) /* 0x01300000 */
+#define VR1000_PA_CTRL1                 (S3C2410_CS5 | 0x7800000)
+
+#define VR1000_VA_CTRL2                 VR1000_IOADDR(0x00100000) /* 0x01400000 */
+#define VR1000_PA_CTRL2                 (S3C2410_CS1 | 0x6000000)
+
+#define VR1000_VA_CTRL3                 VR1000_IOADDR(0x00200000) /* 0x01500000 */
+#define VR1000_PA_CTRL3                 (S3C2410_CS1 | 0x6800000)
+
+#define VR1000_VA_CTRL4                 VR1000_IOADDR(0x00300000) /* 0x01600000 */
+#define VR1000_PA_CTRL4                 (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define VR1000_PA_PC104_IRQREQ          (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define VR1000_VA_PC104_IRQREQ          VR1000_IOADDR(0x00400000)
+
+#define VR1000_PA_PC104_IRQRAW          (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define VR1000_VA_PC104_IRQRAW          VR1000_IOADDR(0x00500000)
+
+#define VR1000_PA_PC104_IRQMASK         (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define VR1000_VA_PC104_IRQMASK         VR1000_IOADDR(0x00600000)
+
+/*
+ * 0xE0000000 contains the IO space that is split by speed and
+ * whether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
+ * 0x02600000 to 0x02700000 1MB
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define VR1000_VA_MULTISPACE    (0xE0000000)
+
+#define VR1000_VA_ISAIO         (VR1000_VA_MULTISPACE + 0x00000000)
+#define VR1000_VA_ISAMEM        (VR1000_VA_MULTISPACE + 0x01000000)
+#define VR1000_VA_IDEPRI        (VR1000_VA_MULTISPACE + 0x02000000)
+#define VR1000_VA_IDEPRIAUX     (VR1000_VA_MULTISPACE + 0x02100000)
+#define VR1000_VA_IDESEC        (VR1000_VA_MULTISPACE + 0x02200000)
+#define VR1000_VA_IDESECAUX     (VR1000_VA_MULTISPACE + 0x02300000)
+#define VR1000_VA_ASIXNET       (VR1000_VA_MULTISPACE + 0x02400000)
+#define VR1000_VA_DM9000        (VR1000_VA_MULTISPACE + 0x02500000)
+#define VR1000_VA_SUPERIO       (VR1000_VA_MULTISPACE + 0x02600000)
+
+/* physical offset addresses for the peripherals */
+
+#define VR1000_PA_IDEPRI        (0x02000000)
+#define VR1000_PA_IDEPRIAUX     (0x02800000)
+#define VR1000_PA_IDESEC        (0x03000000)
+#define VR1000_PA_IDESECAUX     (0x03800000)
+#define VR1000_PA_DM9000        (0x05000000)
+
+#define VR1000_PA_SERIAL        (0x11800000)
+#define VR1000_VA_SERIAL        (VR1000_IOADDR(0x00700000))
+
+/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
+#define VR1000_PA_SRAM          (S3C2410_CS1 | 0x05000000)
+
+/* some configurations for the peripherals */
+
+#define VR1000_DM9000_CS        VR1000_VAM_CS4
+
+#endif /* __MACH_S3C24XX_VR1000_H */