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-rw-r--r--arch/arm/mach-s3c24xx/sleep-s3c2410.S12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a5..65200ae72c90 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -45,9 +45,9 @@ ENTRY(s3c2410_cpu_suspend)
45 ldr r4, =S3C2410_REFRESH 45 ldr r4, =S3C2410_REFRESH
46 ldr r5, =S3C24XX_MISCCR 46 ldr r5, =S3C24XX_MISCCR
47 ldr r6, =S3C2410_CLKCON 47 ldr r6, =S3C2410_CLKCON
48 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) 48 ldr r7, [r4] @ get REFRESH (and ensure in TLB)
49 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) 49 ldr r8, [r5] @ get MISCCR (and ensure in TLB)
50 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB) 50 ldr r9, [r6] @ get CLKCON (and ensure in TLB)
51 51
52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command 52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals 53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
@@ -61,8 +61,8 @@ ENTRY(s3c2410_cpu_suspend)
61 @@ align next bit of code to cache line 61 @@ align next bit of code to cache line
62 .align 5 62 .align 5
63s3c2410_do_sleep: 63s3c2410_do_sleep:
64 streq r7, [ r4 ] @ SDRAM sleep command 64 streq r7, [r4] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config 65 streq r8, [r5] @ SDRAM power-down config
66 streq r9, [ r6 ] @ CPU sleep 66 streq r9, [r6] @ CPU sleep
671: beq 1b 671: beq 1b
68 mov pc, r14 68 mov pc, r14