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Diffstat (limited to 'arch/arm/mach-s3c24xx/s3c2412.c')
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.c43
1 files changed, 0 insertions, 43 deletions
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 657cbaca80ac..d49f52fbc842 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -173,49 +173,6 @@ void __init s3c2412_map_io(void)
173 173
174void __init_or_cpufreq s3c2412_setup_clocks(void) 174void __init_or_cpufreq s3c2412_setup_clocks(void)
175{ 175{
176 struct clk *xtal_clk;
177 unsigned long tmp;
178 unsigned long xtal;
179 unsigned long fclk;
180 unsigned long hclk;
181 unsigned long pclk;
182
183 xtal_clk = clk_get(NULL, "xtal");
184 xtal = clk_get_rate(xtal_clk);
185 clk_put(xtal_clk);
186
187 /* now we've got our machine bits initialised, work out what
188 * clocks we've got */
189
190 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
191
192 clk_mpll.rate = fclk;
193
194 tmp = __raw_readl(S3C2410_CLKDIVN);
195
196 /* work out clock scalings */
197
198 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
199 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
200 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
201
202 /* print brieft summary of clocks, etc */
203
204 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
205 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
206
207 s3c24xx_setup_clocks(fclk, hclk, pclk);
208}
209
210void __init s3c2412_init_clocks(int xtal)
211{
212 /* initialise the clocks here, to allow other things like the
213 * console to use them
214 */
215
216 s3c24xx_register_baseclocks(xtal);
217 s3c2412_setup_clocks();
218 s3c2412_baseclk_add();
219} 176}
220 177
221/* need to register the subsystem before we actually register the device, and 178/* need to register the subsystem before we actually register the device, and