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diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
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index 000000000000..60c72c54c21e
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1/* linux/arch/arm/mach-s3c2440/mach-anubis.c
2 *
3 * Copyright 2003-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/ata_platform.h>
22#include <linux/i2c.h>
23#include <linux/io.h>
24#include <linux/sm501.h>
25#include <linux/sm501-regs.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/anubis-map.h>
32#include <mach/anubis-irq.h>
33#include <mach/anubis-cpld.h>
34
35#include <mach/hardware.h>
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <plat/regs-serial.h>
40#include <mach/regs-gpio.h>
41#include <mach/regs-mem.h>
42#include <mach/regs-lcd.h>
43#include <plat/nand.h>
44#include <plat/iic.h>
45
46#include <linux/mtd/mtd.h>
47#include <linux/mtd/nand.h>
48#include <linux/mtd/nand_ecc.h>
49#include <linux/mtd/partitions.h>
50
51#include <net/ax88796.h>
52
53#include <plat/clock.h>
54#include <plat/devs.h>
55#include <plat/cpu.h>
56#include <plat/audio-simtec.h>
57
58#include "simtec.h"
59#include "common.h"
60
61#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
62
63static struct map_desc anubis_iodesc[] __initdata = {
64 /* ISA IO areas */
65
66 {
67 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
68 .pfn = __phys_to_pfn(0x0),
69 .length = SZ_4M,
70 .type = MT_DEVICE,
71 }, {
72 .virtual = (u32)S3C24XX_VA_ISA_WORD,
73 .pfn = __phys_to_pfn(0x0),
74 .length = SZ_4M,
75 .type = MT_DEVICE,
76 },
77
78 /* we could possibly compress the next set down into a set of smaller tables
79 * pagetables, but that would mean using an L2 section, and it still means
80 * we cannot actually feed the same register to an LDR due to 16K spacing
81 */
82
83 /* CPLD control registers */
84
85 {
86 .virtual = (u32)ANUBIS_VA_CTRL1,
87 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
88 .length = SZ_4K,
89 .type = MT_DEVICE,
90 }, {
91 .virtual = (u32)ANUBIS_VA_IDREG,
92 .pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
93 .length = SZ_4K,
94 .type = MT_DEVICE,
95 },
96};
97
98#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
99#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
100#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
101
102static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
103 [0] = {
104 .hwport = 0,
105 .flags = 0,
106 .ucon = UCON,
107 .ulcon = ULCON,
108 .ufcon = UFCON,
109 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
110 },
111 [1] = {
112 .hwport = 2,
113 .flags = 0,
114 .ucon = UCON,
115 .ulcon = ULCON,
116 .ufcon = UFCON,
117 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
118 },
119};
120
121/* NAND Flash on Anubis board */
122
123static int external_map[] = { 2 };
124static int chip0_map[] = { 0 };
125static int chip1_map[] = { 1 };
126
127static struct mtd_partition __initdata anubis_default_nand_part[] = {
128 [0] = {
129 .name = "Boot Agent",
130 .size = SZ_16K,
131 .offset = 0,
132 },
133 [1] = {
134 .name = "/boot",
135 .size = SZ_4M - SZ_16K,
136 .offset = SZ_16K,
137 },
138 [2] = {
139 .name = "user1",
140 .offset = SZ_4M,
141 .size = SZ_32M - SZ_4M,
142 },
143 [3] = {
144 .name = "user2",
145 .offset = SZ_32M,
146 .size = MTDPART_SIZ_FULL,
147 }
148};
149
150static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
151 [0] = {
152 .name = "Boot Agent",
153 .size = SZ_128K,
154 .offset = 0,
155 },
156 [1] = {
157 .name = "/boot",
158 .size = SZ_4M - SZ_128K,
159 .offset = SZ_128K,
160 },
161 [2] = {
162 .name = "user1",
163 .offset = SZ_4M,
164 .size = SZ_32M - SZ_4M,
165 },
166 [3] = {
167 .name = "user2",
168 .offset = SZ_32M,
169 .size = MTDPART_SIZ_FULL,
170 }
171};
172
173/* the Anubis has 3 selectable slots for nand-flash, the two
174 * on-board chip areas, as well as the external slot.
175 *
176 * Note, there is no current hot-plug support for the External
177 * socket.
178*/
179
180static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
181 [1] = {
182 .name = "External",
183 .nr_chips = 1,
184 .nr_map = external_map,
185 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
186 .partitions = anubis_default_nand_part,
187 },
188 [0] = {
189 .name = "chip0",
190 .nr_chips = 1,
191 .nr_map = chip0_map,
192 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
193 .partitions = anubis_default_nand_part,
194 },
195 [2] = {
196 .name = "chip1",
197 .nr_chips = 1,
198 .nr_map = chip1_map,
199 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
200 .partitions = anubis_default_nand_part,
201 },
202};
203
204static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
205{
206 unsigned int tmp;
207
208 slot = set->nr_map[slot] & 3;
209
210 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
211 slot, set, set->nr_map);
212
213 tmp = __raw_readb(ANUBIS_VA_CTRL1);
214 tmp &= ~ANUBIS_CTRL1_NANDSEL;
215 tmp |= slot;
216
217 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
218
219 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
220}
221
222static struct s3c2410_platform_nand __initdata anubis_nand_info = {
223 .tacls = 25,
224 .twrph0 = 55,
225 .twrph1 = 40,
226 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
227 .sets = anubis_nand_sets,
228 .select_chip = anubis_nand_select,
229};
230
231/* IDE channels */
232
233static struct pata_platform_info anubis_ide_platdata = {
234 .ioport_shift = 5,
235};
236
237static struct resource anubis_ide0_resource[] = {
238 {
239 .start = S3C2410_CS3,
240 .end = S3C2410_CS3 + (8*32) - 1,
241 .flags = IORESOURCE_MEM,
242 }, {
243 .start = S3C2410_CS3 + (1<<26) + (6*32),
244 .end = S3C2410_CS3 + (1<<26) + (7*32) - 1,
245 .flags = IORESOURCE_MEM,
246 }, {
247 .start = IRQ_IDE0,
248 .end = IRQ_IDE0,
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct platform_device anubis_device_ide0 = {
254 .name = "pata_platform",
255 .id = 0,
256 .num_resources = ARRAY_SIZE(anubis_ide0_resource),
257 .resource = anubis_ide0_resource,
258 .dev = {
259 .platform_data = &anubis_ide_platdata,
260 .coherent_dma_mask = ~0,
261 },
262};
263
264static struct resource anubis_ide1_resource[] = {
265 {
266 .start = S3C2410_CS4,
267 .end = S3C2410_CS4 + (8*32) - 1,
268 .flags = IORESOURCE_MEM,
269 }, {
270 .start = S3C2410_CS4 + (1<<26) + (6*32),
271 .end = S3C2410_CS4 + (1<<26) + (7*32) - 1,
272 .flags = IORESOURCE_MEM,
273 }, {
274 .start = IRQ_IDE0,
275 .end = IRQ_IDE0,
276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280static struct platform_device anubis_device_ide1 = {
281 .name = "pata_platform",
282 .id = 1,
283 .num_resources = ARRAY_SIZE(anubis_ide1_resource),
284 .resource = anubis_ide1_resource,
285 .dev = {
286 .platform_data = &anubis_ide_platdata,
287 .coherent_dma_mask = ~0,
288 },
289};
290
291/* Asix AX88796 10/100 ethernet controller */
292
293static struct ax_plat_data anubis_asix_platdata = {
294 .flags = AXFLG_MAC_FROMDEV,
295 .wordlength = 2,
296 .dcr_val = 0x48,
297 .rcr_val = 0x40,
298};
299
300static struct resource anubis_asix_resource[] = {
301 [0] = {
302 .start = S3C2410_CS5,
303 .end = S3C2410_CS5 + (0x20 * 0x20) -1,
304 .flags = IORESOURCE_MEM
305 },
306 [1] = {
307 .start = IRQ_ASIX,
308 .end = IRQ_ASIX,
309 .flags = IORESOURCE_IRQ
310 }
311};
312
313static struct platform_device anubis_device_asix = {
314 .name = "ax88796",
315 .id = 0,
316 .num_resources = ARRAY_SIZE(anubis_asix_resource),
317 .resource = anubis_asix_resource,
318 .dev = {
319 .platform_data = &anubis_asix_platdata,
320 }
321};
322
323/* SM501 */
324
325static struct resource anubis_sm501_resource[] = {
326 [0] = {
327 .start = S3C2410_CS2,
328 .end = S3C2410_CS2 + SZ_8M,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 .start = S3C2410_CS2 + SZ_64M - SZ_2M,
333 .end = S3C2410_CS2 + SZ_64M - 1,
334 .flags = IORESOURCE_MEM,
335 },
336 [2] = {
337 .start = IRQ_EINT0,
338 .end = IRQ_EINT0,
339 .flags = IORESOURCE_IRQ,
340 },
341};
342
343static struct sm501_initdata anubis_sm501_initdata = {
344 .gpio_high = {
345 .set = 0x3F000000, /* 24bit panel */
346 .mask = 0x0,
347 },
348 .misc_timing = {
349 .set = 0x010100, /* SDRAM timing */
350 .mask = 0x1F1F00,
351 },
352 .misc_control = {
353 .set = SM501_MISC_PNL_24BIT,
354 .mask = 0,
355 },
356
357 .devices = SM501_USE_GPIO,
358
359 /* set the SDRAM and bus clocks */
360 .mclk = 72 * MHZ,
361 .m1xclk = 144 * MHZ,
362};
363
364static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
365 [0] = {
366 .bus_num = 1,
367 .pin_scl = 44,
368 .pin_sda = 45,
369 },
370 [1] = {
371 .bus_num = 2,
372 .pin_scl = 40,
373 .pin_sda = 41,
374 },
375};
376
377static struct sm501_platdata anubis_sm501_platdata = {
378 .init = &anubis_sm501_initdata,
379 .gpio_base = -1,
380 .gpio_i2c = anubis_sm501_gpio_i2c,
381 .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
382};
383
384static struct platform_device anubis_device_sm501 = {
385 .name = "sm501",
386 .id = 0,
387 .num_resources = ARRAY_SIZE(anubis_sm501_resource),
388 .resource = anubis_sm501_resource,
389 .dev = {
390 .platform_data = &anubis_sm501_platdata,
391 },
392};
393
394/* Standard Anubis devices */
395
396static struct platform_device *anubis_devices[] __initdata = {
397 &s3c_device_ohci,
398 &s3c_device_wdt,
399 &s3c_device_adc,
400 &s3c_device_i2c0,
401 &s3c_device_rtc,
402 &s3c_device_nand,
403 &anubis_device_ide0,
404 &anubis_device_ide1,
405 &anubis_device_asix,
406 &anubis_device_sm501,
407};
408
409static struct clk *anubis_clocks[] __initdata = {
410 &s3c24xx_dclk0,
411 &s3c24xx_dclk1,
412 &s3c24xx_clkout0,
413 &s3c24xx_clkout1,
414 &s3c24xx_uclk,
415};
416
417/* I2C devices. */
418
419static struct i2c_board_info anubis_i2c_devs[] __initdata = {
420 {
421 I2C_BOARD_INFO("tps65011", 0x48),
422 .irq = IRQ_EINT20,
423 }
424};
425
426/* Audio setup */
427static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
428 .have_mic = 1,
429 .have_lout = 1,
430 .output_cdclk = 1,
431 .use_mpllin = 1,
432 .amp_gpio = S3C2410_GPB(2),
433 .amp_gain[0] = S3C2410_GPD(10),
434 .amp_gain[1] = S3C2410_GPD(11),
435};
436
437static void __init anubis_map_io(void)
438{
439 /* initialise the clocks */
440
441 s3c24xx_dclk0.parent = &clk_upll;
442 s3c24xx_dclk0.rate = 12*1000*1000;
443
444 s3c24xx_dclk1.parent = &clk_upll;
445 s3c24xx_dclk1.rate = 24*1000*1000;
446
447 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
448 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
449
450 s3c24xx_uclk.parent = &s3c24xx_clkout1;
451
452 s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
453
454 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
455 s3c24xx_init_clocks(0);
456 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
457
458 /* check for the newer revision boards with large page nand */
459
460 if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
461 printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
462 __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
463 anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
464 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
465 } else {
466 /* ensure that the GPIO is setup */
467 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
468 }
469}
470
471static void __init anubis_init(void)
472{
473 s3c_i2c0_set_platdata(NULL);
474 s3c_nand_set_platdata(&anubis_nand_info);
475 simtec_audio_add(NULL, false, &anubis_audio);
476
477 platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
478
479 i2c_register_board_info(0, anubis_i2c_devs,
480 ARRAY_SIZE(anubis_i2c_devs));
481}
482
483
484MACHINE_START(ANUBIS, "Simtec-Anubis")
485 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
486 .atag_offset = 0x100,
487 .map_io = anubis_map_io,
488 .init_machine = anubis_init,
489 .init_irq = s3c24xx_init_irq,
490 .timer = &s3c24xx_timer,
491 .restart = s3c244x_restart,
492MACHINE_END
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