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-rw-r--r--arch/arm/mach-s3c2443/clock.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 6a8d7cced4a2..f854e7385e3c 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -31,17 +31,17 @@
31#include <linux/mutex.h> 31#include <linux/mutex.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/serial_core.h> 33#include <linux/serial_core.h>
34#include <linux/io.h>
34 35
35#include <asm/mach/map.h> 36#include <asm/mach/map.h>
36 37
37#include <mach/hardware.h> 38#include <mach/hardware.h>
38#include <asm/io.h>
39 39
40#include <mach/regs-s3c2443-clock.h> 40#include <mach/regs-s3c2443-clock.h>
41 41
42#include <asm/plat-s3c24xx/s3c2443.h> 42#include <plat/s3c2443.h>
43#include <asm/plat-s3c24xx/clock.h> 43#include <plat/clock.h>
44#include <asm/plat-s3c24xx/cpu.h> 44#include <plat/cpu.h>
45 45
46/* We currently have to assume that the system is running 46/* We currently have to assume that the system is running
47 * from the XTPll input, and that all ***REFCLKs are being 47 * from the XTPll input, and that all ***REFCLKs are being
@@ -1033,8 +1033,7 @@ void __init s3c2443_init_clocks(int xtal)
1033 1033
1034 fclk = pll / s3c2443_fclk_div(clkdiv0); 1034 fclk = pll / s3c2443_fclk_div(clkdiv0);
1035 hclk = s3c2443_prediv_getrate(&clk_prediv); 1035 hclk = s3c2443_prediv_getrate(&clk_prediv);
1036 hclk = hclk / s3c2443_get_hdiv(clkdiv0); 1036 hclk /= s3c2443_get_hdiv(clkdiv0);
1037 hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
1038 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); 1037 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
1039 1038
1040 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); 1039 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);