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-rw-r--r--arch/arm/mach-s3c2412/Kconfig85
-rw-r--r--arch/arm/mach-s3c2412/Makefile12
-rw-r--r--arch/arm/mach-s3c2412/clock.c763
-rw-r--r--arch/arm/mach-s3c2412/dma.c180
-rw-r--r--arch/arm/mach-s3c2412/irq.c214
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c666
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c162
-rw-r--r--arch/arm/mach-s3c2412/mach-vstms.c166
-rw-r--r--arch/arm/mach-s3c2412/pm.c124
-rw-r--r--arch/arm/mach-s3c2412/s3c2412.c251
-rw-r--r--arch/arm/mach-s3c2412/sleep.S68
11 files changed, 0 insertions, 2691 deletions
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index b8b9029e9f2d..c5256f4e90bb 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -2,41 +2,6 @@
2# 2#
3# Licensed under GPLv2 3# Licensed under GPLv2
4 4
5config CPU_S3C2412
6 bool
7 depends on ARCH_S3C2410
8 select CPU_ARM926T
9 select CPU_LLSERIAL_S3C2440
10 select S3C2412_PM if PM
11 select S3C2412_DMA if S3C2410_DMA
12 help
13 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
14
15config CPU_S3C2412_ONLY
16 bool
17 depends on ARCH_S3C2410 && !CPU_S3C2410 && \
18 !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
19 !CPU_S3C2443 && CPU_S3C2412
20 default y if CPU_S3C2412
21
22config S3C2412_DMA
23 bool
24 depends on CPU_S3C2412
25 help
26 Internal config node for S3C2412 DMA support
27
28config S3C2412_PM
29 bool
30 select S3C2412_PM_SLEEP
31 help
32 Internal config node to apply S3C2412 power management
33
34config S3C2412_PM_SLEEP
35 bool
36 help
37 Internal config node to apply sleep for S3C2412 power management.
38 Can be selected by another SoCs with similar sleep procedure.
39
40# Note, the S3C2412 IOtiming support is in plat-s3c24xx 5# Note, the S3C2412 IOtiming support is in plat-s3c24xx
41 6
42config S3C2412_CPUFREQ 7config S3C2412_CPUFREQ
@@ -46,53 +11,3 @@ config S3C2412_CPUFREQ
46 default y 11 default y
47 help 12 help
48 CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. 13 CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
49
50menu "S3C2412 Machines"
51
52config MACH_JIVE
53 bool "Logitech Jive"
54 select CPU_S3C2412
55 select S3C_DEV_USB_HOST
56 select S3C_DEV_NAND
57 help
58 Say Y here if you are using the Logitech Jive.
59
60config MACH_JIVE_SHOW_BOOTLOADER
61 bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
62 depends on MACH_JIVE && EXPERIMENTAL
63
64config MACH_SMDK2413
65 bool "SMDK2413"
66 select CPU_S3C2412
67 select MACH_S3C2413
68 select MACH_SMDK
69 select S3C_DEV_USB_HOST
70 select S3C_DEV_NAND
71 help
72 Say Y here if you are using an SMDK2413
73
74config MACH_S3C2413
75 bool
76 help
77 Internal node for S3C2413 version of SMDK2413, so that
78 machine_is_s3c2413() will work when MACH_SMDK2413 is
79 selected
80
81config MACH_SMDK2412
82 bool "SMDK2412"
83 select MACH_SMDK2413
84 help
85 Say Y here if you are using an SMDK2412
86
87 Note, this shares support with SMDK2413, so will automatically
88 select MACH_SMDK2413.
89
90config MACH_VSTMS
91 bool "VMSTMS"
92 select CPU_S3C2412
93 select S3C_DEV_USB_HOST
94 select S3C_DEV_NAND
95 help
96 Say Y here if you are using an VSTMS board
97
98endmenu
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 7e4d95fa8a97..41a6c279fb2f 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -9,16 +9,4 @@ obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
11 11
12obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
13obj-$(CONFIG_CPU_S3C2412) += irq.o
14obj-$(CONFIG_CPU_S3C2412) += clock.o
15obj-$(CONFIG_S3C2412_DMA) += dma.o
16obj-$(CONFIG_S3C2412_PM) += pm.o
17obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o
18obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o 12obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o
19
20# Machine support
21
22obj-$(CONFIG_MACH_JIVE) += mach-jive.o
23obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o
24obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
deleted file mode 100644
index d10b695a9066..000000000000
--- a/arch/arm/mach-s3c2412/clock.c
+++ /dev/null
@@ -1,763 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412,S3C2413 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/errno.h>
28#include <linux/err.h>
29#include <linux/device.h>
30#include <linux/clk.h>
31#include <linux/mutex.h>
32#include <linux/delay.h>
33#include <linux/serial_core.h>
34#include <linux/io.h>
35
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39
40#include <plat/regs-serial.h>
41#include <mach/regs-clock.h>
42#include <mach/regs-gpio.h>
43
44#include <plat/s3c2412.h>
45#include <plat/clock.h>
46#include <plat/cpu.h>
47
48/* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being
50 * fed from it, as we cannot read the state of OM[4] from
51 * software.
52 *
53 * It would be possible for each board initialisation to
54 * set the correct muxing at initialisation
55*/
56
57static int s3c2412_clkcon_enable(struct clk *clk, int enable)
58{
59 unsigned int clocks = clk->ctrlbit;
60 unsigned long clkcon;
61
62 clkcon = __raw_readl(S3C2410_CLKCON);
63
64 if (enable)
65 clkcon |= clocks;
66 else
67 clkcon &= ~clocks;
68
69 __raw_writel(clkcon, S3C2410_CLKCON);
70
71 return 0;
72}
73
74static int s3c2412_upll_enable(struct clk *clk, int enable)
75{
76 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
77 unsigned long orig = upllcon;
78
79 if (!enable)
80 upllcon |= S3C2412_PLLCON_OFF;
81 else
82 upllcon &= ~S3C2412_PLLCON_OFF;
83
84 __raw_writel(upllcon, S3C2410_UPLLCON);
85
86 /* allow ~150uS for the PLL to settle and lock */
87
88 if (enable && (orig & S3C2412_PLLCON_OFF))
89 udelay(150);
90
91 return 0;
92}
93
94/* clock selections */
95
96static struct clk clk_erefclk = {
97 .name = "erefclk",
98};
99
100static struct clk clk_urefclk = {
101 .name = "urefclk",
102};
103
104static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
105{
106 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
107
108 if (parent == &clk_urefclk)
109 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
110 else if (parent == &clk_upll)
111 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
112 else
113 return -EINVAL;
114
115 clk->parent = parent;
116
117 __raw_writel(clksrc, S3C2412_CLKSRC);
118 return 0;
119}
120
121static struct clk clk_usysclk = {
122 .name = "usysclk",
123 .parent = &clk_xtal,
124 .ops = &(struct clk_ops) {
125 .set_parent = s3c2412_setparent_usysclk,
126 },
127};
128
129static struct clk clk_mrefclk = {
130 .name = "mrefclk",
131 .parent = &clk_xtal,
132};
133
134static struct clk clk_mdivclk = {
135 .name = "mdivclk",
136 .parent = &clk_xtal,
137};
138
139static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
140{
141 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
142
143 if (parent == &clk_usysclk)
144 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
145 else if (parent == &clk_h)
146 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
147 else
148 return -EINVAL;
149
150 clk->parent = parent;
151
152 __raw_writel(clksrc, S3C2412_CLKSRC);
153 return 0;
154}
155
156static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
157 unsigned long rate)
158{
159 unsigned long parent_rate = clk_get_rate(clk->parent);
160 int div;
161
162 if (rate > parent_rate)
163 return parent_rate;
164
165 div = parent_rate / rate;
166 if (div > 2)
167 div = 2;
168
169 return parent_rate / div;
170}
171
172static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
173{
174 unsigned long parent_rate = clk_get_rate(clk->parent);
175 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
176
177 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
178}
179
180static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
181{
182 unsigned long parent_rate = clk_get_rate(clk->parent);
183 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
184
185 rate = s3c2412_roundrate_usbsrc(clk, rate);
186
187 if ((parent_rate / rate) == 2)
188 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
189 else
190 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
191
192 __raw_writel(clkdivn, S3C2410_CLKDIVN);
193 return 0;
194}
195
196static struct clk clk_usbsrc = {
197 .name = "usbsrc",
198 .ops = &(struct clk_ops) {
199 .get_rate = s3c2412_getrate_usbsrc,
200 .set_rate = s3c2412_setrate_usbsrc,
201 .round_rate = s3c2412_roundrate_usbsrc,
202 .set_parent = s3c2412_setparent_usbsrc,
203 },
204};
205
206static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
207{
208 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
209
210 if (parent == &clk_mdivclk)
211 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
212 else if (parent == &clk_mpll)
213 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
214 else
215 return -EINVAL;
216
217 clk->parent = parent;
218
219 __raw_writel(clksrc, S3C2412_CLKSRC);
220 return 0;
221}
222
223static struct clk clk_msysclk = {
224 .name = "msysclk",
225 .ops = &(struct clk_ops) {
226 .set_parent = s3c2412_setparent_msysclk,
227 },
228};
229
230static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
231{
232 unsigned long flags;
233 unsigned long clkdiv;
234 unsigned long dvs;
235
236 /* Note, we current equate fclk andf msysclk for S3C2412 */
237
238 if (parent == &clk_msysclk || parent == &clk_f)
239 dvs = 0;
240 else if (parent == &clk_h)
241 dvs = S3C2412_CLKDIVN_DVSEN;
242 else
243 return -EINVAL;
244
245 clk->parent = parent;
246
247 /* update this under irq lockdown, clkdivn is not protected
248 * by the clock system. */
249
250 local_irq_save(flags);
251
252 clkdiv = __raw_readl(S3C2410_CLKDIVN);
253 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
254 clkdiv |= dvs;
255 __raw_writel(clkdiv, S3C2410_CLKDIVN);
256
257 local_irq_restore(flags);
258
259 return 0;
260}
261
262static struct clk clk_armclk = {
263 .name = "armclk",
264 .parent = &clk_msysclk,
265 .ops = &(struct clk_ops) {
266 .set_parent = s3c2412_setparent_armclk,
267 },
268};
269
270/* these next clocks have an divider immediately after them,
271 * so we can register them with their divider and leave out the
272 * intermediate clock stage
273*/
274static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
275 unsigned long rate)
276{
277 unsigned long parent_rate = clk_get_rate(clk->parent);
278 int div;
279
280 if (rate > parent_rate)
281 return parent_rate;
282
283 /* note, we remove the +/- 1 calculations as they cancel out */
284
285 div = (rate / parent_rate);
286
287 if (div < 1)
288 div = 1;
289 else if (div > 16)
290 div = 16;
291
292 return parent_rate / div;
293}
294
295static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
296{
297 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
298
299 if (parent == &clk_erefclk)
300 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
301 else if (parent == &clk_mpll)
302 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
303 else
304 return -EINVAL;
305
306 clk->parent = parent;
307
308 __raw_writel(clksrc, S3C2412_CLKSRC);
309 return 0;
310}
311
312static unsigned long s3c2412_getrate_uart(struct clk *clk)
313{
314 unsigned long parent_rate = clk_get_rate(clk->parent);
315 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
316
317 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
318 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
319
320 return parent_rate / (div + 1);
321}
322
323static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
324{
325 unsigned long parent_rate = clk_get_rate(clk->parent);
326 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
327
328 rate = s3c2412_roundrate_clksrc(clk, rate);
329
330 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
331 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
332
333 __raw_writel(clkdivn, S3C2410_CLKDIVN);
334 return 0;
335}
336
337static struct clk clk_uart = {
338 .name = "uartclk",
339 .ops = &(struct clk_ops) {
340 .get_rate = s3c2412_getrate_uart,
341 .set_rate = s3c2412_setrate_uart,
342 .set_parent = s3c2412_setparent_uart,
343 .round_rate = s3c2412_roundrate_clksrc,
344 },
345};
346
347static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
348{
349 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
350
351 if (parent == &clk_erefclk)
352 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
353 else if (parent == &clk_mpll)
354 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
355 else
356 return -EINVAL;
357
358 clk->parent = parent;
359
360 __raw_writel(clksrc, S3C2412_CLKSRC);
361 return 0;
362}
363
364static unsigned long s3c2412_getrate_i2s(struct clk *clk)
365{
366 unsigned long parent_rate = clk_get_rate(clk->parent);
367 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
368
369 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
370 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
371
372 return parent_rate / (div + 1);
373}
374
375static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
376{
377 unsigned long parent_rate = clk_get_rate(clk->parent);
378 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
379
380 rate = s3c2412_roundrate_clksrc(clk, rate);
381
382 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
383 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
384
385 __raw_writel(clkdivn, S3C2410_CLKDIVN);
386 return 0;
387}
388
389static struct clk clk_i2s = {
390 .name = "i2sclk",
391 .ops = &(struct clk_ops) {
392 .get_rate = s3c2412_getrate_i2s,
393 .set_rate = s3c2412_setrate_i2s,
394 .set_parent = s3c2412_setparent_i2s,
395 .round_rate = s3c2412_roundrate_clksrc,
396 },
397};
398
399static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
400{
401 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
402
403 if (parent == &clk_usysclk)
404 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
405 else if (parent == &clk_h)
406 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
407 else
408 return -EINVAL;
409
410 clk->parent = parent;
411
412 __raw_writel(clksrc, S3C2412_CLKSRC);
413 return 0;
414}
415static unsigned long s3c2412_getrate_cam(struct clk *clk)
416{
417 unsigned long parent_rate = clk_get_rate(clk->parent);
418 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
419
420 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
421 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
422
423 return parent_rate / (div + 1);
424}
425
426static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
427{
428 unsigned long parent_rate = clk_get_rate(clk->parent);
429 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
430
431 rate = s3c2412_roundrate_clksrc(clk, rate);
432
433 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
434 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
435
436 __raw_writel(clkdivn, S3C2410_CLKDIVN);
437 return 0;
438}
439
440static struct clk clk_cam = {
441 .name = "camif-upll", /* same as 2440 name */
442 .ops = &(struct clk_ops) {
443 .get_rate = s3c2412_getrate_cam,
444 .set_rate = s3c2412_setrate_cam,
445 .set_parent = s3c2412_setparent_cam,
446 .round_rate = s3c2412_roundrate_clksrc,
447 },
448};
449
450/* standard clock definitions */
451
452static struct clk init_clocks_disable[] = {
453 {
454 .name = "nand",
455 .parent = &clk_h,
456 .enable = s3c2412_clkcon_enable,
457 .ctrlbit = S3C2412_CLKCON_NAND,
458 }, {
459 .name = "sdi",
460 .parent = &clk_p,
461 .enable = s3c2412_clkcon_enable,
462 .ctrlbit = S3C2412_CLKCON_SDI,
463 }, {
464 .name = "adc",
465 .parent = &clk_p,
466 .enable = s3c2412_clkcon_enable,
467 .ctrlbit = S3C2412_CLKCON_ADC,
468 }, {
469 .name = "i2c",
470 .parent = &clk_p,
471 .enable = s3c2412_clkcon_enable,
472 .ctrlbit = S3C2412_CLKCON_IIC,
473 }, {
474 .name = "iis",
475 .parent = &clk_p,
476 .enable = s3c2412_clkcon_enable,
477 .ctrlbit = S3C2412_CLKCON_IIS,
478 }, {
479 .name = "spi",
480 .parent = &clk_p,
481 .enable = s3c2412_clkcon_enable,
482 .ctrlbit = S3C2412_CLKCON_SPI,
483 }
484};
485
486static struct clk init_clocks[] = {
487 {
488 .name = "dma",
489 .parent = &clk_h,
490 .enable = s3c2412_clkcon_enable,
491 .ctrlbit = S3C2412_CLKCON_DMA0,
492 }, {
493 .name = "dma",
494 .parent = &clk_h,
495 .enable = s3c2412_clkcon_enable,
496 .ctrlbit = S3C2412_CLKCON_DMA1,
497 }, {
498 .name = "dma",
499 .parent = &clk_h,
500 .enable = s3c2412_clkcon_enable,
501 .ctrlbit = S3C2412_CLKCON_DMA2,
502 }, {
503 .name = "dma",
504 .parent = &clk_h,
505 .enable = s3c2412_clkcon_enable,
506 .ctrlbit = S3C2412_CLKCON_DMA3,
507 }, {
508 .name = "lcd",
509 .parent = &clk_h,
510 .enable = s3c2412_clkcon_enable,
511 .ctrlbit = S3C2412_CLKCON_LCDC,
512 }, {
513 .name = "gpio",
514 .parent = &clk_p,
515 .enable = s3c2412_clkcon_enable,
516 .ctrlbit = S3C2412_CLKCON_GPIO,
517 }, {
518 .name = "usb-host",
519 .parent = &clk_h,
520 .enable = s3c2412_clkcon_enable,
521 .ctrlbit = S3C2412_CLKCON_USBH,
522 }, {
523 .name = "usb-device",
524 .parent = &clk_h,
525 .enable = s3c2412_clkcon_enable,
526 .ctrlbit = S3C2412_CLKCON_USBD,
527 }, {
528 .name = "timers",
529 .parent = &clk_p,
530 .enable = s3c2412_clkcon_enable,
531 .ctrlbit = S3C2412_CLKCON_PWMT,
532 }, {
533 .name = "uart",
534 .devname = "s3c2412-uart.0",
535 .parent = &clk_p,
536 .enable = s3c2412_clkcon_enable,
537 .ctrlbit = S3C2412_CLKCON_UART0,
538 }, {
539 .name = "uart",
540 .devname = "s3c2412-uart.1",
541 .parent = &clk_p,
542 .enable = s3c2412_clkcon_enable,
543 .ctrlbit = S3C2412_CLKCON_UART1,
544 }, {
545 .name = "uart",
546 .devname = "s3c2412-uart.2",
547 .parent = &clk_p,
548 .enable = s3c2412_clkcon_enable,
549 .ctrlbit = S3C2412_CLKCON_UART2,
550 }, {
551 .name = "rtc",
552 .parent = &clk_p,
553 .enable = s3c2412_clkcon_enable,
554 .ctrlbit = S3C2412_CLKCON_RTC,
555 }, {
556 .name = "watchdog",
557 .parent = &clk_p,
558 .ctrlbit = 0,
559 }, {
560 .name = "usb-bus-gadget",
561 .parent = &clk_usb_bus,
562 .enable = s3c2412_clkcon_enable,
563 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
564 }, {
565 .name = "usb-bus-host",
566 .parent = &clk_usb_bus,
567 .enable = s3c2412_clkcon_enable,
568 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
569 }
570};
571
572/* clocks to add where we need to check their parentage */
573
574struct clk_init {
575 struct clk *clk;
576 unsigned int bit;
577 struct clk *src_0;
578 struct clk *src_1;
579};
580
581static struct clk_init clks_src[] __initdata = {
582 {
583 .clk = &clk_usysclk,
584 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
585 .src_0 = &clk_urefclk,
586 .src_1 = &clk_upll,
587 }, {
588 .clk = &clk_i2s,
589 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
590 .src_0 = &clk_erefclk,
591 .src_1 = &clk_mpll,
592 }, {
593 .clk = &clk_cam,
594 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
595 .src_0 = &clk_usysclk,
596 .src_1 = &clk_h,
597 }, {
598 .clk = &clk_msysclk,
599 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
600 .src_0 = &clk_mdivclk,
601 .src_1 = &clk_mpll,
602 }, {
603 .clk = &clk_uart,
604 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
605 .src_0 = &clk_erefclk,
606 .src_1 = &clk_mpll,
607 }, {
608 .clk = &clk_usbsrc,
609 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
610 .src_0 = &clk_usysclk,
611 .src_1 = &clk_h,
612 /* here we assume OM[4] select xtal */
613 }, {
614 .clk = &clk_erefclk,
615 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
616 .src_0 = &clk_xtal,
617 .src_1 = &clk_ext,
618 }, {
619 .clk = &clk_urefclk,
620 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
621 .src_0 = &clk_xtal,
622 .src_1 = &clk_ext,
623 },
624};
625
626/* s3c2412_clk_initparents
627 *
628 * Initialise the parents for the clocks that we get at start-time
629*/
630
631static void __init s3c2412_clk_initparents(void)
632{
633 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
634 struct clk_init *cip = clks_src;
635 struct clk *src;
636 int ptr;
637 int ret;
638
639 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
640 ret = s3c24xx_register_clock(cip->clk);
641 if (ret < 0) {
642 printk(KERN_ERR "Failed to register clock %s (%d)\n",
643 cip->clk->name, ret);
644 }
645
646 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
647
648 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
649 clk_set_parent(cip->clk, src);
650 }
651}
652
653/* clocks to add straight away */
654
655static struct clk *clks[] __initdata = {
656 &clk_ext,
657 &clk_usb_bus,
658 &clk_mrefclk,
659 &clk_armclk,
660};
661
662static struct clk_lookup s3c2412_clk_lookup[] = {
663 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
664 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
665 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
666};
667
668int __init s3c2412_baseclk_add(void)
669{
670 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
671 unsigned int dvs;
672 struct clk *clkp;
673 int ret;
674 int ptr;
675
676 clk_upll.enable = s3c2412_upll_enable;
677 clk_usb_bus.parent = &clk_usbsrc;
678 clk_usb_bus.rate = 0x0;
679
680 clk_f.parent = &clk_msysclk;
681
682 s3c2412_clk_initparents();
683
684 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
685 clkp = clks[ptr];
686
687 ret = s3c24xx_register_clock(clkp);
688 if (ret < 0) {
689 printk(KERN_ERR "Failed to register clock %s (%d)\n",
690 clkp->name, ret);
691 }
692 }
693
694 /* set the dvs state according to what we got at boot time */
695
696 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
697
698 if (dvs)
699 clk_armclk.parent = &clk_h;
700
701 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
702
703 /* ensure usb bus clock is within correct rate of 48MHz */
704
705 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
706 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
707
708 /* for the moment, let's use the UPLL, and see if we can
709 * get 48MHz */
710
711 clk_set_parent(&clk_usysclk, &clk_upll);
712 clk_set_parent(&clk_usbsrc, &clk_usysclk);
713 clk_set_rate(&clk_usbsrc, 48*1000*1000);
714 }
715
716 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
717 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
718 print_mhz(clk_get_rate(&clk_upll)),
719 print_mhz(clk_get_rate(&clk_usb_bus)));
720
721 /* register clocks from clock array */
722
723 clkp = init_clocks;
724 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
725 /* ensure that we note the clock state */
726
727 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
728
729 ret = s3c24xx_register_clock(clkp);
730 if (ret < 0) {
731 printk(KERN_ERR "Failed to register clock %s (%d)\n",
732 clkp->name, ret);
733 }
734 }
735
736 /* We must be careful disabling the clocks we are not intending to
737 * be using at boot time, as subsystems such as the LCD which do
738 * their own DMA requests to the bus can cause the system to lockup
739 * if they where in the middle of requesting bus access.
740 *
741 * Disabling the LCD clock if the LCD is active is very dangerous,
742 * and therefore the bootloader should be careful to not enable
743 * the LCD clock if it is not needed.
744 */
745
746 /* install (and disable) the clocks we do not need immediately */
747
748 clkp = init_clocks_disable;
749 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
750
751 ret = s3c24xx_register_clock(clkp);
752 if (ret < 0) {
753 printk(KERN_ERR "Failed to register clock %s (%d)\n",
754 clkp->name, ret);
755 }
756
757 s3c2412_clkcon_enable(clkp, 0);
758 }
759
760 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
761 s3c_pwmclk_init();
762 return 0;
763}
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
deleted file mode 100644
index 38472ac920ff..000000000000
--- a/arch/arm/mach-s3c2412/dma.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/serial_core.h>
19#include <linux/io.h>
20
21#include <mach/dma.h>
22
23#include <plat/dma-s3c24xx.h>
24#include <plat/cpu.h>
25
26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h>
34#include <plat/regs-spi.h>
35
36#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
37
38static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
39 [DMACH_XD0] = {
40 .name = "xdreq0",
41 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
42 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0),
43 },
44 [DMACH_XD1] = {
45 .name = "xdreq1",
46 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
47 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1),
48 },
49 [DMACH_SDI] = {
50 .name = "sdi",
51 .channels = MAP(S3C2412_DMAREQSEL_SDI),
52 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
53 },
54 [DMACH_SPI0] = {
55 .name = "spi0",
56 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
57 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
58 },
59 [DMACH_SPI1] = {
60 .name = "spi1",
61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
62 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
63 },
64 [DMACH_UART0] = {
65 .name = "uart0",
66 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
67 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
68 },
69 [DMACH_UART1] = {
70 .name = "uart1",
71 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
72 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
73 },
74 [DMACH_UART2] = {
75 .name = "uart2",
76 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
77 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
78 },
79 [DMACH_UART0_SRC2] = {
80 .name = "uart0",
81 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
82 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
83 },
84 [DMACH_UART1_SRC2] = {
85 .name = "uart1",
86 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
87 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
88 },
89 [DMACH_UART2_SRC2] = {
90 .name = "uart2",
91 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
92 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
93 },
94 [DMACH_TIMER] = {
95 .name = "timer",
96 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
97 .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER),
98 },
99 [DMACH_I2S_IN] = {
100 .name = "i2s-sdi",
101 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
102 .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX),
103 },
104 [DMACH_I2S_OUT] = {
105 .name = "i2s-sdo",
106 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
107 .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX),
108 },
109 [DMACH_USB_EP1] = {
110 .name = "usb-ep1",
111 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
112 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1),
113 },
114 [DMACH_USB_EP2] = {
115 .name = "usb-ep2",
116 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
117 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2),
118 },
119 [DMACH_USB_EP3] = {
120 .name = "usb-ep3",
121 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
122 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3),
123 },
124 [DMACH_USB_EP4] = {
125 .name = "usb-ep4",
126 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
127 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4),
128 },
129};
130
131static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
132 struct s3c24xx_dma_map *map,
133 enum dma_data_direction dir)
134{
135 unsigned long chsel;
136
137 if (dir == DMA_FROM_DEVICE)
138 chsel = map->channels_rx[0];
139 else
140 chsel = map->channels[0];
141
142 chsel &= ~DMA_CH_VALID;
143 chsel |= S3C2412_DMAREQSEL_HW;
144
145 writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
146}
147
148static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
149 struct s3c24xx_dma_map *map)
150{
151 s3c2412_dma_direction(chan, map, chan->source);
152}
153
154static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
155 .select = s3c2412_dma_select,
156 .direction = s3c2412_dma_direction,
157 .dcon_mask = 0,
158 .map = s3c2412_dma_mappings,
159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
160};
161
162static int __init s3c2412_dma_add(struct device *dev,
163 struct subsys_interface *sif)
164{
165 s3c2410_dma_init();
166 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
167}
168
169static struct subsys_interface s3c2412_dma_interface = {
170 .name = "s3c2412_dma",
171 .subsys = &s3c2412_subsys,
172 .add_dev = s3c2412_dma_add,
173};
174
175static int __init s3c2412_dma_init(void)
176{
177 return subsys_interface_register(&s3c2412_dma_interface);
178}
179
180arch_initcall(s3c2412_dma_init);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
deleted file mode 100644
index e65619ddbccc..000000000000
--- a/arch/arm/mach-s3c2412/irq.c
+++ /dev/null
@@ -1,214 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/irq.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36#include <mach/regs-power.h>
37
38#include <plat/cpu.h>
39#include <plat/irq.h>
40#include <plat/pm.h>
41
42#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
43#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
44
45/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
46 * having them turn up in both the INT* and the EINT* registers. Whilst
47 * both show the status, they both now need to be acked when the IRQs
48 * go off.
49*/
50
51static void
52s3c2412_irq_mask(struct irq_data *data)
53{
54 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
55 unsigned long mask;
56
57 mask = __raw_readl(S3C2410_INTMSK);
58 __raw_writel(mask | bitval, S3C2410_INTMSK);
59
60 mask = __raw_readl(S3C2412_EINTMASK);
61 __raw_writel(mask | bitval, S3C2412_EINTMASK);
62}
63
64static inline void
65s3c2412_irq_ack(struct irq_data *data)
66{
67 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
68
69 __raw_writel(bitval, S3C2412_EINTPEND);
70 __raw_writel(bitval, S3C2410_SRCPND);
71 __raw_writel(bitval, S3C2410_INTPND);
72}
73
74static inline void
75s3c2412_irq_maskack(struct irq_data *data)
76{
77 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
78 unsigned long mask;
79
80 mask = __raw_readl(S3C2410_INTMSK);
81 __raw_writel(mask|bitval, S3C2410_INTMSK);
82
83 mask = __raw_readl(S3C2412_EINTMASK);
84 __raw_writel(mask | bitval, S3C2412_EINTMASK);
85
86 __raw_writel(bitval, S3C2412_EINTPEND);
87 __raw_writel(bitval, S3C2410_SRCPND);
88 __raw_writel(bitval, S3C2410_INTPND);
89}
90
91static void
92s3c2412_irq_unmask(struct irq_data *data)
93{
94 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
95 unsigned long mask;
96
97 mask = __raw_readl(S3C2412_EINTMASK);
98 __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
99
100 mask = __raw_readl(S3C2410_INTMSK);
101 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
102}
103
104static struct irq_chip s3c2412_irq_eint0t4 = {
105 .irq_ack = s3c2412_irq_ack,
106 .irq_mask = s3c2412_irq_mask,
107 .irq_unmask = s3c2412_irq_unmask,
108 .irq_set_wake = s3c_irq_wake,
109 .irq_set_type = s3c_irqext_type,
110};
111
112#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
113
114/* CF and SDI sub interrupts */
115
116static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
117{
118 unsigned int subsrc, submsk;
119
120 subsrc = __raw_readl(S3C2410_SUBSRCPND);
121 submsk = __raw_readl(S3C2410_INTSUBMSK);
122
123 subsrc &= ~submsk;
124
125 if (subsrc & INTBIT(IRQ_S3C2412_SDI))
126 generic_handle_irq(IRQ_S3C2412_SDI);
127
128 if (subsrc & INTBIT(IRQ_S3C2412_CF))
129 generic_handle_irq(IRQ_S3C2412_CF);
130}
131
132#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
133#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
134
135static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
136{
137 s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
138}
139
140static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
141{
142 s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
143}
144
145static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
146{
147 s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
148}
149
150static struct irq_chip s3c2412_irq_cfsdi = {
151 .name = "s3c2412-cfsdi",
152 .irq_ack = s3c2412_irq_cfsdi_ack,
153 .irq_mask = s3c2412_irq_cfsdi_mask,
154 .irq_unmask = s3c2412_irq_cfsdi_unmask,
155};
156
157static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
158{
159 unsigned long pwrcfg;
160
161 pwrcfg = __raw_readl(S3C2412_PWRCFG);
162 if (state)
163 pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
164 else
165 pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
166 __raw_writel(pwrcfg, S3C2412_PWRCFG);
167
168 return s3c_irq_chip.irq_set_wake(data, state);
169}
170
171static struct irq_chip s3c2412_irq_rtc_chip;
172
173static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
174{
175 unsigned int irqno;
176
177 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
178 irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
179 handle_edge_irq);
180 set_irq_flags(irqno, IRQF_VALID);
181 }
182
183 /* add demux support for CF/SDI */
184
185 irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
186
187 for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
188 irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
189 handle_level_irq);
190 set_irq_flags(irqno, IRQF_VALID);
191 }
192
193 /* change RTC IRQ's set wake method */
194
195 s3c2412_irq_rtc_chip = s3c_irq_chip;
196 s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
197
198 irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
199
200 return 0;
201}
202
203static struct subsys_interface s3c2412_irq_interface = {
204 .name = "s3c2412_irq",
205 .subsys = &s3c2412_subsys,
206 .add_dev = s3c2412_irq_add,
207};
208
209static int s3c2412_irq_init(void)
210{
211 return subsys_interface_register(&s3c2412_irq_interface);
212}
213
214arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
deleted file mode 100644
index ae73ba34ecc6..000000000000
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ /dev/null
@@ -1,666 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-jive.c
2 *
3 * Copyright 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/syscore_ops.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/i2c.h>
24
25#include <video/ili9320.h>
26
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_gpio.h>
29
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
33
34#include <plat/regs-serial.h>
35#include <plat/nand.h>
36#include <plat/iic.h>
37
38#include <mach/regs-power.h>
39#include <mach/regs-gpio.h>
40#include <mach/regs-mem.h>
41#include <mach/regs-lcd.h>
42#include <mach/fb.h>
43
44#include <asm/mach-types.h>
45
46#include <linux/mtd/mtd.h>
47#include <linux/mtd/nand.h>
48#include <linux/mtd/nand_ecc.h>
49#include <linux/mtd/partitions.h>
50
51#include <plat/s3c2412.h>
52#include <plat/gpio-cfg.h>
53#include <plat/clock.h>
54#include <plat/devs.h>
55#include <plat/cpu.h>
56#include <plat/pm.h>
57#include <plat/udc.h>
58
59static struct map_desc jive_iodesc[] __initdata = {
60};
61
62#define UCON S3C2410_UCON_DEFAULT
63#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
64#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
65
66static struct s3c2410_uartcfg jive_uartcfgs[] = {
67 [0] = {
68 .hwport = 0,
69 .flags = 0,
70 .ucon = UCON,
71 .ulcon = ULCON,
72 .ufcon = UFCON,
73 },
74 [1] = {
75 .hwport = 1,
76 .flags = 0,
77 .ucon = UCON,
78 .ulcon = ULCON,
79 .ufcon = UFCON,
80 },
81 [2] = {
82 .hwport = 2,
83 .flags = 0,
84 .ucon = UCON,
85 .ulcon = ULCON,
86 .ufcon = UFCON,
87 }
88};
89
90/* Jive flash assignment
91 *
92 * 0x00000000-0x00028000 : uboot
93 * 0x00028000-0x0002c000 : uboot env
94 * 0x0002c000-0x00030000 : spare
95 * 0x00030000-0x00200000 : zimage A
96 * 0x00200000-0x01600000 : cramfs A
97 * 0x01600000-0x017d0000 : zimage B
98 * 0x017d0000-0x02bd0000 : cramfs B
99 * 0x02bd0000-0x03fd0000 : yaffs
100 */
101static struct mtd_partition __initdata jive_imageA_nand_part[] = {
102
103#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
104 /* Don't allow access to the bootloader from linux */
105 {
106 .name = "uboot",
107 .offset = 0,
108 .size = (160 * SZ_1K),
109 .mask_flags = MTD_WRITEABLE, /* force read-only */
110 },
111
112 /* spare */
113 {
114 .name = "spare",
115 .offset = (176 * SZ_1K),
116 .size = (16 * SZ_1K),
117 },
118#endif
119
120 /* booted images */
121 {
122 .name = "kernel (ro)",
123 .offset = (192 * SZ_1K),
124 .size = (SZ_2M) - (192 * SZ_1K),
125 .mask_flags = MTD_WRITEABLE, /* force read-only */
126 }, {
127 .name = "root (ro)",
128 .offset = (SZ_2M),
129 .size = (20 * SZ_1M),
130 .mask_flags = MTD_WRITEABLE, /* force read-only */
131 },
132
133 /* yaffs */
134 {
135 .name = "yaffs",
136 .offset = (44 * SZ_1M),
137 .size = (20 * SZ_1M),
138 },
139
140 /* bootloader environment */
141 {
142 .name = "env",
143 .offset = (160 * SZ_1K),
144 .size = (16 * SZ_1K),
145 },
146
147 /* upgrade images */
148 {
149 .name = "zimage",
150 .offset = (22 * SZ_1M),
151 .size = (2 * SZ_1M) - (192 * SZ_1K),
152 }, {
153 .name = "cramfs",
154 .offset = (24 * SZ_1M) - (192*SZ_1K),
155 .size = (20 * SZ_1M),
156 },
157};
158
159static struct mtd_partition __initdata jive_imageB_nand_part[] = {
160
161#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
162 /* Don't allow access to the bootloader from linux */
163 {
164 .name = "uboot",
165 .offset = 0,
166 .size = (160 * SZ_1K),
167 .mask_flags = MTD_WRITEABLE, /* force read-only */
168 },
169
170 /* spare */
171 {
172 .name = "spare",
173 .offset = (176 * SZ_1K),
174 .size = (16 * SZ_1K),
175 },
176#endif
177
178 /* booted images */
179 {
180 .name = "kernel (ro)",
181 .offset = (22 * SZ_1M),
182 .size = (2 * SZ_1M) - (192 * SZ_1K),
183 .mask_flags = MTD_WRITEABLE, /* force read-only */
184 },
185 {
186 .name = "root (ro)",
187 .offset = (24 * SZ_1M) - (192 * SZ_1K),
188 .size = (20 * SZ_1M),
189 .mask_flags = MTD_WRITEABLE, /* force read-only */
190 },
191
192 /* yaffs */
193 {
194 .name = "yaffs",
195 .offset = (44 * SZ_1M),
196 .size = (20 * SZ_1M),
197 },
198
199 /* bootloader environment */
200 {
201 .name = "env",
202 .offset = (160 * SZ_1K),
203 .size = (16 * SZ_1K),
204 },
205
206 /* upgrade images */
207 {
208 .name = "zimage",
209 .offset = (192 * SZ_1K),
210 .size = (2 * SZ_1M) - (192 * SZ_1K),
211 }, {
212 .name = "cramfs",
213 .offset = (2 * SZ_1M),
214 .size = (20 * SZ_1M),
215 },
216};
217
218static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
219 [0] = {
220 .name = "flash",
221 .nr_chips = 1,
222 .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
223 .partitions = jive_imageA_nand_part,
224 },
225};
226
227static struct s3c2410_platform_nand __initdata jive_nand_info = {
228 /* set taken from osiris nand timings, possibly still conservative */
229 .tacls = 30,
230 .twrph0 = 55,
231 .twrph1 = 40,
232 .sets = jive_nand_sets,
233 .nr_sets = ARRAY_SIZE(jive_nand_sets),
234};
235
236static int __init jive_mtdset(char *options)
237{
238 struct s3c2410_nand_set *nand = &jive_nand_sets[0];
239 unsigned long set;
240
241 if (options == NULL || options[0] == '\0')
242 return 0;
243
244 if (strict_strtoul(options, 10, &set)) {
245 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
246 return 0;
247 }
248
249 switch (set) {
250 case 1:
251 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
252 nand->partitions = jive_imageB_nand_part;
253 case 0:
254 /* this is already setup in the nand info */
255 break;
256 default:
257 printk(KERN_ERR "Unknown mtd set %ld specified,"
258 "using default.", set);
259 }
260
261 return 0;
262}
263
264/* parse the mtdset= option given to the kernel command line */
265__setup("mtdset=", jive_mtdset);
266
267/* LCD timing and setup */
268
269#define LCD_XRES (240)
270#define LCD_YRES (320)
271#define LCD_LEFT_MARGIN (12)
272#define LCD_RIGHT_MARGIN (12)
273#define LCD_LOWER_MARGIN (12)
274#define LCD_UPPER_MARGIN (12)
275#define LCD_VSYNC (2)
276#define LCD_HSYNC (2)
277
278#define LCD_REFRESH (60)
279
280#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
281#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
282
283static struct s3c2410fb_display jive_vgg2432a4_display[] = {
284 [0] = {
285 .width = LCD_XRES,
286 .height = LCD_YRES,
287 .xres = LCD_XRES,
288 .yres = LCD_YRES,
289 .left_margin = LCD_LEFT_MARGIN,
290 .right_margin = LCD_RIGHT_MARGIN,
291 .upper_margin = LCD_UPPER_MARGIN,
292 .lower_margin = LCD_LOWER_MARGIN,
293 .hsync_len = LCD_HSYNC,
294 .vsync_len = LCD_VSYNC,
295
296 .pixclock = (1000000000000LL /
297 (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
298
299 .bpp = 16,
300 .type = (S3C2410_LCDCON1_TFT16BPP |
301 S3C2410_LCDCON1_TFT),
302
303 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
304 S3C2410_LCDCON5_INVVLINE |
305 S3C2410_LCDCON5_INVVFRAME |
306 S3C2410_LCDCON5_INVVDEN |
307 S3C2410_LCDCON5_PWREN),
308 },
309};
310
311/* todo - put into gpio header */
312
313#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
314#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
315
316static struct s3c2410fb_mach_info jive_lcd_config = {
317 .displays = jive_vgg2432a4_display,
318 .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
319 .default_display = 0,
320
321 /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
322 * and disable the pull down resistors on pins we are using for LCD
323 * data. */
324
325 .gpcup = (0xf << 1) | (0x3f << 10),
326
327 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
328 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
329 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
330 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
331 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
332
333 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
334 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
335 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
336 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
337 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
338
339 .gpdup = (0x3f << 2) | (0x3f << 10),
340
341 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
342 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
343 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
344 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
345 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
346 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
347
348 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
349 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
350 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
351 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
352 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
353 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
354};
355
356/* ILI9320 support. */
357
358static void jive_lcm_reset(unsigned int set)
359{
360 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
361
362 gpio_set_value(S3C2410_GPG(13), set);
363}
364
365#undef LCD_UPPER_MARGIN
366#define LCD_UPPER_MARGIN 2
367
368static struct ili9320_platdata jive_lcm_config = {
369 .hsize = LCD_XRES,
370 .vsize = LCD_YRES,
371
372 .reset = jive_lcm_reset,
373 .suspend = ILI9320_SUSPEND_DEEP,
374
375 .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
376 .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
377 ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
378 .display3 = 0x0,
379 .display4 = 0x0,
380 .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
381 ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
382 .rgb_if2 = ILI9320_RGBIF2_DPL,
383 .interface2 = 0x0,
384 .interface3 = 0x3,
385 .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
386 ILI9320_INTERFACE4_DIVE(1)),
387 .interface5 = 0x0,
388 .interface6 = 0x0,
389};
390
391/* LCD SPI support */
392
393static struct spi_gpio_platform_data jive_lcd_spi = {
394 .sck = S3C2410_GPG(8),
395 .mosi = S3C2410_GPB(8),
396 .miso = SPI_GPIO_NO_MISO,
397};
398
399static struct platform_device jive_device_lcdspi = {
400 .name = "spi-gpio",
401 .id = 1,
402 .dev.platform_data = &jive_lcd_spi,
403};
404
405
406/* WM8750 audio code SPI definition */
407
408static struct spi_gpio_platform_data jive_wm8750_spi = {
409 .sck = S3C2410_GPB(4),
410 .mosi = S3C2410_GPB(9),
411 .miso = SPI_GPIO_NO_MISO,
412};
413
414static struct platform_device jive_device_wm8750 = {
415 .name = "spi-gpio",
416 .id = 2,
417 .dev.platform_data = &jive_wm8750_spi,
418};
419
420/* JIVE SPI devices. */
421
422static struct spi_board_info __initdata jive_spi_devs[] = {
423 [0] = {
424 .modalias = "VGG2432A4",
425 .bus_num = 1,
426 .chip_select = 0,
427 .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
428 .max_speed_hz = 100000,
429 .platform_data = &jive_lcm_config,
430 .controller_data = (void *)S3C2410_GPB(7),
431 }, {
432 .modalias = "WM8750",
433 .bus_num = 2,
434 .chip_select = 0,
435 .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
436 .max_speed_hz = 100000,
437 .controller_data = (void *)S3C2410_GPH(10),
438 },
439};
440
441/* I2C bus and device configuration. */
442
443static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
444 .frequency = 80 * 1000,
445 .flags = S3C_IICFLG_FILTER,
446 .sda_delay = 2,
447};
448
449static struct i2c_board_info jive_i2c_devs[] __initdata = {
450 [0] = {
451 I2C_BOARD_INFO("lis302dl", 0x1c),
452 .irq = IRQ_EINT14,
453 },
454};
455
456/* The platform devices being used. */
457
458static struct platform_device *jive_devices[] __initdata = {
459 &s3c_device_ohci,
460 &s3c_device_rtc,
461 &s3c_device_wdt,
462 &s3c_device_i2c0,
463 &s3c_device_lcd,
464 &jive_device_lcdspi,
465 &jive_device_wm8750,
466 &s3c_device_nand,
467 &s3c_device_usbgadget,
468};
469
470static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
471 .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
472};
473
474/* Jive power management device */
475
476#ifdef CONFIG_PM
477static int jive_pm_suspend(void)
478{
479 /* Write the magic value u-boot uses to check for resume into
480 * the INFORM0 register, and ensure INFORM1 is set to the
481 * correct address to resume from. */
482
483 __raw_writel(0x2BED, S3C2412_INFORM0);
484 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
485
486 return 0;
487}
488
489static void jive_pm_resume(void)
490{
491 __raw_writel(0x0, S3C2412_INFORM0);
492}
493
494#else
495#define jive_pm_suspend NULL
496#define jive_pm_resume NULL
497#endif
498
499static struct syscore_ops jive_pm_syscore_ops = {
500 .suspend = jive_pm_suspend,
501 .resume = jive_pm_resume,
502};
503
504static void __init jive_map_io(void)
505{
506 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
507 s3c24xx_init_clocks(12000000);
508 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
509}
510
511static void jive_power_off(void)
512{
513 printk(KERN_INFO "powering system down...\n");
514
515 s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
516 s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
517}
518
519static void __init jive_machine_init(void)
520{
521 /* register system core operations for managing low level suspend */
522
523 register_syscore_ops(&jive_pm_syscore_ops);
524
525 /* write our sleep configurations for the IO. Pull down all unused
526 * IO, ensure that we have turned off all peripherals we do not
527 * need, and configure the ones we do need. */
528
529 /* Port B sleep */
530
531 __raw_writel(S3C2412_SLPCON_IN(0) |
532 S3C2412_SLPCON_PULL(1) |
533 S3C2412_SLPCON_HIGH(2) |
534 S3C2412_SLPCON_PULL(3) |
535 S3C2412_SLPCON_PULL(4) |
536 S3C2412_SLPCON_PULL(5) |
537 S3C2412_SLPCON_PULL(6) |
538 S3C2412_SLPCON_HIGH(7) |
539 S3C2412_SLPCON_PULL(8) |
540 S3C2412_SLPCON_PULL(9) |
541 S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
542
543 /* Port C sleep */
544
545 __raw_writel(S3C2412_SLPCON_PULL(0) |
546 S3C2412_SLPCON_PULL(1) |
547 S3C2412_SLPCON_PULL(2) |
548 S3C2412_SLPCON_PULL(3) |
549 S3C2412_SLPCON_PULL(4) |
550 S3C2412_SLPCON_PULL(5) |
551 S3C2412_SLPCON_LOW(6) |
552 S3C2412_SLPCON_PULL(6) |
553 S3C2412_SLPCON_PULL(7) |
554 S3C2412_SLPCON_PULL(8) |
555 S3C2412_SLPCON_PULL(9) |
556 S3C2412_SLPCON_PULL(10) |
557 S3C2412_SLPCON_PULL(11) |
558 S3C2412_SLPCON_PULL(12) |
559 S3C2412_SLPCON_PULL(13) |
560 S3C2412_SLPCON_PULL(14) |
561 S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
562
563 /* Port D sleep */
564
565 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
566
567 /* Port F sleep */
568
569 __raw_writel(S3C2412_SLPCON_LOW(0) |
570 S3C2412_SLPCON_LOW(1) |
571 S3C2412_SLPCON_LOW(2) |
572 S3C2412_SLPCON_EINT(3) |
573 S3C2412_SLPCON_EINT(4) |
574 S3C2412_SLPCON_EINT(5) |
575 S3C2412_SLPCON_EINT(6) |
576 S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
577
578 /* Port G sleep */
579
580 __raw_writel(S3C2412_SLPCON_IN(0) |
581 S3C2412_SLPCON_IN(1) |
582 S3C2412_SLPCON_IN(2) |
583 S3C2412_SLPCON_IN(3) |
584 S3C2412_SLPCON_IN(4) |
585 S3C2412_SLPCON_IN(5) |
586 S3C2412_SLPCON_IN(6) |
587 S3C2412_SLPCON_IN(7) |
588 S3C2412_SLPCON_PULL(8) |
589 S3C2412_SLPCON_PULL(9) |
590 S3C2412_SLPCON_IN(10) |
591 S3C2412_SLPCON_PULL(11) |
592 S3C2412_SLPCON_PULL(12) |
593 S3C2412_SLPCON_PULL(13) |
594 S3C2412_SLPCON_IN(14) |
595 S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
596
597 /* Port H sleep */
598
599 __raw_writel(S3C2412_SLPCON_PULL(0) |
600 S3C2412_SLPCON_PULL(1) |
601 S3C2412_SLPCON_PULL(2) |
602 S3C2412_SLPCON_PULL(3) |
603 S3C2412_SLPCON_PULL(4) |
604 S3C2412_SLPCON_PULL(5) |
605 S3C2412_SLPCON_PULL(6) |
606 S3C2412_SLPCON_IN(7) |
607 S3C2412_SLPCON_IN(8) |
608 S3C2412_SLPCON_PULL(9) |
609 S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
610
611 /* initialise the power management now we've setup everything. */
612
613 s3c_pm_init();
614
615 /** TODO - check that this is after the cmdline option! */
616 s3c_nand_set_platdata(&jive_nand_info);
617
618 /* initialise the spi */
619
620 gpio_request(S3C2410_GPG(13), "lcm reset");
621 gpio_direction_output(S3C2410_GPG(13), 0);
622
623 gpio_request(S3C2410_GPB(7), "jive spi");
624 gpio_direction_output(S3C2410_GPB(7), 1);
625
626 s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
627 s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
628
629 s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
630 s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
631
632 /* initialise the WM8750 spi */
633
634 gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
635 gpio_direction_output(S3C2410_GPH(10), 1);
636
637 /* Turn off suspend on both USB ports, and switch the
638 * selectable USB port to USB device mode. */
639
640 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
641 S3C2410_MISCCR_USBSUSPND0 |
642 S3C2410_MISCCR_USBSUSPND1, 0x0);
643
644 s3c24xx_udc_set_platdata(&jive_udc_cfg);
645 s3c24xx_fb_set_platdata(&jive_lcd_config);
646
647 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
648
649 s3c_i2c0_set_platdata(&jive_i2c_cfg);
650 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
651
652 pm_power_off = jive_power_off;
653
654 platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
655}
656
657MACHINE_START(JIVE, "JIVE")
658 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
659 .atag_offset = 0x100,
660
661 .init_irq = s3c24xx_init_irq,
662 .map_io = jive_map_io,
663 .init_machine = jive_machine_init,
664 .timer = &s3c24xx_timer,
665 .restart = s3c2412_restart,
666MACHINE_END
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
deleted file mode 100644
index b11451b853d8..000000000000
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ /dev/null
@@ -1,162 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/mach-smdk2413.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Thanks to Dimity Andric (TomTom) and Steven Ryu (Samsung) for the
7 * loans of SMDK2413 to work with.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/gpio.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <asm/hardware/iomd.h>
31#include <asm/setup.h>
32#include <asm/irq.h>
33#include <asm/mach-types.h>
34
35//#include <asm/debug-ll.h>
36#include <plat/regs-serial.h>
37#include <mach/regs-gpio.h>
38#include <mach/regs-lcd.h>
39
40#include <mach/idle.h>
41#include <plat/udc.h>
42#include <plat/iic.h>
43#include <mach/fb.h>
44
45#include <plat/s3c2410.h>
46#include <plat/s3c2412.h>
47#include <plat/clock.h>
48#include <plat/devs.h>
49#include <plat/cpu.h>
50
51#include <plat/common-smdk.h>
52
53static struct map_desc smdk2413_iodesc[] __initdata = {
54};
55
56static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = {
57 [0] = {
58 .hwport = 0,
59 .flags = 0,
60 .ucon = 0x3c5,
61 .ulcon = 0x03,
62 .ufcon = 0x51,
63 },
64 [1] = {
65 .hwport = 1,
66 .flags = 0,
67 .ucon = 0x3c5,
68 .ulcon = 0x03,
69 .ufcon = 0x51,
70 },
71 /* IR port */
72 [2] = {
73 .hwport = 2,
74 .flags = 0,
75 .ucon = 0x3c5,
76 .ulcon = 0x43,
77 .ufcon = 0x51,
78 }
79};
80
81
82static struct s3c2410_udc_mach_info smdk2413_udc_cfg __initdata = {
83 .pullup_pin = S3C2410_GPF(2),
84};
85
86
87static struct platform_device *smdk2413_devices[] __initdata = {
88 &s3c_device_ohci,
89 &s3c_device_wdt,
90 &s3c_device_i2c0,
91 &s3c_device_iis,
92 &s3c_device_usbgadget,
93};
94
95static void __init smdk2413_fixup(struct tag *tags, char **cmdline,
96 struct meminfo *mi)
97{
98 if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
99 mi->nr_banks=1;
100 mi->bank[0].start = 0x30000000;
101 mi->bank[0].size = SZ_64M;
102 }
103}
104
105static void __init smdk2413_map_io(void)
106{
107 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
108 s3c24xx_init_clocks(12000000);
109 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
110}
111
112static void __init smdk2413_machine_init(void)
113{ /* Turn off suspend on both USB ports, and switch the
114 * selectable USB port to USB device mode. */
115
116 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
117 S3C2410_MISCCR_USBSUSPND0 |
118 S3C2410_MISCCR_USBSUSPND1, 0x0);
119
120
121 s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
122 s3c_i2c0_set_platdata(NULL);
123
124 platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
125 smdk_machine_init();
126}
127
128MACHINE_START(S3C2413, "S3C2413")
129 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
130 .atag_offset = 0x100,
131
132 .fixup = smdk2413_fixup,
133 .init_irq = s3c24xx_init_irq,
134 .map_io = smdk2413_map_io,
135 .init_machine = smdk2413_machine_init,
136 .timer = &s3c24xx_timer,
137 .restart = s3c2412_restart,
138MACHINE_END
139
140MACHINE_START(SMDK2412, "SMDK2412")
141 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
142 .atag_offset = 0x100,
143
144 .fixup = smdk2413_fixup,
145 .init_irq = s3c24xx_init_irq,
146 .map_io = smdk2413_map_io,
147 .init_machine = smdk2413_machine_init,
148 .timer = &s3c24xx_timer,
149 .restart = s3c2412_restart,
150MACHINE_END
151
152MACHINE_START(SMDK2413, "SMDK2413")
153 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
154 .atag_offset = 0x100,
155
156 .fixup = smdk2413_fixup,
157 .init_irq = s3c24xx_init_irq,
158 .map_io = smdk2413_map_io,
159 .init_machine = smdk2413_machine_init,
160 .timer = &s3c24xx_timer,
161 .restart = s3c2412_restart,
162MACHINE_END
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
deleted file mode 100644
index 94bfaa1fb148..000000000000
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ /dev/null
@@ -1,166 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/mach-vstms.c
2 *
3 * (C) 2006 Thomas Gleixner <tglx@linutronix.de>
4 *
5 * Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/nand_ecc.h>
24#include <linux/mtd/partitions.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/setup.h>
32#include <asm/irq.h>
33#include <asm/mach-types.h>
34
35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h>
37#include <mach/regs-lcd.h>
38
39#include <mach/idle.h>
40#include <mach/fb.h>
41
42#include <plat/iic.h>
43#include <plat/nand.h>
44
45#include <plat/s3c2410.h>
46#include <plat/s3c2412.h>
47#include <plat/clock.h>
48#include <plat/devs.h>
49#include <plat/cpu.h>
50
51
52static struct map_desc vstms_iodesc[] __initdata = {
53};
54
55static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
56 [0] = {
57 .hwport = 0,
58 .flags = 0,
59 .ucon = 0x3c5,
60 .ulcon = 0x03,
61 .ufcon = 0x51,
62 },
63 [1] = {
64 .hwport = 1,
65 .flags = 0,
66 .ucon = 0x3c5,
67 .ulcon = 0x03,
68 .ufcon = 0x51,
69 },
70 [2] = {
71 .hwport = 2,
72 .flags = 0,
73 .ucon = 0x3c5,
74 .ulcon = 0x03,
75 .ufcon = 0x51,
76 }
77};
78
79static struct mtd_partition __initdata vstms_nand_part[] = {
80 [0] = {
81 .name = "Boot Agent",
82 .size = 0x7C000,
83 .offset = 0,
84 },
85 [1] = {
86 .name = "UBoot Config",
87 .offset = 0x7C000,
88 .size = 0x4000,
89 },
90 [2] = {
91 .name = "Kernel",
92 .offset = 0x80000,
93 .size = 0x200000,
94 },
95 [3] = {
96 .name = "RFS",
97 .offset = 0x280000,
98 .size = 0x3d80000,
99 },
100};
101
102static struct s3c2410_nand_set __initdata vstms_nand_sets[] = {
103 [0] = {
104 .name = "NAND",
105 .nr_chips = 1,
106 .nr_partitions = ARRAY_SIZE(vstms_nand_part),
107 .partitions = vstms_nand_part,
108 },
109};
110
111/* choose a set of timings which should suit most 512Mbit
112 * chips and beyond.
113*/
114
115static struct s3c2410_platform_nand __initdata vstms_nand_info = {
116 .tacls = 20,
117 .twrph0 = 60,
118 .twrph1 = 20,
119 .nr_sets = ARRAY_SIZE(vstms_nand_sets),
120 .sets = vstms_nand_sets,
121};
122
123static struct platform_device *vstms_devices[] __initdata = {
124 &s3c_device_ohci,
125 &s3c_device_wdt,
126 &s3c_device_i2c0,
127 &s3c_device_iis,
128 &s3c_device_rtc,
129 &s3c_device_nand,
130};
131
132static void __init vstms_fixup(struct tag *tags, char **cmdline,
133 struct meminfo *mi)
134{
135 if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
136 mi->nr_banks=1;
137 mi->bank[0].start = 0x30000000;
138 mi->bank[0].size = SZ_64M;
139 }
140}
141
142static void __init vstms_map_io(void)
143{
144 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
145 s3c24xx_init_clocks(12000000);
146 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
147}
148
149static void __init vstms_init(void)
150{
151 s3c_i2c0_set_platdata(NULL);
152 s3c_nand_set_platdata(&vstms_nand_info);
153
154 platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
155}
156
157MACHINE_START(VSTMS, "VSTMS")
158 .atag_offset = 0x100,
159
160 .fixup = vstms_fixup,
161 .init_irq = s3c24xx_init_irq,
162 .init_machine = vstms_init,
163 .map_io = vstms_map_io,
164 .timer = &s3c24xx_timer,
165 .restart = s3c2412_restart,
166MACHINE_END
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
deleted file mode 100644
index d04588506ec4..000000000000
--- a/arch/arm/mach-s3c2412/pm.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/pm.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/device.h>
20#include <linux/syscore_ops.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23
24#include <mach/hardware.h>
25#include <asm/cacheflush.h>
26#include <asm/irq.h>
27
28#include <mach/regs-power.h>
29#include <mach/regs-gpioj.h>
30#include <mach/regs-gpio.h>
31#include <mach/regs-dsc.h>
32
33#include <plat/cpu.h>
34#include <plat/pm.h>
35
36#include <plat/s3c2412.h>
37
38extern void s3c2412_sleep_enter(void);
39
40static int s3c2412_cpu_suspend(unsigned long arg)
41{
42 unsigned long tmp;
43
44 /* set our standby method to sleep */
45
46 tmp = __raw_readl(S3C2412_PWRCFG);
47 tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP;
48 __raw_writel(tmp, S3C2412_PWRCFG);
49
50 s3c2412_sleep_enter();
51
52 panic("sleep resumed to originator?");
53}
54
55static void s3c2412_pm_prepare(void)
56{
57}
58
59static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
60{
61 pm_cpu_prep = s3c2412_pm_prepare;
62 pm_cpu_sleep = s3c2412_cpu_suspend;
63
64 return 0;
65}
66
67static struct sleep_save s3c2412_sleep[] = {
68 SAVE_ITEM(S3C2412_DSC0),
69 SAVE_ITEM(S3C2412_DSC1),
70 SAVE_ITEM(S3C2413_GPJDAT),
71 SAVE_ITEM(S3C2413_GPJCON),
72 SAVE_ITEM(S3C2413_GPJUP),
73
74 /* save the PWRCFG to get back to original sleep method */
75
76 SAVE_ITEM(S3C2412_PWRCFG),
77
78 /* save the sleep configuration anyway, just in case these
79 * get damaged during wakeup */
80
81 SAVE_ITEM(S3C2412_GPBSLPCON),
82 SAVE_ITEM(S3C2412_GPCSLPCON),
83 SAVE_ITEM(S3C2412_GPDSLPCON),
84 SAVE_ITEM(S3C2412_GPFSLPCON),
85 SAVE_ITEM(S3C2412_GPGSLPCON),
86 SAVE_ITEM(S3C2412_GPHSLPCON),
87 SAVE_ITEM(S3C2413_GPJSLPCON),
88};
89
90static struct subsys_interface s3c2412_pm_interface = {
91 .name = "s3c2412_pm",
92 .subsys = &s3c2412_subsys,
93 .add_dev = s3c2412_pm_add,
94};
95
96static __init int s3c2412_pm_init(void)
97{
98 return subsys_interface_register(&s3c2412_pm_interface);
99}
100
101arch_initcall(s3c2412_pm_init);
102
103static int s3c2412_pm_suspend(void)
104{
105 s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
106 return 0;
107}
108
109static void s3c2412_pm_resume(void)
110{
111 unsigned long tmp;
112
113 tmp = __raw_readl(S3C2412_PWRCFG);
114 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
115 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
116 __raw_writel(tmp, S3C2412_PWRCFG);
117
118 s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
119}
120
121struct syscore_ops s3c2412_pm_syscore_ops = {
122 .suspend = s3c2412_pm_suspend,
123 .resume = s3c2412_pm_resume,
124};
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
deleted file mode 100644
index c6eac9871093..000000000000
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/s3c2412.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/device.h>
22#include <linux/syscore_ops.h>
23#include <linux/serial_core.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/hardware.h>
32#include <asm/proc-fns.h>
33#include <asm/irq.h>
34
35#include <plat/cpu-freq.h>
36
37#include <mach/regs-clock.h>
38#include <plat/regs-serial.h>
39#include <mach/regs-power.h>
40#include <mach/regs-gpio.h>
41#include <mach/regs-gpioj.h>
42#include <mach/regs-dsc.h>
43#include <plat/regs-spi.h>
44#include <mach/regs-s3c2412.h>
45
46#include <plat/s3c2412.h>
47#include <plat/cpu.h>
48#include <plat/devs.h>
49#include <plat/clock.h>
50#include <plat/pm.h>
51#include <plat/pll.h>
52#include <plat/nand-core.h>
53
54#ifndef CONFIG_CPU_S3C2412_ONLY
55void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
56
57static inline void s3c2412_init_gpio2(void)
58{
59 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
60}
61#else
62#define s3c2412_init_gpio2() do { } while(0)
63#endif
64
65/* Initial IO mappings */
66
67static struct map_desc s3c2412_iodesc[] __initdata = {
68 IODESC_ENT(CLKPWR),
69 IODESC_ENT(TIMER),
70 IODESC_ENT(WATCHDOG),
71 {
72 .virtual = (unsigned long)S3C2412_VA_SSMC,
73 .pfn = __phys_to_pfn(S3C2412_PA_SSMC),
74 .length = SZ_1M,
75 .type = MT_DEVICE,
76 },
77 {
78 .virtual = (unsigned long)S3C2412_VA_EBI,
79 .pfn = __phys_to_pfn(S3C2412_PA_EBI),
80 .length = SZ_1M,
81 .type = MT_DEVICE,
82 },
83};
84
85/* uart registration process */
86
87void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
88{
89 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
90
91 /* rename devices that are s3c2412/s3c2413 specific */
92 s3c_device_sdi.name = "s3c2412-sdi";
93 s3c_device_lcd.name = "s3c2412-lcd";
94 s3c_nand_setname("s3c2412-nand");
95
96 /* alter IRQ of SDI controller */
97
98 s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
99 s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
100
101 /* spi channel related changes, s3c2412/13 specific */
102 s3c_device_spi0.name = "s3c2412-spi";
103 s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
104 s3c_device_spi1.name = "s3c2412-spi";
105 s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
106 s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
107
108}
109
110/* s3c2412_idle
111 *
112 * use the standard idle call by ensuring the idle mode
113 * in power config, then issuing the idle co-processor
114 * instruction
115*/
116
117static void s3c2412_idle(void)
118{
119 unsigned long tmp;
120
121 /* ensure our idle mode is to go to idle */
122
123 tmp = __raw_readl(S3C2412_PWRCFG);
124 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
125 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
126 __raw_writel(tmp, S3C2412_PWRCFG);
127
128 cpu_do_idle();
129}
130
131void s3c2412_restart(char mode, const char *cmd)
132{
133 if (mode == 's')
134 soft_restart(0);
135
136 /* errata "Watch-dog/Software Reset Problem" specifies that
137 * this reset must be done with the SYSCLK sourced from
138 * EXTCLK instead of FOUT to avoid a glitch in the reset
139 * mechanism.
140 *
141 * See the watchdog section of the S3C2412 manual for more
142 * information on this fix.
143 */
144
145 __raw_writel(0x00, S3C2412_CLKSRC);
146 __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
147
148 mdelay(1);
149}
150
151/* s3c2412_map_io
152 *
153 * register the standard cpu IO areas, and any passed in from the
154 * machine specific initialisation.
155*/
156
157void __init s3c2412_map_io(void)
158{
159 /* move base of IO */
160
161 s3c2412_init_gpio2();
162
163 /* set our idle function */
164
165 arm_pm_idle = s3c2412_idle;
166
167 /* register our io-tables */
168
169 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
170}
171
172void __init_or_cpufreq s3c2412_setup_clocks(void)
173{
174 struct clk *xtal_clk;
175 unsigned long tmp;
176 unsigned long xtal;
177 unsigned long fclk;
178 unsigned long hclk;
179 unsigned long pclk;
180
181 xtal_clk = clk_get(NULL, "xtal");
182 xtal = clk_get_rate(xtal_clk);
183 clk_put(xtal_clk);
184
185 /* now we've got our machine bits initialised, work out what
186 * clocks we've got */
187
188 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
189
190 clk_mpll.rate = fclk;
191
192 tmp = __raw_readl(S3C2410_CLKDIVN);
193
194 /* work out clock scalings */
195
196 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
197 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
198 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
199
200 /* print brieft summary of clocks, etc */
201
202 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
203 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
204
205 s3c24xx_setup_clocks(fclk, hclk, pclk);
206}
207
208void __init s3c2412_init_clocks(int xtal)
209{
210 /* initialise the clocks here, to allow other things like the
211 * console to use them
212 */
213
214 s3c24xx_register_baseclocks(xtal);
215 s3c2412_setup_clocks();
216 s3c2412_baseclk_add();
217}
218
219/* need to register the subsystem before we actually register the device, and
220 * we also need to ensure that it has been initialised before any of the
221 * drivers even try to use it (even if not on an s3c2412 based system)
222 * as a driver which may support both 2410 and 2440 may try and use it.
223*/
224
225struct bus_type s3c2412_subsys = {
226 .name = "s3c2412-core",
227 .dev_name = "s3c2412-core",
228};
229
230static int __init s3c2412_core_init(void)
231{
232 return subsys_system_register(&s3c2412_subsys, NULL);
233}
234
235core_initcall(s3c2412_core_init);
236
237static struct device s3c2412_dev = {
238 .bus = &s3c2412_subsys,
239};
240
241int __init s3c2412_init(void)
242{
243 printk("S3C2412: Initialising architecture\n");
244
245#ifdef CONFIG_PM
246 register_syscore_ops(&s3c2412_pm_syscore_ops);
247#endif
248 register_syscore_ops(&s3c24xx_irq_syscore_ops);
249
250 return device_register(&s3c2412_dev);
251}
diff --git a/arch/arm/mach-s3c2412/sleep.S b/arch/arm/mach-s3c2412/sleep.S
deleted file mode 100644
index c82418ed714d..000000000000
--- a/arch/arm/mach-s3c2412/sleep.S
+++ /dev/null
@@ -1,68 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/sleep.S
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 Power Manager low-level sleep support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/linkage.h>
24#include <asm/assembler.h>
25#include <mach/hardware.h>
26#include <mach/map.h>
27
28#include <mach/regs-irq.h>
29
30 .text
31
32 .global s3c2412_sleep_enter
33
34s3c2412_sleep_enter:
35 mov r0, #0 /* argument for coprocessors */
36 ldr r1, =S3C2410_INTPND
37 ldr r2, =S3C2410_SRCPND
38 ldr r3, =S3C2410_EINTPEND
39
40 teq r0, r0
41 bl s3c2412_sleep_enter1
42 teq pc, r0
43 bl s3c2412_sleep_enter1
44
45 .align 5
46
47 /* this is called twice, first with the Z flag to ensure that the
48 * instructions have been loaded into the cache, and the second
49 * time to try and suspend the system.
50 */
51s3c2412_sleep_enter1:
52 mcr p15, 0, r0, c7, c10, 4
53 mcrne p15, 0, r0, c7, c0, 4
54
55 /* if we return from here, it is because an interrupt was
56 * active when we tried to shutdown. Try and ack the IRQ and
57 * retry, as simply returning causes the system to lock.
58 */
59
60 ldrne r9, [ r1 ]
61 strne r9, [ r1 ]
62 ldrne r9, [ r2 ]
63 strne r9, [ r2 ]
64 ldrne r9, [ r3 ]
65 strne r9, [ r3 ]
66 bne s3c2412_sleep_enter1
67
68 mov pc, r14
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 15:13:08 -0400