9 files changed, 255 insertions, 23 deletions

diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 8e8fe48ea47f..0b43431d4b75 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -10,6 +10,7 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_PM if PM
         select S3C2412_DMA if S3C2410_DMA
+        select S3C2410_GPIO
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index f8e011691b31..267f3348301e 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -12,8 +12,9 @@ obj-				:=
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
 obj-$(CONFIG_CPU_S3C2412)       += irq.o
 obj-$(CONFIG_CPU_S3C2412)       += clock.o
+obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
-obj-$(CONFIG_S3C2412_PM)        += pm.o
+obj-$(CONFIG_S3C2412_PM)        += pm.o sleep.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 458993601897..2697a65ba727 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -217,7 +217,7 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
 
         if (parent == &clk_mdivclk)
                 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
-        else if (parent == &clk_upll)
+        else if (parent == &clk_mpll)
                 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
         else
                 return -EINVAL;
@@ -234,6 +234,45 @@ static struct clk clk_msysclk = {
         .set_parent     = s3c2412_setparent_msysclk,
 };
 
+static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long flags;
+        unsigned long clkdiv;
+        unsigned long dvs;
+
+        /* Note, we current equate fclk andf msysclk for S3C2412 */
+
+        if (parent == &clk_msysclk || parent == &clk_f)
+                dvs = 0;
+        else if (parent == &clk_h)
+                dvs = S3C2412_CLKDIVN_DVSEN;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        /* update this under irq lockdown, clkdivn is not protected
+         * by the clock system. */
+
+        local_irq_save(flags);
+
+        clkdiv  = __raw_readl(S3C2410_CLKDIVN);
+        clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
+        clkdiv |= dvs;
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static struct clk clk_armclk = {
+        .name           = "armclk",
+        .id             = -1,
+        .parent         = &clk_msysclk,
+        .set_parent     = s3c2412_setparent_armclk,
+};
+
 /* these next clocks have an divider immediately after them,
  * so we can register them with their divider and leave out the
  * intermediate clock stage
@@ -630,11 +669,13 @@ static struct clk *clks[] __initdata = {
         &clk_erefclk,
         &clk_urefclk,
         &clk_mrefclk,
+        &clk_armclk,
 };
 
 int __init s3c2412_baseclk_add(void)
 {
         unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
+        unsigned int dvs;
         struct clk *clkp;
         int ret;
         int ptr;
@@ -643,6 +684,8 @@ int __init s3c2412_baseclk_add(void)
         clk_usb_bus.parent = &clk_usbsrc;
         clk_usb_bus.rate = 0x0;
 
+        clk_f.parent = &clk_msysclk;
+
         s3c2412_clk_initparents();
 
         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
@@ -655,6 +698,15 @@ int __init s3c2412_baseclk_add(void)
                 }
         }
 
+        /* set the dvs state according to what we got at boot time */
+
+        dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
+
+        if (dvs)
+                clk_armclk.parent = &clk_h;
+
+        printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
+
         /* ensure usb bus clock is within correct rate of 48MHz */
 
         if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 53c1d5bbce19..1dd864993566 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -30,6 +30,7 @@
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
+#include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
 #include <asm/plat-s3c24xx/regs-spi.h>
 
@@ -39,106 +40,141 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
         [DMACH_XD0] = {
                 .name           = "xdreq0",
                 .channels       = MAP(S3C2412_DMAREQSEL_XDREQ0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ0),
         },
         [DMACH_XD1] = {
                 .name           = "xdreq1",
                 .channels       = MAP(S3C2412_DMAREQSEL_XDREQ1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ1),
         },
         [DMACH_SDI] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_SDI),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
+                .hw_addr.to     = S3C2410_PA_SDI + S3C2410_SDIDATA,
+                .hw_addr.from   = S3C2410_PA_SDI + S3C2410_SDIDATA,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
                 .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
                 .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
                 .hw_addr.to     = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
                 .hw_addr.from   = S3C2410_PA_SPI + S3C2412_SPI1  + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
                 .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
                 .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
                 .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
                 .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
                 .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
                 .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_UART0_SRC2] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
                 .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
                 .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1_SRC2] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
                 .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
                 .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
                 .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
                 .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
                 .channels       = MAP(S3C2412_DMAREQSEL_TIMER),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_TIMER),
         },
         [DMACH_I2S_IN] = {
                 .name           = "i2s-sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2SRX),
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2SRX),
+                .hw_addr.from   = S3C2410_PA_IIS + S3C2412_IISRXD,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2STX),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2STX),
+                .hw_addr.to     = S3C2410_PA_IIS + S3C2412_IISTXD,
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP1),
         },
         [DMACH_USB_EP2] = {
                 .name           = "usb-ep2",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP2),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP2),
         },
         [DMACH_USB_EP3] = {
                 .name           = "usb-ep3",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP3),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP3),
         },
         [DMACH_USB_EP4] = {
                 .name           = "usb-ep4",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP4),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP4),
         },
 };
 
+static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
+                                  struct s3c24xx_dma_map *map,
+                                  enum s3c2410_dmasrc dir)
+{
+        unsigned long chsel;
+
+        if (dir == S3C2410_DMASRC_HW)
+                chsel = map->channels_rx[0];
+        else
+                chsel = map->channels[0];
+
+        chsel &= ~DMA_CH_VALID;
+        chsel |= S3C2412_DMAREQSEL_HW;
+
+        writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
+}
+
 static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
                                struct s3c24xx_dma_map *map)
 {
-        writel(map->channels[0] | S3C2412_DMAREQSEL_HW,
-               chan->regs + S3C2412_DMA_DMAREQSEL);
+        s3c2412_dma_direction(chan, map, chan->source);
 }
 
 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
         .select         = s3c2412_dma_select,
+        .direction      = s3c2412_dma_direction,
         .dcon_mask      = 0,
         .map            = s3c2412_dma_mappings,
         .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
new file mode 100644
index 000000000000..8e55c3a2eab8
--- /dev/null
+++ b/arch/arm/mach-s3c2412/gpio.c
@@ -0,0 +1,60 @@
+/* linux/arch/arm/mach-s3c2412/gpio.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/.
+ *
+ * S3C2412/S3C2413 specific GPIO support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/regs-gpio.h>
+
+#include <asm/hardware.h>
+
+int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
+{
+        void __iomem *base = S3C24XX_GPIO_BASE(pin);
+        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
+        unsigned long flags;
+        unsigned long slpcon;
+
+        offs *= 2;
+
+        if (pin < S3C2410_GPIO_BANKB)
+                return -EINVAL;
+
+        if (pin >= S3C2410_GPIO_BANKF &&
+            pin <= S3C2410_GPIO_BANKG)
+                return -EINVAL;
+
+        if (pin > (S3C2410_GPIO_BANKH + 32))
+                return -EINVAL;
+
+        local_irq_save(flags);
+
+        slpcon = __raw_readl(base + 0x0C);
+
+        slpcon &= ~(3 << offs);
+        slpcon |= state << offs;
+
+        __raw_writel(slpcon, base + 0x0C);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index e9d0c769f5da..cc1917bf952a 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -33,6 +33,7 @@
 
 #include <asm/arch/regs-irq.h>
 #include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-power.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/irq.h>
@@ -153,6 +154,22 @@ static struct irq_chip s3c2412_irq_cfsdi = {
         .unmask         = s3c2412_irq_cfsdi_unmask,
 };
 
+static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state)
+{
+        unsigned long pwrcfg;
+
+        pwrcfg = __raw_readl(S3C2412_PWRCFG);
+        if (state)
+                pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
+        else
+                pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
+        __raw_writel(pwrcfg, S3C2412_PWRCFG);
+
+        return s3c_irq_chip.set_wake(irqno, state);
+}
+
+static struct irq_chip s3c2412_irq_rtc_chip;
+
 static int s3c2412_irq_add(struct sys_device *sysdev)
 {
         unsigned int irqno;
@@ -173,6 +190,13 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
+        /* change RTC IRQ's set wake method */
+
+        s3c2412_irq_rtc_chip = s3c_irq_chip;
+        s3c2412_irq_rtc_chip.set_wake = s3c2412_irq_rtc_wake;
+
+        set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index 8988dac388a9..d4ffb2d98076 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -33,6 +33,8 @@
 
 #include <asm/plat-s3c24xx/s3c2412.h>
 
+extern void s3c2412_sleep_enter(void);
+
 static void s3c2412_cpu_suspend(void)
 {
         unsigned long tmp;
@@ -43,20 +45,7 @@ static void s3c2412_cpu_suspend(void)
         tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP;
         __raw_writel(tmp, S3C2412_PWRCFG);
 
-        /* issue the standby signal into the pm unit. Note, we
-         * issue a write-buffer drain just in case */
-
-        tmp = 0;
-
-        asm("b 1f\n\t"
-            ".align 5\n\t"
-            "1:\n\t"
-            "mcr p15, 0, %0, c7, c10, 4\n\t"
-            "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
-
-        /* we should never get past here */
-
-        panic("sleep resumed to originator?");
+        s3c2412_sleep_enter();
 }
 
 static void s3c2412_pm_prepare(void)
@@ -88,7 +77,6 @@ static struct sleep_save s3c2412_sleep[] = {
         SAVE_ITEM(S3C2412_GPBSLPCON),
         SAVE_ITEM(S3C2412_GPCSLPCON),
         SAVE_ITEM(S3C2412_GPDSLPCON),
-        SAVE_ITEM(S3C2412_GPESLPCON),
         SAVE_ITEM(S3C2412_GPFSLPCON),
         SAVE_ITEM(S3C2412_GPGSLPCON),
         SAVE_ITEM(S3C2412_GPHSLPCON),
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 265cd3f567a3..abf1599c9f97 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -168,6 +168,8 @@ void __init s3c2412_init_clocks(int xtal)
 
         fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
 
+        clk_mpll.rate = fclk;
+
         tmp = __raw_readl(S3C2410_CLKDIVN);
 
         /* work out clock scalings */
diff --git a/arch/arm/mach-s3c2412/sleep.S b/arch/arm/mach-s3c2412/sleep.S
new file mode 100644
index 000000000000..db32cac4199a
--- /dev/null
+++ b/arch/arm/mach-s3c2412/sleep.S
@@ -0,0 +1,68 @@
+/* linux/arch/arm/mach-s3c2412/sleep.S
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 Power Manager low-level sleep support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/hardware.h>
+#include <asm/arch/map.h>
+
+#include <asm/arch/regs-irq.h>
+
+        .text
+
+        .global s3c2412_sleep_enter
+
+s3c2412_sleep_enter:
+        mov     r0, #0                  /* argument for coprocessors */
+        ldr     r1, =S3C2410_INTPND
+        ldr     r2, =S3C2410_SRCPND
+        ldr     r3, =S3C2410_EINTPEND
+
+        teq     r0, r0
+        bl      s3c2412_sleep_enter1
+        teq     pc, r0
+        bl      s3c2412_sleep_enter1
+
+        .align  5
+
+        /* this is called twice, first with the Z flag to ensure that the
+         * instructions have been loaded into the cache, and the second
+         * time to try and suspend the system.
+        */
+s3c2412_sleep_enter1:
+        mcr     p15, 0, r0, c7, c10, 4
+        mcrne   p15, 0, r0, c7, c0, 4
+
+        /* if we return from here, it is because an interrupt was
+         * active when we tried to shutdown. Try and ack the IRQ and
+         * retry, as simply returning causes the system to lock.
+        */
+
+        ldrne   r9, [ r1 ]
+        strne   r9, [ r1 ]
+        ldrne   r9, [ r2 ]
+        strne   r9, [ r2 ]
+        ldrne   r9, [ r3 ]
+        strne   r9, [ r3 ]
+        bne     s3c2412_sleep_enter1
+
+        mov     pc, r14