diff options
Diffstat (limited to 'arch/arm/mach-s3c2412/dma.c')
-rw-r--r-- | arch/arm/mach-s3c2412/dma.c | 48 |
1 files changed, 42 insertions, 6 deletions
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index 53c1d5bbce19..1dd864993566 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <asm/arch/regs-mem.h> | 30 | #include <asm/arch/regs-mem.h> |
31 | #include <asm/arch/regs-lcd.h> | 31 | #include <asm/arch/regs-lcd.h> |
32 | #include <asm/arch/regs-sdi.h> | 32 | #include <asm/arch/regs-sdi.h> |
33 | #include <asm/plat-s3c24xx/regs-s3c2412-iis.h> | ||
33 | #include <asm/plat-s3c24xx/regs-iis.h> | 34 | #include <asm/plat-s3c24xx/regs-iis.h> |
34 | #include <asm/plat-s3c24xx/regs-spi.h> | 35 | #include <asm/plat-s3c24xx/regs-spi.h> |
35 | 36 | ||
@@ -39,106 +40,141 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { | |||
39 | [DMACH_XD0] = { | 40 | [DMACH_XD0] = { |
40 | .name = "xdreq0", | 41 | .name = "xdreq0", |
41 | .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), | 42 | .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), |
43 | .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0), | ||
42 | }, | 44 | }, |
43 | [DMACH_XD1] = { | 45 | [DMACH_XD1] = { |
44 | .name = "xdreq1", | 46 | .name = "xdreq1", |
45 | .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), | 47 | .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), |
48 | .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1), | ||
46 | }, | 49 | }, |
47 | [DMACH_SDI] = { | 50 | [DMACH_SDI] = { |
48 | .name = "sdi", | 51 | .name = "sdi", |
49 | .channels = MAP(S3C2412_DMAREQSEL_SDI), | 52 | .channels = MAP(S3C2412_DMAREQSEL_SDI), |
50 | .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, | 53 | .channels_rx = MAP(S3C2412_DMAREQSEL_SDI), |
51 | .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, | 54 | .hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA, |
55 | .hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA, | ||
52 | }, | 56 | }, |
53 | [DMACH_SPI0] = { | 57 | [DMACH_SPI0] = { |
54 | .name = "spi0", | 58 | .name = "spi0", |
55 | .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), | 59 | .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), |
60 | .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), | ||
56 | .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, | 61 | .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, |
57 | .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, | 62 | .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, |
58 | }, | 63 | }, |
59 | [DMACH_SPI1] = { | 64 | [DMACH_SPI1] = { |
60 | .name = "spi1", | 65 | .name = "spi1", |
61 | .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), | 66 | .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), |
67 | .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), | ||
62 | .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT, | 68 | .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT, |
63 | .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT, | 69 | .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT, |
64 | }, | 70 | }, |
65 | [DMACH_UART0] = { | 71 | [DMACH_UART0] = { |
66 | .name = "uart0", | 72 | .name = "uart0", |
67 | .channels = MAP(S3C2412_DMAREQSEL_UART0_0), | 73 | .channels = MAP(S3C2412_DMAREQSEL_UART0_0), |
74 | .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), | ||
68 | .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, | 75 | .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, |
69 | .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, | 76 | .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, |
70 | }, | 77 | }, |
71 | [DMACH_UART1] = { | 78 | [DMACH_UART1] = { |
72 | .name = "uart1", | 79 | .name = "uart1", |
73 | .channels = MAP(S3C2412_DMAREQSEL_UART1_0), | 80 | .channels = MAP(S3C2412_DMAREQSEL_UART1_0), |
81 | .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), | ||
74 | .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, | 82 | .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, |
75 | .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, | 83 | .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, |
76 | }, | 84 | }, |
77 | [DMACH_UART2] = { | 85 | [DMACH_UART2] = { |
78 | .name = "uart2", | 86 | .name = "uart2", |
79 | .channels = MAP(S3C2412_DMAREQSEL_UART2_0), | 87 | .channels = MAP(S3C2412_DMAREQSEL_UART2_0), |
88 | .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), | ||
80 | .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, | 89 | .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, |
81 | .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, | 90 | .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, |
82 | }, | 91 | }, |
83 | [DMACH_UART0_SRC2] = { | 92 | [DMACH_UART0_SRC2] = { |
84 | .name = "uart0", | 93 | .name = "uart0", |
85 | .channels = MAP(S3C2412_DMAREQSEL_UART0_1), | 94 | .channels = MAP(S3C2412_DMAREQSEL_UART0_1), |
95 | .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), | ||
86 | .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, | 96 | .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, |
87 | .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, | 97 | .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, |
88 | }, | 98 | }, |
89 | [DMACH_UART1_SRC2] = { | 99 | [DMACH_UART1_SRC2] = { |
90 | .name = "uart1", | 100 | .name = "uart1", |
91 | .channels = MAP(S3C2412_DMAREQSEL_UART1_1), | 101 | .channels = MAP(S3C2412_DMAREQSEL_UART1_1), |
102 | .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), | ||
92 | .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, | 103 | .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, |
93 | .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, | 104 | .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, |
94 | }, | 105 | }, |
95 | [DMACH_UART2_SRC2] = { | 106 | [DMACH_UART2_SRC2] = { |
96 | .name = "uart2", | 107 | .name = "uart2", |
97 | .channels = MAP(S3C2412_DMAREQSEL_UART2_1), | 108 | .channels = MAP(S3C2412_DMAREQSEL_UART2_1), |
109 | .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), | ||
98 | .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, | 110 | .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, |
99 | .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, | 111 | .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, |
100 | }, | 112 | }, |
101 | [DMACH_TIMER] = { | 113 | [DMACH_TIMER] = { |
102 | .name = "timer", | 114 | .name = "timer", |
103 | .channels = MAP(S3C2412_DMAREQSEL_TIMER), | 115 | .channels = MAP(S3C2412_DMAREQSEL_TIMER), |
116 | .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER), | ||
104 | }, | 117 | }, |
105 | [DMACH_I2S_IN] = { | 118 | [DMACH_I2S_IN] = { |
106 | .name = "i2s-sdi", | 119 | .name = "i2s-sdi", |
107 | .channels = MAP(S3C2412_DMAREQSEL_I2SRX), | 120 | .channels = MAP(S3C2412_DMAREQSEL_I2SRX), |
108 | .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, | 121 | .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX), |
122 | .hw_addr.from = S3C2410_PA_IIS + S3C2412_IISRXD, | ||
109 | }, | 123 | }, |
110 | [DMACH_I2S_OUT] = { | 124 | [DMACH_I2S_OUT] = { |
111 | .name = "i2s-sdo", | 125 | .name = "i2s-sdo", |
112 | .channels = MAP(S3C2412_DMAREQSEL_I2STX), | 126 | .channels = MAP(S3C2412_DMAREQSEL_I2STX), |
113 | .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, | 127 | .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX), |
128 | .hw_addr.to = S3C2410_PA_IIS + S3C2412_IISTXD, | ||
114 | }, | 129 | }, |
115 | [DMACH_USB_EP1] = { | 130 | [DMACH_USB_EP1] = { |
116 | .name = "usb-ep1", | 131 | .name = "usb-ep1", |
117 | .channels = MAP(S3C2412_DMAREQSEL_USBEP1), | 132 | .channels = MAP(S3C2412_DMAREQSEL_USBEP1), |
133 | .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1), | ||
118 | }, | 134 | }, |
119 | [DMACH_USB_EP2] = { | 135 | [DMACH_USB_EP2] = { |
120 | .name = "usb-ep2", | 136 | .name = "usb-ep2", |
121 | .channels = MAP(S3C2412_DMAREQSEL_USBEP2), | 137 | .channels = MAP(S3C2412_DMAREQSEL_USBEP2), |
138 | .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2), | ||
122 | }, | 139 | }, |
123 | [DMACH_USB_EP3] = { | 140 | [DMACH_USB_EP3] = { |
124 | .name = "usb-ep3", | 141 | .name = "usb-ep3", |
125 | .channels = MAP(S3C2412_DMAREQSEL_USBEP3), | 142 | .channels = MAP(S3C2412_DMAREQSEL_USBEP3), |
143 | .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3), | ||
126 | }, | 144 | }, |
127 | [DMACH_USB_EP4] = { | 145 | [DMACH_USB_EP4] = { |
128 | .name = "usb-ep4", | 146 | .name = "usb-ep4", |
129 | .channels = MAP(S3C2412_DMAREQSEL_USBEP4), | 147 | .channels = MAP(S3C2412_DMAREQSEL_USBEP4), |
148 | .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4), | ||
130 | }, | 149 | }, |
131 | }; | 150 | }; |
132 | 151 | ||
152 | static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan, | ||
153 | struct s3c24xx_dma_map *map, | ||
154 | enum s3c2410_dmasrc dir) | ||
155 | { | ||
156 | unsigned long chsel; | ||
157 | |||
158 | if (dir == S3C2410_DMASRC_HW) | ||
159 | chsel = map->channels_rx[0]; | ||
160 | else | ||
161 | chsel = map->channels[0]; | ||
162 | |||
163 | chsel &= ~DMA_CH_VALID; | ||
164 | chsel |= S3C2412_DMAREQSEL_HW; | ||
165 | |||
166 | writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL); | ||
167 | } | ||
168 | |||
133 | static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, | 169 | static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, |
134 | struct s3c24xx_dma_map *map) | 170 | struct s3c24xx_dma_map *map) |
135 | { | 171 | { |
136 | writel(map->channels[0] | S3C2412_DMAREQSEL_HW, | 172 | s3c2412_dma_direction(chan, map, chan->source); |
137 | chan->regs + S3C2412_DMA_DMAREQSEL); | ||
138 | } | 173 | } |
139 | 174 | ||
140 | static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { | 175 | static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { |
141 | .select = s3c2412_dma_select, | 176 | .select = s3c2412_dma_select, |
177 | .direction = s3c2412_dma_direction, | ||
142 | .dcon_mask = 0, | 178 | .dcon_mask = 0, |
143 | .map = s3c2412_dma_mappings, | 179 | .map = s3c2412_dma_mappings, |
144 | .map_size = ARRAY_SIZE(s3c2412_dma_mappings), | 180 | .map_size = ARRAY_SIZE(s3c2412_dma_mappings), |