7 files changed, 562 insertions, 23 deletions

diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 0b9d7ca49ec1..ed07c4149d82 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -9,6 +9,13 @@ config MACH_ANUBIS
           Say Y gere if you are using the Simtec Electronics ANUBIS
           development system
 
+config MACH_OSIRIS
+        bool "Simtec IM2440D20 (OSIRIS) module"
+        select CPU_S3C2440
+        help
+          Say Y here if you are using the Simtec IM2440D20 module, also
+          known as the Osiris.
+
 config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select CPU_S3C2410
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 1217bf00309c..1b3b476e5637 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_BAST_PC104_IRQ)	+= bast-irq.o
 # machine specific support
 
 obj-$(CONFIG_MACH_ANUBIS)       += mach-anubis.o
+obj-$(CONFIG_MACH_OSIRIS)       += mach-osiris.o
 obj-$(CONFIG_ARCH_BAST)         += mach-bast.o usb-simtec.o
 obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o
 obj-$(CONFIG_MACH_N30)          += mach-n30.o
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 08489efdaf06..fec02c92f95f 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -38,12 +38,14 @@
 #include <linux/ioport.h>
 #include <linux/clk.h>
 #include <linux/mutex.h>
+#include <linux/delay.h>
 
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/arch/regs-clock.h>
+#include <asm/arch/regs-gpio.h>
 
 #include "clock.h"
 #include "cpu.h"
@@ -51,7 +53,8 @@
 /* clock information */
 
 static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
+
+DEFINE_MUTEX(clocks_mutex);
 
 /* old functions */
 
@@ -178,12 +181,24 @@ unsigned long clk_get_rate(struct clk *clk)
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
+        if (!IS_ERR(clk) && clk->round_rate)
+                return (clk->round_rate)(clk, rate);
+
         return rate;
 }
 
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
-        return -EINVAL;
+        int ret;
+
+        if (IS_ERR(clk))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        ret = (clk->set_rate)(clk, rate);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
 }
 
 struct clk *clk_get_parent(struct clk *clk)
@@ -191,6 +206,23 @@ struct clk *clk_get_parent(struct clk *clk)
         return clk->parent;
 }
 
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = 0;
+
+        if (IS_ERR(clk))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+
+        if (clk->set_parent)
+                ret = (clk->set_parent)(clk, parent);
+
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+
 EXPORT_SYMBOL(clk_get);
 EXPORT_SYMBOL(clk_put);
 EXPORT_SYMBOL(clk_enable);
@@ -199,6 +231,29 @@ EXPORT_SYMBOL(clk_get_rate);
 EXPORT_SYMBOL(clk_round_rate);
 EXPORT_SYMBOL(clk_set_rate);
 EXPORT_SYMBOL(clk_get_parent);
+EXPORT_SYMBOL(clk_set_parent);
+
+/* base clock enable */
+
+static int s3c24xx_upll_enable(struct clk *clk, int enable)
+{
+        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
+        unsigned long orig = clkslow;
+
+        if (enable)
+                clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
+        else
+                clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
+
+        __raw_writel(clkslow, S3C2410_CLKSLOW);
+
+        /* if we started the UPLL, then allow to settle */
+
+        if (enable && !(orig & S3C2410_CLKSLOW_UCLK_OFF))
+                udelay(200);
+
+        return 0;
+}
 
 /* base clocks */
 
@@ -210,6 +265,14 @@ static struct clk clk_xtal = {
         .ctrlbit        = 0,
 };
 
+static struct clk clk_upll = {
+        .name           = "upll",
+        .id             = -1,
+        .parent         = NULL,
+        .enable         = s3c24xx_upll_enable,
+        .ctrlbit        = 0,
+};
+
 static struct clk clk_f = {
         .name           = "fclk",
         .id             = -1,
@@ -234,26 +297,124 @@ static struct clk clk_p = {
         .ctrlbit        = 0,
 };
 
+struct clk clk_usb_bus = {
+        .name           = "usb-bus",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = &clk_upll,
+};
+
 /* clocks that could be registered by external code */
 
+static int s3c24xx_dclk_enable(struct clk *clk, int enable)
+{
+        unsigned long dclkcon = __raw_readl(S3C2410_DCLKCON);
+
+        if (enable)
+                dclkcon |= clk->ctrlbit;
+        else
+                dclkcon &= ~clk->ctrlbit;
+
+        __raw_writel(dclkcon, S3C2410_DCLKCON);
+
+        return 0;
+}
+
+static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
+{
+        unsigned long dclkcon;
+        unsigned int uclk;
+
+        if (parent == &clk_upll)
+                uclk = 1;
+        else if (parent == &clk_p)
+                uclk = 0;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        dclkcon = __raw_readl(S3C2410_DCLKCON);
+
+        if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
+                if (uclk)
+                        dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
+                else
+                        dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
+        } else {
+                if (uclk)
+                        dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
+                else
+                        dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
+        }
+
+        __raw_writel(dclkcon, S3C2410_DCLKCON);
+
+        return 0;
+}
+
+
+static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
+{
+        unsigned long mask;
+        unsigned long source;
+
+        /* calculate the MISCCR setting for the clock */
+
+        if (parent == &clk_xtal)
+                source = S3C2410_MISCCR_CLK0_MPLL;
+        else if (parent == &clk_upll)
+                source = S3C2410_MISCCR_CLK0_UPLL;
+        else if (parent == &clk_f)
+                source = S3C2410_MISCCR_CLK0_FCLK;
+        else if (parent == &clk_p)
+                source = S3C2410_MISCCR_CLK0_PCLK;
+        else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
+                source = S3C2410_MISCCR_CLK0_DCLK0;
+        else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
+                source = S3C2410_MISCCR_CLK0_DCLK0;
+        else
+                return -EINVAL;
+
+        if (clk == &s3c24xx_dclk0)
+                mask = S3C2410_MISCCR_CLK0_MASK;
+        else {
+                source <<= 4;
+                mask = S3C2410_MISCCR_CLK1_MASK;
+        }
+
+        s3c2410_modify_misccr(mask, source);
+        return 0;
+}
+
+/* external clock definitions */
+
 struct clk s3c24xx_dclk0 = {
         .name           = "dclk0",
         .id             = -1,
+        .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
+        .enable         = s3c24xx_dclk_enable,
+        .set_parent     = s3c24xx_dclk_setparent,
 };
 
 struct clk s3c24xx_dclk1 = {
         .name           = "dclk1",
         .id             = -1,
+        .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
+        .enable         = s3c24xx_dclk_enable,
+        .set_parent     = s3c24xx_dclk_setparent,
 };
 
 struct clk s3c24xx_clkout0 = {
         .name           = "clkout0",
         .id             = -1,
+        .set_parent     = s3c24xx_clkout_setparent,
 };
 
 struct clk s3c24xx_clkout1 = {
         .name           = "clkout1",
         .id             = -1,
+        .set_parent     = s3c24xx_clkout_setparent,
 };
 
 struct clk s3c24xx_uclk = {
@@ -262,7 +423,7 @@ struct clk s3c24xx_uclk = {
 };
 
 
-/* clock definitions */
+/* standard clock definitions */
 
 static struct clk init_clocks[] = {
         {
@@ -374,7 +535,7 @@ int s3c24xx_register_clock(struct clk *clk)
 
         /* if this is a standard clock, set the usage state */
 
-        if (clk->ctrlbit) {
+        if (clk->ctrlbit && clk->enable == s3c24xx_clkcon_enable) {
                 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
 
                 clk->usage = (clkcon & clk->ctrlbit) ? 1 : 0;
@@ -396,6 +557,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
                                 unsigned long hclk,
                                 unsigned long pclk)
 {
+        unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
         unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
         struct clk *clkp = init_clocks;
         int ptr;
@@ -406,6 +568,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
         /* initialise the main system clocks */
 
         clk_xtal.rate = xtal;
+        clk_upll.rate = s3c2410_get_pll(upllcon, xtal);
 
         clk_h.rate = hclk;
         clk_p.rate = pclk;
@@ -439,6 +602,9 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
         if (s3c24xx_register_clock(&clk_xtal) < 0)
                 printk(KERN_ERR "failed to register master xtal\n");
 
+        if (s3c24xx_register_clock(&clk_upll) < 0)
+                printk(KERN_ERR "failed to register upll clock\n");
+
         if (s3c24xx_register_clock(&clk_f) < 0)
                 printk(KERN_ERR "failed to register cpu fclk\n");
 
@@ -448,6 +614,10 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
         if (s3c24xx_register_clock(&clk_p) < 0)
                 printk(KERN_ERR "failed to register cpu pclk\n");
 
+
+        if (s3c24xx_register_clock(&clk_usb_bus) < 0)
+                printk(KERN_ERR "failed to register usb bus clock\n");
+
         /* register clocks from clock array */
 
         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
diff --git a/arch/arm/mach-s3c2410/clock.h b/arch/arm/mach-s3c2410/clock.h
index eb5c95d1e7f2..01bb458bf8eb 100644
--- a/arch/arm/mach-s3c2410/clock.h
+++ b/arch/arm/mach-s3c2410/clock.h
@@ -19,7 +19,11 @@ struct clk {
         int                   usage;
         unsigned long         rate;
         unsigned long         ctrlbit;
+
         int                 (*enable)(struct clk *, int enable);
+        int                 (*set_rate)(struct clk *c, unsigned long rate);
+        unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
+        int                 (*set_parent)(struct clk *c, struct clk *parent);
 };
 
 /* other clocks which may be registered by board support */
@@ -30,11 +34,15 @@ extern struct clk s3c24xx_clkout0;
 extern struct clk s3c24xx_clkout1;
 extern struct clk s3c24xx_uclk;
 
+extern struct clk clk_usb_bus;
+
 /* exports for arch/arm/mach-s3c2410
  *
  * Please DO NOT use these outside of arch/arm/mach-s3c2410
 */
 
+extern struct mutex clocks_mutex;
+
 extern int s3c24xx_clkcon_enable(struct clk *clk, int enable);
 extern int s3c24xx_register_clock(struct clk *clk);
 
diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c
new file mode 100644
index 000000000000..ae0787557751
--- /dev/null
+++ b/arch/arm/mach-s3c2410/mach-osiris.c
@@ -0,0 +1,294 @@
+/* linux/arch/arm/mach-s3c2410/mach-osiris.c
+ *
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/osiris-map.h>
+#include <asm/arch/osiris-cpld.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-mem.h>
+#include <asm/arch/regs-lcd.h>
+#include <asm/arch/nand.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include "clock.h"
+#include "devs.h"
+#include "cpu.h"
+
+/* onboard perihpheral map */
+
+static struct map_desc osiris_iodesc[] __initdata = {
+  /* ISA IO areas (may be over-written later) */
+
+  {
+          .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
+          .pfn          = __phys_to_pfn(S3C2410_CS5),
+          .length       = SZ_16M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)S3C24XX_VA_ISA_WORD,
+          .pfn          = __phys_to_pfn(S3C2410_CS5),
+          .length       = SZ_16M,
+          .type         = MT_DEVICE,
+  },
+
+  /* CPLD control registers */
+
+  {
+          .virtual      = (u32)OSIRIS_VA_CTRL1,
+          .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
+          .length       = SZ_16K,
+          .type         = MT_DEVICE
+  }, {
+          .virtual      = (u32)OSIRIS_VA_CTRL2,
+          .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
+          .length       = SZ_16K,
+          .type         = MT_DEVICE
+  },
+};
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
+        [0] = {
+                .name           = "uclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+        [1] = {
+                .name           = "pclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0.
+        }
+};
+
+
+static struct s3c2410_uartcfg osiris_uartcfgs[] = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = osiris_serial_clocks,
+                .clocks_size = ARRAY_SIZE(osiris_serial_clocks)
+        },
+        [1] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = osiris_serial_clocks,
+                .clocks_size = ARRAY_SIZE(osiris_serial_clocks)
+        },
+};
+
+/* NAND Flash on Osiris board */
+
+static int external_map[]   = { 2 };
+static int chip0_map[]      = { 0 };
+static int chip1_map[]      = { 1 };
+
+static struct mtd_partition osiris_default_nand_part[] = {
+        [0] = {
+                .name   = "Boot Agent",
+                .size   = SZ_16K,
+                .offset = 0
+        },
+        [1] = {
+                .name   = "/boot",
+                .size   = SZ_4M - SZ_16K,
+                .offset = SZ_16K,
+        },
+        [2] = {
+                .name   = "user1",
+                .offset = SZ_4M,
+                .size   = SZ_32M - SZ_4M,
+        },
+        [3] = {
+                .name   = "user2",
+                .offset = SZ_32M,
+                .size   = MTDPART_SIZ_FULL,
+        }
+};
+
+/* the Osiris has 3 selectable slots for nand-flash, the two
+ * on-board chip areas, as well as the external slot.
+ *
+ * Note, there is no current hot-plug support for the External
+ * socket.
+*/
+
+static struct s3c2410_nand_set osiris_nand_sets[] = {
+        [1] = {
+                .name           = "External",
+                .nr_chips       = 1,
+                .nr_map         = external_map,
+                .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
+                .partitions     = osiris_default_nand_part
+        },
+        [0] = {
+                .name           = "chip0",
+                .nr_chips       = 1,
+                .nr_map         = chip0_map,
+                .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
+                .partitions     = osiris_default_nand_part
+        },
+        [2] = {
+                .name           = "chip1",
+                .nr_chips       = 1,
+                .nr_map         = chip1_map,
+                .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
+                .partitions     = osiris_default_nand_part
+        },
+};
+
+static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
+{
+        unsigned int tmp;
+
+        slot = set->nr_map[slot] & 3;
+
+        pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
+                 slot, set, set->nr_map);
+
+        tmp = __raw_readb(OSIRIS_VA_CTRL1);
+        tmp &= ~OSIRIS_CTRL1_NANDSEL;
+        tmp |= slot;
+
+        pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
+
+        __raw_writeb(tmp, OSIRIS_VA_CTRL1);
+}
+
+static struct s3c2410_platform_nand osiris_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 60,
+        .twrph1         = 60,
+        .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
+        .sets           = osiris_nand_sets,
+        .select_chip    = osiris_nand_select,
+};
+
+/* PCMCIA control and configuration */
+
+static struct resource osiris_pcmcia_resource[] = {
+        [0] = {
+                .start  = 0x0f000000,
+                .end    = 0x0f100000,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0x0c000000,
+                .end    = 0x0c100000,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device osiris_pcmcia = {
+        .name           = "osiris-pcmcia",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
+        .resource       = osiris_pcmcia_resource,
+};
+
+/* Standard Osiris devices */
+
+static struct platform_device *osiris_devices[] __initdata = {
+        &s3c_device_i2c,
+        &s3c_device_nand,
+        &osiris_pcmcia,
+};
+
+static struct clk *osiris_clocks[] = {
+        &s3c24xx_dclk0,
+        &s3c24xx_dclk1,
+        &s3c24xx_clkout0,
+        &s3c24xx_clkout1,
+        &s3c24xx_uclk,
+};
+
+static struct s3c24xx_board osiris_board __initdata = {
+        .devices       = osiris_devices,
+        .devices_count = ARRAY_SIZE(osiris_devices),
+        .clocks        = osiris_clocks,
+        .clocks_count  = ARRAY_SIZE(osiris_clocks)
+};
+
+static void __init osiris_map_io(void)
+{
+        unsigned long flags;
+
+        /* initialise the clocks */
+
+        s3c24xx_dclk0.parent = NULL;
+        s3c24xx_dclk0.rate   = 12*1000*1000;
+
+        s3c24xx_dclk1.parent = NULL;
+        s3c24xx_dclk1.rate   = 24*1000*1000;
+
+        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
+        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
+
+        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
+
+        s3c_device_nand.dev.platform_data = &osiris_nand_info;
+
+        s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
+        s3c24xx_init_clocks(0);
+        s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
+        s3c24xx_set_board(&osiris_board);
+
+        /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
+
+        local_irq_save(flags);
+        __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
+        local_irq_restore(flags);
+
+        /* write-protect line to the NAND */
+        s3c2410_gpio_setpin(S3C2410_GPA0, 1);
+}
+
+MACHINE_START(OSIRIS, "Simtec-OSIRIS")
+        /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .map_io         = osiris_map_io,
+        .init_irq       = s3c24xx_init_irq,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c
index b557a2be8a01..57a15974d4b5 100644
--- a/arch/arm/mach-s3c2410/s3c2440-clock.c
+++ b/arch/arm/mach-s3c2410/s3c2440-clock.c
@@ -31,6 +31,7 @@
 #include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/mutex.h>
 #include <linux/clk.h>
 
 #include <asm/hardware.h>
@@ -45,10 +46,47 @@
 
 /* S3C2440 extended clock support */
 
-static struct clk s3c2440_clk_upll = {
-        .name           = "upll",
-        .id             = -1,
-};
+static unsigned long s3c2440_camif_upll_round(struct clk *clk,
+                                              unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int div;
+
+        if (rate > parent_rate)
+                return parent_rate;
+
+        /* note, we remove the +/- 1 calculations for the divisor */
+
+        div = (parent_rate / rate) / 2;
+
+        if (div < 1)
+                div = 1;
+        else if (div > 16)
+                div = 16;
+
+        return parent_rate / (div * 2);
+}
+
+static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
+
+        rate = s3c2440_camif_upll_round(clk, rate);
+
+        camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
+
+        if (rate != parent_rate) {
+                camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
+                camdivn |= (((parent_rate / rate) / 2) - 1);
+        }
+
+        __raw_writel(camdivn, S3C2440_CAMDIVN);
+
+        return 0;
+}
+
+/* Extra S3C2440 clocks */
 
 static struct clk s3c2440_clk_cam = {
         .name           = "camif",
@@ -57,6 +95,13 @@ static struct clk s3c2440_clk_cam = {
         .ctrlbit        = S3C2440_CLKCON_CAMERA,
 };
 
+static struct clk s3c2440_clk_cam_upll = {
+        .name           = "camif-upll",
+        .id             = -1,
+        .set_rate       = s3c2440_camif_upll_setrate,
+        .round_rate     = s3c2440_camif_upll_round,
+};
+
 static struct clk s3c2440_clk_ac97 = {
         .name           = "ac97",
         .id             = -1,
@@ -66,38 +111,46 @@ static struct clk s3c2440_clk_ac97 = {
 
 static int s3c2440_clk_add(struct sys_device *sysdev)
 {
-        unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
         unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
+        unsigned long clkdivn;
         struct clk *clk_h;
         struct clk *clk_p;
-        struct clk *clk_xtal;
-
-        clk_xtal = clk_get(NULL, "xtal");
-        if (IS_ERR(clk_xtal)) {
-                printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
-                return -EINVAL;
-        }
-
-        s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
+        struct clk *clk_upll;
 
-        printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",
-               print_mhz(s3c2440_clk_upll.rate),
+        printk("S3C2440: Clock Support, DVS %s\n",
                (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
 
         clk_p = clk_get(NULL, "pclk");
         clk_h = clk_get(NULL, "hclk");
+        clk_upll = clk_get(NULL, "upll");
 
-        if (IS_ERR(clk_p) || IS_ERR(clk_h)) {
+        if (IS_ERR(clk_p) || IS_ERR(clk_h) || IS_ERR(clk_upll)) {
                 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
                 return -EINVAL;
         }
 
+        /* check rate of UPLL, and if it is near 96MHz, then change
+         * to using half the UPLL rate for the system */
+
+        if (clk_get_rate(clk_upll) > (94 * MHZ)) {
+                clk_usb_bus.rate = clk_get_rate(clk_upll) / 2;
+
+                mutex_lock(&clocks_mutex);
+
+                clkdivn = __raw_readl(S3C2410_CLKDIVN);
+                clkdivn |= S3C2440_CLKDIVN_UCLK;
+                __raw_writel(camdivn, S3C2410_CLKDIVN);
+
+                mutex_unlock(&clocks_mutex);
+        }
+
         s3c2440_clk_cam.parent = clk_h;
         s3c2440_clk_ac97.parent = clk_p;
+        s3c2440_clk_cam_upll.parent = clk_upll;
 
         s3c24xx_register_clock(&s3c2440_clk_ac97);
         s3c24xx_register_clock(&s3c2440_clk_cam);
-        s3c24xx_register_clock(&s3c2440_clk_upll);
+        s3c24xx_register_clock(&s3c2440_clk_cam_upll);
 
         clk_disable(&s3c2440_clk_ac97);
         clk_disable(&s3c2440_clk_cam);
diff --git a/arch/arm/mach-s3c2410/time.c b/arch/arm/mach-s3c2410/time.c
index 10a2976aefdd..9d7b799ea4a4 100644
--- a/arch/arm/mach-s3c2410/time.c
+++ b/arch/arm/mach-s3c2410/time.c
@@ -142,6 +142,12 @@ static struct irqaction s3c2410_timer_irq = {
         .handler        = s3c2410_timer_interrupt,
 };
 
+#define use_tclk1_12() ( \
+        machine_is_bast()       || \
+        machine_is_vr1000()     || \
+        machine_is_anubis()     || \
+        machine_is_osiris() )
+
 /*
  * Set up timer interrupt, and return the current time in seconds.
  *
@@ -165,7 +171,7 @@ static void s3c2410_timer_setup (void)
 
         /* configure the system for whichever machine is in use */
 
-        if (machine_is_bast() || machine_is_vr1000() || machine_is_anubis()) {
+        if (use_tclk1_12()) {
                 /* timer is at 12MHz, scaler is 1 */
                 timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
                 tcnt = 12000000 / HZ;