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-rw-r--r--arch/arm/mach-s3c2410/Kconfig18
-rw-r--r--arch/arm/mach-s3c2410/Makefile2
-rw-r--r--arch/arm/mach-s3c2410/cpu-freq.c159
-rw-r--r--arch/arm/mach-s3c2410/dma.c11
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-core.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/irqs.h6
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h8
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h4
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-mem.h10
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h23
-rw-r--r--arch/arm/mach-s3c2410/include/mach/spi.h3
-rw-r--r--arch/arm/mach-s3c2410/irq.c15
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c41
-rw-r--r--arch/arm/mach-s3c2410/pll.c95
-rw-r--r--arch/arm/mach-s3c2410/pm.c12
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c29
16 files changed, 433 insertions, 5 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 41bb65d5b91f..d8c023d4df30 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -12,6 +12,7 @@ config CPU_S3C2410
12 select S3C2410_GPIO 12 select S3C2410_GPIO
13 select CPU_LLSERIAL_S3C2410 13 select CPU_LLSERIAL_S3C2410
14 select S3C2410_PM if PM 14 select S3C2410_PM if PM
15 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
15 help 16 help
16 Support for S3C2410 and S3C2410A family from the S3C24XX line 17 Support for S3C2410 and S3C2410A family from the S3C24XX line
17 of Samsung Mobile CPUs. 18 of Samsung Mobile CPUs.
@@ -45,6 +46,22 @@ config MACH_BAST_IDE
45 Internal node for machines with an BAST style IDE 46 Internal node for machines with an BAST style IDE
46 interface 47 interface
47 48
49# cpu frequency scaling support
50
51config S3C2410_CPUFREQ
52 bool
53 depends on CPU_FREQ_S3C24XX && CPU_S3C2410
54 select S3C2410_CPUFREQ_UTILS
55 help
56 CPU Frequency scaling support for S3C2410
57
58config S3C2410_PLLTABLE
59 bool
60 depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
61 default y
62 help
63 Select the PLL table for the S3C2410
64
48menu "S3C2410 Machines" 65menu "S3C2410 Machines"
49 66
50config ARCH_SMDK2410 67config ARCH_SMDK2410
@@ -79,6 +96,7 @@ config MACH_N30
79config ARCH_BAST 96config ARCH_BAST
80 bool "Simtec Electronics BAST (EB2410ITX)" 97 bool "Simtec Electronics BAST (EB2410ITX)"
81 select CPU_S3C2410 98 select CPU_S3C2410
99 select S3C2410_IOTIMING if S3C2410_CPUFREQ
82 select PM_SIMTEC if PM 100 select PM_SIMTEC if PM
83 select SIMTEC_NOR 101 select SIMTEC_NOR
84 select MACH_BAST_IDE 102 select MACH_BAST_IDE
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index fca02f82711c..2ab5ba4b266f 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
15obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o 15obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
16obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o 16obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
17obj-$(CONFIG_S3C2410_GPIO) += gpio.o 17obj-$(CONFIG_S3C2410_GPIO) += gpio.o
18obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o
19obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
18 20
19# Machine support 21# Machine support
20 22
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
new file mode 100644
index 000000000000..9d1186877d08
--- /dev/null
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -0,0 +1,159 @@
1/* linux/arch/arm/mach-s3c2410/cpu-freq.c
2 *
3 * Copyright (c) 2006,2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 CPU Frequency scaling
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/cpufreq.h>
19#include <linux/sysdev.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/io.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <mach/regs-clock.h>
28
29#include <plat/cpu.h>
30#include <plat/clock.h>
31#include <plat/cpu-freq-core.h>
32
33/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
34
35static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
36{
37 u32 clkdiv = 0;
38
39 if (cfg->divs.h_divisor == 2)
40 clkdiv |= S3C2410_CLKDIVN_HDIVN;
41
42 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
43 clkdiv |= S3C2410_CLKDIVN_PDIVN;
44
45 __raw_writel(clkdiv, S3C2410_CLKDIVN);
46}
47
48static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
49{
50 unsigned long hclk, fclk, pclk;
51 unsigned int hdiv, pdiv;
52 unsigned long hclk_max;
53
54 fclk = cfg->freq.fclk;
55 hclk_max = cfg->max.hclk;
56
57 cfg->freq.armclk = fclk;
58
59 s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
60 __func__, fclk, hclk_max);
61
62 hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
63 hclk = fclk / hdiv;
64
65 if (hclk > cfg->max.hclk) {
66 s3c_freq_dbg("%s: hclk too big\n", __func__);
67 return -EINVAL;
68 }
69
70 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
71 pclk = hclk / pdiv;
72
73 if (pclk > cfg->max.pclk) {
74 s3c_freq_dbg("%s: pclk too big\n", __func__);
75 return -EINVAL;
76 }
77
78 pdiv *= hdiv;
79
80 /* record the result */
81 cfg->divs.p_divisor = pdiv;
82 cfg->divs.h_divisor = hdiv;
83
84 return 0 ;
85}
86
87static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
88 .max = {
89 .fclk = 200000000,
90 .hclk = 100000000,
91 .pclk = 50000000,
92 },
93
94 /* transition latency is about 5ms worst-case, so
95 * set 10ms to be sure */
96 .latency = 10000000,
97
98 .locktime_m = 150,
99 .locktime_u = 150,
100 .locktime_bits = 12,
101
102 .need_pll = 1,
103
104 .name = "s3c2410",
105 .calc_iotiming = s3c2410_iotiming_calc,
106 .set_iotiming = s3c2410_iotiming_set,
107 .get_iotiming = s3c2410_iotiming_get,
108 .resume_clocks = s3c2410_setup_clocks,
109
110 .set_fvco = s3c2410_set_fvco,
111 .set_refresh = s3c2410_cpufreq_setrefresh,
112 .set_divs = s3c2410_cpufreq_setdivs,
113 .calc_divs = s3c2410_cpufreq_calcdivs,
114
115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
116};
117
118static int s3c2410_cpufreq_add(struct sys_device *sysdev)
119{
120 return s3c_cpufreq_register(&s3c2410_cpufreq_info);
121}
122
123static struct sysdev_driver s3c2410_cpufreq_driver = {
124 .add = s3c2410_cpufreq_add,
125};
126
127static int __init s3c2410_cpufreq_init(void)
128{
129 return sysdev_driver_register(&s3c2410_sysclass,
130 &s3c2410_cpufreq_driver);
131}
132
133arch_initcall(s3c2410_cpufreq_init);
134
135static int s3c2410a_cpufreq_add(struct sys_device *sysdev)
136{
137 /* alter the maximum freq settings for S3C2410A. If a board knows
138 * it only has a maximum of 200, then it should register its own
139 * limits. */
140
141 s3c2410_cpufreq_info.max.fclk = 266000000;
142 s3c2410_cpufreq_info.max.hclk = 133000000;
143 s3c2410_cpufreq_info.max.pclk = 66500000;
144 s3c2410_cpufreq_info.name = "s3c2410a";
145
146 return s3c2410_cpufreq_add(sysdev);
147}
148
149static struct sysdev_driver s3c2410a_cpufreq_driver = {
150 .add = s3c2410a_cpufreq_add,
151};
152
153static int __init s3c2410a_cpufreq_init(void)
154{
155 return sysdev_driver_register(&s3c2410a_sysclass,
156 &s3c2410a_cpufreq_driver);
157}
158
159arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index dbf96e60d992..63b753f56c64 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -164,6 +164,17 @@ static int __init s3c2410_dma_drvinit(void)
164} 164}
165 165
166arch_initcall(s3c2410_dma_drvinit); 166arch_initcall(s3c2410_dma_drvinit);
167
168static struct sysdev_driver s3c2410a_dma_driver = {
169 .add = s3c2410_dma_add,
170};
171
172static int __init s3c2410a_dma_drvinit(void)
173{
174 return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
175}
176
177arch_initcall(s3c2410a_dma_drvinit);
167#endif 178#endif
168 179
169#if defined(CONFIG_CPU_S3C2442) 180#if defined(CONFIG_CPU_S3C2442)
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
index 8fe192081d3a..f8b879a7973c 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -28,7 +28,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
28 return NULL; 28 return NULL;
29 29
30 chip = &s3c24xx_gpios[pin/32]; 30 chip = &s3c24xx_gpios[pin/32];
31 return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL; 31 return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
32} 32}
33 33
34#endif /* __ASM_ARCH_GPIO_CORE_H */ 34#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 2a2384ffa7b1..6c12c6312ad8 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -164,6 +164,12 @@
164#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 164#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
165#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 165#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
166 166
167#ifdef CONFIG_CPU_S3C2440
168#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
169#else
170#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
171#endif
172
167/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ 173/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
168#define FIQ_START IRQ_EINT0 174#define FIQ_START IRQ_EINT0
169 175
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index e99b212cb1ca..b049e61460b6 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -67,6 +67,13 @@
67#define S3C2443_PA_HSMMC (0x4A800000) 67#define S3C2443_PA_HSMMC (0x4A800000)
68#define S3C2443_SZ_HSMMC (256) 68#define S3C2443_SZ_HSMMC (256)
69 69
70/* S3C2412 memory and IO controls */
71#define S3C2412_PA_SSMC (0x4F000000)
72#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
73
74#define S3C2412_PA_EBI (0x48800000)
75#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
76
70/* physical addresses of all the chip-select areas */ 77/* physical addresses of all the chip-select areas */
71 78
72#define S3C2410_CS0 (0x00000000) 79#define S3C2410_CS0 (0x00000000)
@@ -103,5 +110,6 @@
103#define S3C_PA_UART S3C24XX_PA_UART 110#define S3C_PA_UART S3C24XX_PA_UART
104#define S3C_PA_USBHOST S3C2410_PA_USBHOST 111#define S3C_PA_USBHOST S3C2410_PA_USBHOST
105#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC 112#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
113#define S3C_PA_NAND S3C24XX_PA_NAND
106 114
107#endif /* __ASM_ARCH_MAP_H */ 115#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index b278d0c45ccf..f6e8eec879c8 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -328,13 +328,15 @@
328 328
329#define S3C2410_GPD8_VD16 (0x02 << 16) 329#define S3C2410_GPD8_VD16 (0x02 << 16)
330#define S3C2400_GPD8_TOUT3 (0x02 << 16) 330#define S3C2400_GPD8_TOUT3 (0x02 << 16)
331#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
331 332
332#define S3C2410_GPD9_VD17 (0x02 << 18) 333#define S3C2410_GPD9_VD17 (0x02 << 18)
333#define S3C2400_GPD9_TCLK0 (0x02 << 18) 334#define S3C2400_GPD9_TCLK0 (0x02 << 18)
334#define S3C2410_GPD9_MASK (0x03 << 18) 335#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
335 336
336#define S3C2410_GPD10_VD18 (0x02 << 20) 337#define S3C2410_GPD10_VD18 (0x02 << 20)
337#define S3C2400_GPD10_nWAIT (0x02 << 20) 338#define S3C2400_GPD10_nWAIT (0x02 << 20)
339#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
338 340
339#define S3C2410_GPD11_VD19 (0x02 << 22) 341#define S3C2410_GPD11_VD19 (0x02 << 22)
340 342
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 57759804e2fa..7f7c52947963 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -73,6 +73,16 @@
73#define S3C2410_BWSCON_WS7 (1<<30) 73#define S3C2410_BWSCON_WS7 (1<<30)
74#define S3C2410_BWSCON_ST7 (1<<31) 74#define S3C2410_BWSCON_ST7 (1<<31)
75 75
76/* accesor functions for getting BANK(n) configuration. (n != 0) */
77
78#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
79
80#define S3C2410_BWSCON_DW8 (0)
81#define S3C2410_BWSCON_DW16 (1)
82#define S3C2410_BWSCON_DW32 (2)
83#define S3C2410_BWSCON_WS (1 << 2)
84#define S3C2410_BWSCON_ST (1 << 3)
85
76/* memory set (rom, ram) */ 86/* memory set (rom, ram) */
77#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) 87#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
78#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) 88#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
index a4bf27123170..fb6352515090 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
@@ -14,9 +14,11 @@
14#ifndef __ASM_ARM_REGS_S3C2412_MEM 14#ifndef __ASM_ARM_REGS_S3C2412_MEM
15#define __ASM_ARM_REGS_S3C2412_MEM 15#define __ASM_ARM_REGS_S3C2412_MEM
16 16
17#ifndef S3C2412_MEMREG
18#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) 17#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
19#endif 18#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
19
20#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
21#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
20 22
21#define S3C2412_BANKCFG S3C2412_MEMREG(0x00) 23#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
22#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) 24#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
@@ -26,4 +28,21 @@
26#define S3C2412_REFRESH S3C2412_MEMREG(0x10) 28#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
27#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) 29#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
28 30
31/* EBI control registers */
32
33#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
34#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
35
36/* SSMC control registers */
37
38#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
39#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
40#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
41#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
42#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
43#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
44#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
45#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
46#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
47
29#endif /* __ASM_ARM_REGS_S3C2412_MEM */ 48#endif /* __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
index 1d300fb112b1..193b39d654ed 100644
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
30extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, 30extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
31 int enable); 31 int enable);
32 32
33extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
34 int enable);
35
33#endif /* __ASM_ARCH_SPI_H */ 36#endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 92150399563b..5e2f35332056 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -39,9 +39,22 @@ static struct sysdev_driver s3c2410_irq_driver = {
39 .resume = s3c24xx_irq_resume, 39 .resume = s3c24xx_irq_resume,
40}; 40};
41 41
42static int s3c2410_irq_init(void) 42static int __init s3c2410_irq_init(void)
43{ 43{
44 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver); 44 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
45} 45}
46 46
47arch_initcall(s3c2410_irq_init); 47arch_initcall(s3c2410_irq_init);
48
49static struct sysdev_driver s3c2410a_irq_driver = {
50 .add = s3c2410_irq_add,
51 .suspend = s3c24xx_irq_suspend,
52 .resume = s3c24xx_irq_resume,
53};
54
55static int __init s3c2410a_irq_init(void)
56{
57 return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver);
58}
59
60arch_initcall(s3c2410a_irq_init);
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index ce3baba2cd7f..647c9adb018f 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -45,6 +45,7 @@
45#include <mach/regs-mem.h> 45#include <mach/regs-mem.h>
46#include <mach/regs-lcd.h> 46#include <mach/regs-lcd.h>
47 47
48#include <plat/hwmon.h>
48#include <plat/nand.h> 49#include <plat/nand.h>
49#include <plat/iic.h> 50#include <plat/iic.h>
50#include <mach/fb.h> 51#include <mach/fb.h>
@@ -59,6 +60,7 @@
59#include <plat/clock.h> 60#include <plat/clock.h>
60#include <plat/devs.h> 61#include <plat/devs.h>
61#include <plat/cpu.h> 62#include <plat/cpu.h>
63#include <plat/cpu-freq.h>
62 64
63#include "usb-simtec.h" 65#include "usb-simtec.h"
64#include "nor-simtec.h" 66#include "nor-simtec.h"
@@ -547,7 +549,35 @@ static struct i2c_board_info bast_i2c_devs[] __initdata = {
547 }, 549 },
548}; 550};
549 551
552static struct s3c_hwmon_pdata bast_hwmon_info = {
553 /* LCD contrast (0-6.6V) */
554 .in[0] = &(struct s3c_hwmon_chcfg) {
555 .name = "lcd-contrast",
556 .mult = 3300,
557 .div = 512,
558 },
559 /* LED current feedback */
560 .in[1] = &(struct s3c_hwmon_chcfg) {
561 .name = "led-feedback",
562 .mult = 3300,
563 .div = 1024,
564 },
565 /* LCD feedback (0-6.6V) */
566 .in[2] = &(struct s3c_hwmon_chcfg) {
567 .name = "lcd-feedback",
568 .mult = 3300,
569 .div = 512,
570 },
571 /* Vcore (1.8-2.0V), Vref 3.3V */
572 .in[3] = &(struct s3c_hwmon_chcfg) {
573 .name = "vcore",
574 .mult = 3300,
575 .div = 1024,
576 },
577};
578
550/* Standard BAST devices */ 579/* Standard BAST devices */
580// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
551 581
552static struct platform_device *bast_devices[] __initdata = { 582static struct platform_device *bast_devices[] __initdata = {
553 &s3c_device_usb, 583 &s3c_device_usb,
@@ -556,6 +586,8 @@ static struct platform_device *bast_devices[] __initdata = {
556 &s3c_device_i2c0, 586 &s3c_device_i2c0,
557 &s3c_device_rtc, 587 &s3c_device_rtc,
558 &s3c_device_nand, 588 &s3c_device_nand,
589 &s3c_device_adc,
590 &s3c_device_hwmon,
559 &bast_device_dm9k, 591 &bast_device_dm9k,
560 &bast_device_asix, 592 &bast_device_asix,
561 &bast_device_axpp, 593 &bast_device_axpp,
@@ -570,6 +602,12 @@ static struct clk *bast_clocks[] __initdata = {
570 &s3c24xx_uclk, 602 &s3c24xx_uclk,
571}; 603};
572 604
605static struct s3c_cpufreq_board __initdata bast_cpufreq = {
606 .refresh = 7800, /* 7.8usec */
607 .auto_io = 1,
608 .need_io = 1,
609};
610
573static void __init bast_map_io(void) 611static void __init bast_map_io(void)
574{ 612{
575 /* initialise the clocks */ 613 /* initialise the clocks */
@@ -588,6 +626,7 @@ static void __init bast_map_io(void)
588 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); 626 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
589 627
590 s3c_device_nand.dev.platform_data = &bast_nand_info; 628 s3c_device_nand.dev.platform_data = &bast_nand_info;
629 s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
591 630
592 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); 631 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
593 s3c24xx_init_clocks(0); 632 s3c24xx_init_clocks(0);
@@ -608,6 +647,8 @@ static void __init bast_init(void)
608 647
609 usb_simtec_init(); 648 usb_simtec_init();
610 nor_simtec_init(); 649 nor_simtec_init();
650
651 s3c_cpufreq_setboard(&bast_cpufreq);
611} 652}
612 653
613MACHINE_START(BAST, "Simtec-BAST") 654MACHINE_START(BAST, "Simtec-BAST")
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
new file mode 100644
index 000000000000..f178c2fd9d85
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -0,0 +1,95 @@
1/* arch/arm/mach-s3c2410/pll.c
2 *
3 * Copyright (c) 2006,2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@arm.linux.org.uk>
7 *
8 * S3C2410 CPU PLL tables
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23*/
24
25#include <linux/types.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/sysdev.h>
29#include <linux/list.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32
33#include <plat/cpu.h>
34#include <plat/cpu-freq-core.h>
35
36static struct cpufreq_frequency_table pll_vals_12MHz[] = {
37 { .frequency = 34000000, .index = PLLVAL(82, 2, 3), },
38 { .frequency = 45000000, .index = PLLVAL(82, 1, 3), },
39 { .frequency = 51000000, .index = PLLVAL(161, 3, 3), },
40 { .frequency = 48000000, .index = PLLVAL(120, 2, 3), },
41 { .frequency = 56000000, .index = PLLVAL(142, 2, 3), },
42 { .frequency = 68000000, .index = PLLVAL(82, 2, 2), },
43 { .frequency = 79000000, .index = PLLVAL(71, 1, 2), },
44 { .frequency = 85000000, .index = PLLVAL(105, 2, 2), },
45 { .frequency = 90000000, .index = PLLVAL(112, 2, 2), },
46 { .frequency = 101000000, .index = PLLVAL(127, 2, 2), },
47 { .frequency = 113000000, .index = PLLVAL(105, 1, 2), },
48 { .frequency = 118000000, .index = PLLVAL(150, 2, 2), },
49 { .frequency = 124000000, .index = PLLVAL(116, 1, 2), },
50 { .frequency = 135000000, .index = PLLVAL(82, 2, 1), },
51 { .frequency = 147000000, .index = PLLVAL(90, 2, 1), },
52 { .frequency = 152000000, .index = PLLVAL(68, 1, 1), },
53 { .frequency = 158000000, .index = PLLVAL(71, 1, 1), },
54 { .frequency = 170000000, .index = PLLVAL(77, 1, 1), },
55 { .frequency = 180000000, .index = PLLVAL(82, 1, 1), },
56 { .frequency = 186000000, .index = PLLVAL(85, 1, 1), },
57 { .frequency = 192000000, .index = PLLVAL(88, 1, 1), },
58 { .frequency = 203000000, .index = PLLVAL(161, 3, 1), },
59
60 /* 2410A extras */
61
62 { .frequency = 210000000, .index = PLLVAL(132, 2, 1), },
63 { .frequency = 226000000, .index = PLLVAL(105, 1, 1), },
64 { .frequency = 266000000, .index = PLLVAL(125, 1, 1), },
65 { .frequency = 268000000, .index = PLLVAL(126, 1, 1), },
66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), },
67};
68
69static int s3c2410_plls_add(struct sys_device *dev)
70{
71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
72}
73
74static struct sysdev_driver s3c2410_plls_drv = {
75 .add = s3c2410_plls_add,
76};
77
78static int __init s3c2410_pll_init(void)
79{
80 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv);
81
82}
83
84arch_initcall(s3c2410_pll_init);
85
86static struct sysdev_driver s3c2410a_plls_drv = {
87 .add = s3c2410_plls_add,
88};
89
90static int __init s3c2410a_pll_init(void)
91{
92 return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv);
93}
94
95arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 143e08a599d4..966119c8efee 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -119,6 +119,18 @@ static int __init s3c2410_pm_drvinit(void)
119} 119}
120 120
121arch_initcall(s3c2410_pm_drvinit); 121arch_initcall(s3c2410_pm_drvinit);
122
123static struct sysdev_driver s3c2410a_pm_driver = {
124 .add = s3c2410_pm_add,
125 .resume = s3c2410_pm_resume,
126};
127
128static int __init s3c2410a_pm_drvinit(void)
129{
130 return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
131}
132
133arch_initcall(s3c2410a_pm_drvinit);
122#endif 134#endif
123 135
124#if defined(CONFIG_CPU_S3C2440) 136#if defined(CONFIG_CPU_S3C2440)
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index feb141b1f915..91ba42f688ac 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -105,17 +105,33 @@ void __init_or_cpufreq s3c2410_setup_clocks(void)
105 s3c24xx_setup_clocks(fclk, hclk, pclk); 105 s3c24xx_setup_clocks(fclk, hclk, pclk);
106} 106}
107 107
108/* fake ARMCLK for use with cpufreq, etc. */
109
110static struct clk s3c2410_armclk = {
111 .name = "armclk",
112 .parent = &clk_f,
113 .id = -1,
114};
115
108void __init s3c2410_init_clocks(int xtal) 116void __init s3c2410_init_clocks(int xtal)
109{ 117{
110 s3c24xx_register_baseclocks(xtal); 118 s3c24xx_register_baseclocks(xtal);
111 s3c2410_setup_clocks(); 119 s3c2410_setup_clocks();
112 s3c2410_baseclk_add(); 120 s3c2410_baseclk_add();
121 s3c24xx_register_clock(&s3c2410_armclk);
113} 122}
114 123
115struct sysdev_class s3c2410_sysclass = { 124struct sysdev_class s3c2410_sysclass = {
116 .name = "s3c2410-core", 125 .name = "s3c2410-core",
117}; 126};
118 127
128/* Note, we would have liked to name this s3c2410-core, but we cannot
129 * register two sysdev_class with the same name.
130 */
131struct sysdev_class s3c2410a_sysclass = {
132 .name = "s3c2410a-core",
133};
134
119static struct sys_device s3c2410_sysdev = { 135static struct sys_device s3c2410_sysdev = {
120 .cls = &s3c2410_sysclass, 136 .cls = &s3c2410_sysclass,
121}; 137};
@@ -133,9 +149,22 @@ static int __init s3c2410_core_init(void)
133 149
134core_initcall(s3c2410_core_init); 150core_initcall(s3c2410_core_init);
135 151
152static int __init s3c2410a_core_init(void)
153{
154 return sysdev_class_register(&s3c2410a_sysclass);
155}
156
157core_initcall(s3c2410a_core_init);
158
136int __init s3c2410_init(void) 159int __init s3c2410_init(void)
137{ 160{
138 printk("S3C2410: Initialising architecture\n"); 161 printk("S3C2410: Initialising architecture\n");
139 162
140 return sysdev_register(&s3c2410_sysdev); 163 return sysdev_register(&s3c2410_sysdev);
141} 164}
165
166int __init s3c2410a_init(void)
167{
168 s3c2410_sysdev.cls = &s3c2410a_sysclass;
169 return s3c2410_init();
170}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 12:40:40 -0500