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-rw-r--r--arch/arm/mach-s3c2410/Kconfig8
-rw-r--r--arch/arm/mach-s3c2410/mach-anubis.c51
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c73
-rw-r--r--arch/arm/mach-s3c2410/mach-rx3715.c13
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2440.c23
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c56
6 files changed, 172 insertions, 52 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index c796bcdd6158..0b9d7ca49ec1 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -121,6 +121,14 @@ config S3C2410_BOOT_WATCHDOG
121 system resets depends on the value of PCLK. The timeout on an 121 system resets depends on the value of PCLK. The timeout on an
122 200MHz s3c2410 should be about 30 seconds. 122 200MHz s3c2410 should be about 30 seconds.
123 123
124config S3C2410_BOOT_ERROR_RESET
125 bool "S3C2410 Reboot on decompression error"
126 depends on ARCH_S3C2410
127 help
128 Say y here to use the watchdog to reset the system if the
129 kernel decompressor detects an error during decompression.
130
131
124comment "S3C2410 Setup" 132comment "S3C2410 Setup"
125 133
126config S3C2410_DMA 134config S3C2410_DMA
diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c
index 8390b685c2b6..0f81fc0c2f7f 100644
--- a/arch/arm/mach-s3c2410/mach-anubis.c
+++ b/arch/arm/mach-s3c2410/mach-anubis.c
@@ -56,8 +56,16 @@
56static struct map_desc anubis_iodesc[] __initdata = { 56static struct map_desc anubis_iodesc[] __initdata = {
57 /* ISA IO areas */ 57 /* ISA IO areas */
58 58
59 { (u32)S3C24XX_VA_ISA_BYTE, 0x0, SZ_16M, MT_DEVICE }, 59 {
60 { (u32)S3C24XX_VA_ISA_WORD, 0x0, SZ_16M, MT_DEVICE }, 60 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
61 .pfn = __phys_to_pfn(0x0),
62 .length = SZ_4M,
63 .type = MT_DEVICE
64 }, {
65 .virtual = (u32)S3C24XX_VA_ISA_WORD,
66 .pfn = __phys_to_pfn(0x0),
67 .length = SZ_4M, MT_DEVICE
68 },
61 69
62 /* we could possibly compress the next set down into a set of smaller tables 70 /* we could possibly compress the next set down into a set of smaller tables
63 * pagetables, but that would mean using an L2 section, and it still means 71 * pagetables, but that would mean using an L2 section, and it still means
@@ -66,16 +74,41 @@ static struct map_desc anubis_iodesc[] __initdata = {
66 74
67 /* CPLD control registers */ 75 /* CPLD control registers */
68 76
69 { (u32)ANUBIS_VA_CTRL1, ANUBIS_PA_CTRL1, SZ_4K, MT_DEVICE }, 77 {
70 { (u32)ANUBIS_VA_CTRL2, ANUBIS_PA_CTRL2, SZ_4K, MT_DEVICE }, 78 .virtual = (u32)ANUBIS_VA_CTRL1,
79 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
80 .length = SZ_4K,
81 .type = MT_DEVICE
82 }, {
83 .virtual = (u32)ANUBIS_VA_CTRL2,
84 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2),
85 .length = SZ_4K,
86 .type =MT_DEVICE
87 },
71 88
72 /* IDE drives */ 89 /* IDE drives */
73 90
74 { (u32)ANUBIS_IDEPRI, S3C2410_CS3, SZ_1M, MT_DEVICE }, 91 {
75 { (u32)ANUBIS_IDEPRIAUX, S3C2410_CS3+(1<<26), SZ_1M, MT_DEVICE }, 92 .virtual = (u32)ANUBIS_IDEPRI,
76 93 .pfn = __phys_to_pfn(S3C2410_CS3),
77 { (u32)ANUBIS_IDESEC, S3C2410_CS4, SZ_1M, MT_DEVICE }, 94 .length = SZ_1M,
78 { (u32)ANUBIS_IDESECAUX, S3C2410_CS4+(1<<26), SZ_1M, MT_DEVICE }, 95 .type = MT_DEVICE
96 }, {
97 .virtual = (u32)ANUBIS_IDEPRIAUX,
98 .pfn = __phys_to_pfn(S3C2410_CS3+(1<<26)),
99 .length = SZ_1M,
100 .type = MT_DEVICE
101 }, {
102 .virtual = (u32)ANUBIS_IDESEC,
103 .pfn = __phys_to_pfn(S3C2410_CS4),
104 .length = SZ_1M,
105 .type = MT_DEVICE
106 }, {
107 .virtual = (u32)ANUBIS_IDESECAUX,
108 .pfn = __phys_to_pfn(S3C2410_CS4+(1<<26)),
109 .length = SZ_1M,
110 .type = MT_DEVICE
111 },
79}; 112};
80 113
81#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK 114#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 0b71c896bbd1..1be2567a7486 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -89,32 +89,63 @@
89 89
90/* macros to modify the physical addresses for io space */ 90/* macros to modify the physical addresses for io space */
91 91
92#define PA_CS2(item) ((item) + S3C2410_CS2) 92#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
93#define PA_CS3(item) ((item) + S3C2410_CS3) 93#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
94#define PA_CS4(item) ((item) + S3C2410_CS4) 94#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
95#define PA_CS5(item) ((item) + S3C2410_CS5) 95#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
96 96
97static struct map_desc bast_iodesc[] __initdata = { 97static struct map_desc bast_iodesc[] __initdata = {
98 /* ISA IO areas */ 98 /* ISA IO areas */
99 99 {
100 { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 100 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
101 { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 101 .pfn = PA_CS2(BAST_PA_ISAIO),
102 102 .length = SZ_16M,
103 /* we could possibly compress the next set down into a set of smaller tables 103 .type = MT_DEVICE,
104 * pagetables, but that would mean using an L2 section, and it still means 104 }, {
105 * we cannot actually feed the same register to an LDR due to 16K spacing 105 .virtual = (u32)S3C24XX_VA_ISA_WORD,
106 */ 106 .pfn = PA_CS3(BAST_PA_ISAIO),
107 107 .length = SZ_16M,
108 .type = MT_DEVICE,
109 },
108 /* bast CPLD control registers, and external interrupt controls */ 110 /* bast CPLD control registers, and external interrupt controls */
109 { (u32)BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE }, 111 {
110 { (u32)BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE }, 112 .virtual = (u32)BAST_VA_CTRL1,
111 { (u32)BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE }, 113 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
112 { (u32)BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE }, 114 .length = SZ_1M,
113 115 .type = MT_DEVICE,
116 }, {
117 .virtual = (u32)BAST_VA_CTRL2,
118 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
119 .length = SZ_1M,
120 .type = MT_DEVICE,
121 }, {
122 .virtual = (u32)BAST_VA_CTRL3,
123 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
124 .length = SZ_1M,
125 .type = MT_DEVICE,
126 }, {
127 .virtual = (u32)BAST_VA_CTRL4,
128 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
129 .length = SZ_1M,
130 .type = MT_DEVICE,
131 },
114 /* PC104 IRQ mux */ 132 /* PC104 IRQ mux */
115 { (u32)BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE }, 133 {
116 { (u32)BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE }, 134 .virtual = (u32)BAST_VA_PC104_IRQREQ,
117 { (u32)BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE }, 135 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
136 .length = SZ_1M,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = (u32)BAST_VA_PC104_IRQRAW,
140 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
141 .length = SZ_1M,
142 .type = MT_DEVICE,
143 }, {
144 .virtual = (u32)BAST_VA_PC104_IRQMASK,
145 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
146 .length = SZ_1M,
147 .type = MT_DEVICE,
148 },
118 149
119 /* peripheral space... one for each of fast/slow/byte/16bit */ 150 /* peripheral space... one for each of fast/slow/byte/16bit */
120 /* note, ide is only decoded in word space, even though some registers 151 /* note, ide is only decoded in word space, even though some registers
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
index 24d69019a843..f8d86d1e16b6 100644
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ b/arch/arm/mach-s3c2410/mach-rx3715.c
@@ -56,8 +56,17 @@
56static struct map_desc rx3715_iodesc[] __initdata = { 56static struct map_desc rx3715_iodesc[] __initdata = {
57 /* dump ISA space somewhere unused */ 57 /* dump ISA space somewhere unused */
58 58
59 { (u32)S3C24XX_VA_ISA_WORD, S3C2410_CS3, SZ_16M, MT_DEVICE }, 59 {
60 { (u32)S3C24XX_VA_ISA_BYTE, S3C2410_CS3, SZ_16M, MT_DEVICE }, 60 .virtual = (u32)S3C24XX_VA_ISA_WORD,
61 .pfn = __phys_to_pfn(S3C2410_CS3),
62 .length = SZ_1M,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
66 .pfn = __phys_to_pfn(S3C2410_CS3),
67 .length = SZ_1M,
68 .type = MT_DEVICE,
69 },
61}; 70};
62 71
63 72
diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c
index d666c621ad06..4e31118533e6 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2440.c
@@ -58,8 +58,27 @@
58static struct map_desc smdk2440_iodesc[] __initdata = { 58static struct map_desc smdk2440_iodesc[] __initdata = {
59 /* ISA IO Space map (memory space selected by A24) */ 59 /* ISA IO Space map (memory space selected by A24) */
60 60
61 { (u32)S3C24XX_VA_ISA_WORD, S3C2410_CS2, SZ_16M, MT_DEVICE }, 61 {
62 { (u32)S3C24XX_VA_ISA_BYTE, S3C2410_CS2, SZ_16M, MT_DEVICE }, 62 .virtual = (u32)S3C24XX_VA_ISA_WORD,
63 .pfn = __phys_to_pfn(S3C2410_CS2),
64 .length = 0x10000,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
68 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
69 .length = SZ_4M,
70 .type = MT_DEVICE,
71 }, {
72 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
73 .pfn = __phys_to_pfn(S3C2410_CS2),
74 .length = 0x10000,
75 .type = MT_DEVICE,
76 }, {
77 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
78 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
79 .length = SZ_4M,
80 .type = MT_DEVICE,
81 }
63}; 82};
64 83
65#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK 84#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 46b259673c18..ae7e099bf6c8 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -74,27 +74,47 @@
74 74
75/* macros to modify the physical addresses for io space */ 75/* macros to modify the physical addresses for io space */
76 76
77#define PA_CS2(item) ((item) + S3C2410_CS2) 77#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
78#define PA_CS3(item) ((item) + S3C2410_CS3) 78#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
79#define PA_CS4(item) ((item) + S3C2410_CS4) 79#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
80#define PA_CS5(item) ((item) + S3C2410_CS5) 80#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
81 81
82static struct map_desc vr1000_iodesc[] __initdata = { 82static struct map_desc vr1000_iodesc[] __initdata = {
83 /* ISA IO areas */ 83 /* ISA IO areas */
84 84 {
85 { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 85 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
86 { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 86 .pfn = PA_CS2(BAST_PA_ISAIO),
87 87 .length = SZ_16M,
88 /* we could possibly compress the next set down into a set of smaller tables 88 .type = MT_DEVICE,
89 * pagetables, but that would mean using an L2 section, and it still means 89 }, {
90 * we cannot actually feed the same register to an LDR due to 16K spacing 90 .virtual = (u32)S3C24XX_VA_ISA_WORD,
91 */ 91 .pfn = PA_CS3(BAST_PA_ISAIO),
92 92 .length = SZ_16M,
93 /* bast CPLD control registers, and external interrupt controls */ 93 .type = MT_DEVICE,
94 { (u32)VR1000_VA_CTRL1, VR1000_PA_CTRL1, SZ_1M, MT_DEVICE }, 94 },
95 { (u32)VR1000_VA_CTRL2, VR1000_PA_CTRL2, SZ_1M, MT_DEVICE }, 95
96 { (u32)VR1000_VA_CTRL3, VR1000_PA_CTRL3, SZ_1M, MT_DEVICE }, 96 /* CPLD control registers, and external interrupt controls */
97 { (u32)VR1000_VA_CTRL4, VR1000_PA_CTRL4, SZ_1M, MT_DEVICE }, 97 {
98 .virtual = (u32)VR1000_VA_CTRL1,
99 .pfn = __phys_to_pfn(VR1000_PA_CTRL1),
100 .length = SZ_1M,
101 .type = MT_DEVICE,
102 }, {
103 .virtual = (u32)VR1000_VA_CTRL2,
104 .pfn = __phys_to_pfn(VR1000_PA_CTRL2),
105 .length = SZ_1M,
106 .type = MT_DEVICE,
107 }, {
108 .virtual = (u32)VR1000_VA_CTRL3,
109 .pfn = __phys_to_pfn(VR1000_PA_CTRL3),
110 .length = SZ_1M,
111 .type = MT_DEVICE,
112 }, {
113 .virtual = (u32)VR1000_VA_CTRL4,
114 .pfn = __phys_to_pfn(VR1000_PA_CTRL4),
115 .length = SZ_1M,
116 .type = MT_DEVICE,
117 },
98 118
99 /* peripheral space... one for each of fast/slow/byte/16bit */ 119 /* peripheral space... one for each of fast/slow/byte/16bit */
100 /* note, ide is only decoded in word space, even though some registers 120 /* note, ide is only decoded in word space, even though some registers
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 05:07:07 -0500