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-rw-r--r--arch/arm/mach-s3c2410/Kconfig10
-rw-r--r--arch/arm/mach-s3c2410/Makefile1
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c8
-rw-r--r--arch/arm/mach-s3c2410/dma.c4
-rw-r--r--arch/arm/mach-s3c2410/gpio.c21
-rw-r--r--arch/arm/mach-s3c2410/irq.c63
-rw-r--r--arch/arm/mach-s3c2410/irq.h2
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-osiris.c9
-rw-r--r--arch/arm/mach-s3c2410/mach-rx3715.c3
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c50
-rw-r--r--arch/arm/mach-s3c2410/pm-h1940.S33
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-gpio.c19
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-pm.c30
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-irq.c4
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c10
-rw-r--r--arch/arm/mach-s3c2410/s3c244x-irq.c12
17 files changed, 205 insertions, 82 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 63965c78de8c..9f46bf330bc8 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -41,9 +41,16 @@ config BAST_PC104_IRQ
41 Say Y here to enable the PC104 IRQ routing on the 41 Say Y here to enable the PC104 IRQ routing on the
42 Simtec BAST (EB2410ITX) 42 Simtec BAST (EB2410ITX)
43 43
44config PM_H1940
45 bool
46 depends on PM
47 help
48 Internal node for H1940 and related PM
49
44config ARCH_H1940 50config ARCH_H1940
45 bool "IPAQ H1940" 51 bool "IPAQ H1940"
46 select CPU_S3C2410 52 select CPU_S3C2410
53 select PM_H1940
47 help 54 help
48 Say Y here if you are using the HP IPAQ H1940 55 Say Y here if you are using the HP IPAQ H1940
49 56
@@ -91,7 +98,7 @@ config SMDK2440_CPU2442
91config MACH_S3C2413 98config MACH_S3C2413
92 bool 99 bool
93 help 100 help
94 Internal node for S3C2413 verison of SMDK2413, so that 101 Internal node for S3C2413 version of SMDK2413, so that
95 machine_is_s3c2413() will work when MACH_SMDK2413 is 102 machine_is_s3c2413() will work when MACH_SMDK2413 is
96 selected 103 selected
97 104
@@ -115,6 +122,7 @@ config MACH_VR1000
115config MACH_RX3715 122config MACH_RX3715
116 bool "HP iPAQ rx3715" 123 bool "HP iPAQ rx3715"
117 select CPU_S3C2440 124 select CPU_S3C2440
125 select PM_H1940
118 help 126 help
119 Say Y here if you are using the HP iPAQ rx3715. 127 Say Y here if you are using the HP iPAQ rx3715.
120 128
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index d66013365b6b..27663e28cc88 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += s3c2410-dma.o
31 31
32obj-$(CONFIG_PM) += pm.o sleep.o 32obj-$(CONFIG_PM) += pm.o sleep.o
33obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 33obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
34obj-$(CONFIG_PM_H1940) += pm-h1940.o
34 35
35# S3C2412 support 36# S3C2412 support
36obj-$(CONFIG_CPU_S3C2412) += s3c2412.o 37obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 23d5beea5568..379efe70778c 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -88,7 +88,7 @@ bast_pc104_mask(unsigned int irqno)
88static void 88static void
89bast_pc104_maskack(unsigned int irqno) 89bast_pc104_maskack(unsigned int irqno)
90{ 90{
91 struct irqdesc *desc = irq_desc + IRQ_ISA; 91 struct irq_desc *desc = irq_desc + IRQ_ISA;
92 92
93 bast_pc104_mask(irqno); 93 bast_pc104_mask(irqno);
94 desc->chip->ack(IRQ_ISA); 94 desc->chip->ack(IRQ_ISA);
@@ -104,7 +104,7 @@ bast_pc104_unmask(unsigned int irqno)
104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK); 104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
105} 105}
106 106
107static struct irqchip bast_pc104_chip = { 107static struct irq_chip bast_pc104_chip = {
108 .mask = bast_pc104_mask, 108 .mask = bast_pc104_mask,
109 .unmask = bast_pc104_unmask, 109 .unmask = bast_pc104_unmask,
110 .ack = bast_pc104_maskack 110 .ack = bast_pc104_maskack
@@ -112,7 +112,7 @@ static struct irqchip bast_pc104_chip = {
112 112
113static void 113static void
114bast_irq_pc104_demux(unsigned int irq, 114bast_irq_pc104_demux(unsigned int irq,
115 struct irqdesc *desc) 115 struct irq_desc *desc)
116{ 116{
117 unsigned int stat; 117 unsigned int stat;
118 unsigned int irqno; 118 unsigned int irqno;
@@ -157,7 +157,7 @@ static __init int bast_irq_init(void)
157 unsigned int irqno = bast_pc104_irqs[i]; 157 unsigned int irqno = bast_pc104_irqs[i];
158 158
159 set_irq_chip(irqno, &bast_pc104_chip); 159 set_irq_chip(irqno, &bast_pc104_chip);
160 set_irq_handler(irqno, do_level_IRQ); 160 set_irq_handler(irqno, handle_level_irq);
161 set_irq_flags(irqno, IRQF_VALID); 161 set_irq_flags(irqno, IRQF_VALID);
162 } 162 }
163 } 163 }
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 3d211dc2f2f9..01abb0ace234 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -40,7 +40,7 @@
40 40
41/* io map for dma */ 41/* io map for dma */
42static void __iomem *dma_base; 42static void __iomem *dma_base;
43static kmem_cache_t *dma_kmem; 43static struct kmem_cache *dma_kmem;
44 44
45struct s3c24xx_dma_selection dma_sel; 45struct s3c24xx_dma_selection dma_sel;
46 46
@@ -1271,7 +1271,7 @@ struct sysdev_class dma_sysclass = {
1271 1271
1272/* kmem cache implementation */ 1272/* kmem cache implementation */
1273 1273
1274static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f) 1274static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f)
1275{ 1275{
1276 memset(p, 0, sizeof(struct s3c2410_dma_buf)); 1276 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1277} 1277}
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index db6393c99860..ba346546150b 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -3,7 +3,7 @@
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C2410 GPIO support 6 * S3C24XX GPIO support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -163,3 +163,22 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
163} 163}
164 164
165EXPORT_SYMBOL(s3c2410_modify_misccr); 165EXPORT_SYMBOL(s3c2410_modify_misccr);
166
167int s3c2410_gpio_getirq(unsigned int pin)
168{
169 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
170 return -1; /* not valid interrupts */
171
172 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
173 return -1; /* not valid pin */
174
175 if (pin < S3C2410_GPF4)
176 return (pin - S3C2410_GPF0) + IRQ_EINT0;
177
178 if (pin < S3C2410_GPG0)
179 return (pin - S3C2410_GPF4) + IRQ_EINT4;
180
181 return (pin - S3C2410_GPG0) + IRQ_EINT8;
182}
183
184EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 683b3491ba3c..3c0ed7871c55 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
180 __raw_writel(mask, S3C2410_INTMSK); 180 __raw_writel(mask, S3C2410_INTMSK);
181} 181}
182 182
183struct irqchip s3c_irq_level_chip = { 183struct irq_chip s3c_irq_level_chip = {
184 .name = "s3c-level", 184 .name = "s3c-level",
185 .ack = s3c_irq_maskack, 185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask, 186 .mask = s3c_irq_mask,
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = {
188 .set_wake = s3c_irq_wake 188 .set_wake = s3c_irq_wake
189}; 189};
190 190
191static struct irqchip s3c_irq_chip = { 191static struct irq_chip s3c_irq_chip = {
192 .name = "s3c", 192 .name = "s3c",
193 .ack = s3c_irq_ack, 193 .ack = s3c_irq_ack,
194 .mask = s3c_irq_mask, 194 .mask = s3c_irq_mask,
@@ -206,18 +206,6 @@ s3c_irqext_mask(unsigned int irqno)
206 mask = __raw_readl(S3C24XX_EINTMASK); 206 mask = __raw_readl(S3C24XX_EINTMASK);
207 mask |= ( 1UL << irqno); 207 mask |= ( 1UL << irqno);
208 __raw_writel(mask, S3C24XX_EINTMASK); 208 __raw_writel(mask, S3C24XX_EINTMASK);
209
210 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
211 /* check to see if all need masking */
212
213 if ((mask & (0xf << 4)) == (0xf << 4)) {
214 /* all masked, mask the parent */
215 s3c_irq_mask(IRQ_EINT4t7);
216 }
217 } else {
218 /* todo: the same check as above for the rest of the irq regs...*/
219
220 }
221} 209}
222 210
223static void 211static void
@@ -229,7 +217,6 @@ s3c_irqext_ack(unsigned int irqno)
229 217
230 bit = 1UL << (irqno - EXTINT_OFF); 218 bit = 1UL << (irqno - EXTINT_OFF);
231 219
232
233 mask = __raw_readl(S3C24XX_EINTMASK); 220 mask = __raw_readl(S3C24XX_EINTMASK);
234 221
235 __raw_writel(bit, S3C24XX_EINTPEND); 222 __raw_writel(bit, S3C24XX_EINTPEND);
@@ -258,8 +245,6 @@ s3c_irqext_unmask(unsigned int irqno)
258 mask = __raw_readl(S3C24XX_EINTMASK); 245 mask = __raw_readl(S3C24XX_EINTMASK);
259 mask &= ~( 1UL << irqno); 246 mask &= ~( 1UL << irqno);
260 __raw_writel(mask, S3C24XX_EINTMASK); 247 __raw_writel(mask, S3C24XX_EINTMASK);
261
262 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
263} 248}
264 249
265int 250int
@@ -344,7 +329,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
344 return 0; 329 return 0;
345} 330}
346 331
347static struct irqchip s3c_irqext_chip = { 332static struct irq_chip s3c_irqext_chip = {
348 .name = "s3c-ext", 333 .name = "s3c-ext",
349 .mask = s3c_irqext_mask, 334 .mask = s3c_irqext_mask,
350 .unmask = s3c_irqext_unmask, 335 .unmask = s3c_irqext_unmask,
@@ -353,7 +338,7 @@ static struct irqchip s3c_irqext_chip = {
353 .set_wake = s3c_irqext_wake 338 .set_wake = s3c_irqext_wake
354}; 339};
355 340
356static struct irqchip s3c_irq_eint0t4 = { 341static struct irq_chip s3c_irq_eint0t4 = {
357 .name = "s3c-ext0", 342 .name = "s3c-ext0",
358 .ack = s3c_irq_ack, 343 .ack = s3c_irq_ack,
359 .mask = s3c_irq_mask, 344 .mask = s3c_irq_mask,
@@ -390,7 +375,7 @@ s3c_irq_uart0_ack(unsigned int irqno)
390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); 375 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
391} 376}
392 377
393static struct irqchip s3c_irq_uart0 = { 378static struct irq_chip s3c_irq_uart0 = {
394 .name = "s3c-uart0", 379 .name = "s3c-uart0",
395 .mask = s3c_irq_uart0_mask, 380 .mask = s3c_irq_uart0_mask,
396 .unmask = s3c_irq_uart0_unmask, 381 .unmask = s3c_irq_uart0_unmask,
@@ -417,7 +402,7 @@ s3c_irq_uart1_ack(unsigned int irqno)
417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); 402 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
418} 403}
419 404
420static struct irqchip s3c_irq_uart1 = { 405static struct irq_chip s3c_irq_uart1 = {
421 .name = "s3c-uart1", 406 .name = "s3c-uart1",
422 .mask = s3c_irq_uart1_mask, 407 .mask = s3c_irq_uart1_mask,
423 .unmask = s3c_irq_uart1_unmask, 408 .unmask = s3c_irq_uart1_unmask,
@@ -444,7 +429,7 @@ s3c_irq_uart2_ack(unsigned int irqno)
444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); 429 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
445} 430}
446 431
447static struct irqchip s3c_irq_uart2 = { 432static struct irq_chip s3c_irq_uart2 = {
448 .name = "s3c-uart2", 433 .name = "s3c-uart2",
449 .mask = s3c_irq_uart2_mask, 434 .mask = s3c_irq_uart2_mask,
450 .unmask = s3c_irq_uart2_unmask, 435 .unmask = s3c_irq_uart2_unmask,
@@ -471,7 +456,7 @@ s3c_irq_adc_ack(unsigned int irqno)
471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); 456 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
472} 457}
473 458
474static struct irqchip s3c_irq_adc = { 459static struct irq_chip s3c_irq_adc = {
475 .name = "s3c-adc", 460 .name = "s3c-adc",
476 .mask = s3c_irq_adc_mask, 461 .mask = s3c_irq_adc_mask,
477 .unmask = s3c_irq_adc_unmask, 462 .unmask = s3c_irq_adc_unmask,
@@ -480,11 +465,11 @@ static struct irqchip s3c_irq_adc = {
480 465
481/* irq demux for adc */ 466/* irq demux for adc */
482static void s3c_irq_demux_adc(unsigned int irq, 467static void s3c_irq_demux_adc(unsigned int irq,
483 struct irqdesc *desc) 468 struct irq_desc *desc)
484{ 469{
485 unsigned int subsrc, submsk; 470 unsigned int subsrc, submsk;
486 unsigned int offset = 9; 471 unsigned int offset = 9;
487 struct irqdesc *mydesc; 472 struct irq_desc *mydesc;
488 473
489 /* read the current pending interrupts, and the mask 474 /* read the current pending interrupts, and the mask
490 * for what it is available */ 475 * for what it is available */
@@ -512,7 +497,7 @@ static void s3c_irq_demux_uart(unsigned int start)
512{ 497{
513 unsigned int subsrc, submsk; 498 unsigned int subsrc, submsk;
514 unsigned int offset = start - IRQ_S3CUART_RX0; 499 unsigned int offset = start - IRQ_S3CUART_RX0;
515 struct irqdesc *desc; 500 struct irq_desc *desc;
516 501
517 /* read the current pending interrupts, and the mask 502 /* read the current pending interrupts, and the mask
518 * for what it is available */ 503 * for what it is available */
@@ -549,7 +534,7 @@ static void s3c_irq_demux_uart(unsigned int start)
549 534
550static void 535static void
551s3c_irq_demux_uart0(unsigned int irq, 536s3c_irq_demux_uart0(unsigned int irq,
552 struct irqdesc *desc) 537 struct irq_desc *desc)
553{ 538{
554 irq = irq; 539 irq = irq;
555 s3c_irq_demux_uart(IRQ_S3CUART_RX0); 540 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@@ -557,7 +542,7 @@ s3c_irq_demux_uart0(unsigned int irq,
557 542
558static void 543static void
559s3c_irq_demux_uart1(unsigned int irq, 544s3c_irq_demux_uart1(unsigned int irq,
560 struct irqdesc *desc) 545 struct irq_desc *desc)
561{ 546{
562 irq = irq; 547 irq = irq;
563 s3c_irq_demux_uart(IRQ_S3CUART_RX1); 548 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@@ -565,7 +550,7 @@ s3c_irq_demux_uart1(unsigned int irq,
565 550
566static void 551static void
567s3c_irq_demux_uart2(unsigned int irq, 552s3c_irq_demux_uart2(unsigned int irq,
568 struct irqdesc *desc) 553 struct irq_desc *desc)
569{ 554{
570 irq = irq; 555 irq = irq;
571 s3c_irq_demux_uart(IRQ_S3CUART_RX2); 556 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@@ -573,7 +558,7 @@ s3c_irq_demux_uart2(unsigned int irq,
573 558
574static void 559static void
575s3c_irq_demux_extint8(unsigned int irq, 560s3c_irq_demux_extint8(unsigned int irq,
576 struct irqdesc *desc) 561 struct irq_desc *desc)
577{ 562{
578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 563 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 564 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -595,7 +580,7 @@ s3c_irq_demux_extint8(unsigned int irq,
595 580
596static void 581static void
597s3c_irq_demux_extint4t7(unsigned int irq, 582s3c_irq_demux_extint4t7(unsigned int irq,
598 struct irqdesc *desc) 583 struct irq_desc *desc)
599{ 584{
600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 585 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 586 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -738,7 +723,7 @@ void __init s3c24xx_init_irq(void)
738 case IRQ_UART2: 723 case IRQ_UART2:
739 case IRQ_ADCPARENT: 724 case IRQ_ADCPARENT:
740 set_irq_chip(irqno, &s3c_irq_level_chip); 725 set_irq_chip(irqno, &s3c_irq_level_chip);
741 set_irq_handler(irqno, do_level_IRQ); 726 set_irq_handler(irqno, handle_level_irq);
742 break; 727 break;
743 728
744 case IRQ_RESERVED6: 729 case IRQ_RESERVED6:
@@ -749,7 +734,7 @@ void __init s3c24xx_init_irq(void)
749 default: 734 default:
750 //irqdbf("registering irq %d (s3c irq)\n", irqno); 735 //irqdbf("registering irq %d (s3c irq)\n", irqno);
751 set_irq_chip(irqno, &s3c_irq_chip); 736 set_irq_chip(irqno, &s3c_irq_chip);
752 set_irq_handler(irqno, do_edge_IRQ); 737 set_irq_handler(irqno, handle_edge_irq);
753 set_irq_flags(irqno, IRQF_VALID); 738 set_irq_flags(irqno, IRQF_VALID);
754 } 739 }
755 } 740 }
@@ -769,14 +754,14 @@ void __init s3c24xx_init_irq(void)
769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 754 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
770 irqdbf("registering irq %d (ext int)\n", irqno); 755 irqdbf("registering irq %d (ext int)\n", irqno);
771 set_irq_chip(irqno, &s3c_irq_eint0t4); 756 set_irq_chip(irqno, &s3c_irq_eint0t4);
772 set_irq_handler(irqno, do_edge_IRQ); 757 set_irq_handler(irqno, handle_edge_irq);
773 set_irq_flags(irqno, IRQF_VALID); 758 set_irq_flags(irqno, IRQF_VALID);
774 } 759 }
775 760
776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 761 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
777 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 762 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
778 set_irq_chip(irqno, &s3c_irqext_chip); 763 set_irq_chip(irqno, &s3c_irqext_chip);
779 set_irq_handler(irqno, do_edge_IRQ); 764 set_irq_handler(irqno, handle_edge_irq);
780 set_irq_flags(irqno, IRQF_VALID); 765 set_irq_flags(irqno, IRQF_VALID);
781 } 766 }
782 767
@@ -787,28 +772,28 @@ void __init s3c24xx_init_irq(void)
787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 772 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 773 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
789 set_irq_chip(irqno, &s3c_irq_uart0); 774 set_irq_chip(irqno, &s3c_irq_uart0);
790 set_irq_handler(irqno, do_level_IRQ); 775 set_irq_handler(irqno, handle_level_irq);
791 set_irq_flags(irqno, IRQF_VALID); 776 set_irq_flags(irqno, IRQF_VALID);
792 } 777 }
793 778
794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 779 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 780 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
796 set_irq_chip(irqno, &s3c_irq_uart1); 781 set_irq_chip(irqno, &s3c_irq_uart1);
797 set_irq_handler(irqno, do_level_IRQ); 782 set_irq_handler(irqno, handle_level_irq);
798 set_irq_flags(irqno, IRQF_VALID); 783 set_irq_flags(irqno, IRQF_VALID);
799 } 784 }
800 785
801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 786 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 787 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
803 set_irq_chip(irqno, &s3c_irq_uart2); 788 set_irq_chip(irqno, &s3c_irq_uart2);
804 set_irq_handler(irqno, do_level_IRQ); 789 set_irq_handler(irqno, handle_level_irq);
805 set_irq_flags(irqno, IRQF_VALID); 790 set_irq_flags(irqno, IRQF_VALID);
806 } 791 }
807 792
808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 793 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
809 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 794 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
810 set_irq_chip(irqno, &s3c_irq_adc); 795 set_irq_chip(irqno, &s3c_irq_adc);
811 set_irq_handler(irqno, do_edge_IRQ); 796 set_irq_handler(irqno, handle_edge_irq);
812 set_irq_flags(irqno, IRQF_VALID); 797 set_irq_flags(irqno, IRQF_VALID);
813 } 798 }
814 799
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
index 842a9f42c97b..3686a0082245 100644
--- a/arch/arm/mach-s3c2410/irq.h
+++ b/arch/arm/mach-s3c2410/irq.h
@@ -17,7 +17,7 @@
17 17
18#define EXTINT_OFF (IRQ_EINT4 - 4) 18#define EXTINT_OFF (IRQ_EINT4 - 4)
19 19
20extern struct irqchip s3c_irq_level_chip; 20extern struct irq_chip s3c_irq_level_chip;
21 21
22static inline void 22static inline void
23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, 23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 8c895c077d22..f5b98099a5d9 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -33,6 +33,7 @@
33#include <asm/arch/regs-serial.h> 33#include <asm/arch/regs-serial.h>
34#include <asm/arch/regs-lcd.h> 34#include <asm/arch/regs-lcd.h>
35 35
36#include <asm/arch/h1940.h>
36#include <asm/arch/h1940-latch.h> 37#include <asm/arch/h1940-latch.h>
37#include <asm/arch/fb.h> 38#include <asm/arch/fb.h>
38 39
@@ -41,6 +42,7 @@
41#include "clock.h" 42#include "clock.h"
42#include "devs.h" 43#include "devs.h"
43#include "cpu.h" 44#include "cpu.h"
45#include "pm.h"
44 46
45static struct map_desc h1940_iodesc[] __initdata = { 47static struct map_desc h1940_iodesc[] __initdata = {
46 [0] = { 48 [0] = {
@@ -164,12 +166,16 @@ static void __init h1940_map_io(void)
164 s3c24xx_init_clocks(0); 166 s3c24xx_init_clocks(0);
165 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); 167 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
166 s3c24xx_set_board(&h1940_board); 168 s3c24xx_set_board(&h1940_board);
169
170 /* setup PM */
171
172 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
173 s3c2410_pm_init();
167} 174}
168 175
169static void __init h1940_init_irq(void) 176static void __init h1940_init_irq(void)
170{ 177{
171 s3c24xx_init_irq(); 178 s3c24xx_init_irq();
172
173} 179}
174 180
175static void __init h1940_init(void) 181static void __init h1940_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c
index e193ba69e652..a4ab144e7292 100644
--- a/arch/arm/mach-s3c2410/mach-osiris.c
+++ b/arch/arm/mach-s3c2410/mach-osiris.c
@@ -114,6 +114,15 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
114 .clocks = osiris_serial_clocks, 114 .clocks = osiris_serial_clocks,
115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks), 115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
116 }, 116 },
117 [2] = {
118 .hwport = 2,
119 .flags = 0,
120 .ucon = UCON,
121 .ulcon = ULCON,
122 .ufcon = UFCON,
123 .clocks = osiris_serial_clocks,
124 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
125 }
117}; 126};
118 127
119/* NAND Flash on Osiris board */ 128/* NAND Flash on Osiris board */
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
index 23d7c052013c..ecbcdf79d739 100644
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ b/arch/arm/mach-s3c2410/mach-rx3715.c
@@ -42,6 +42,7 @@
42#include <asm/arch/regs-gpio.h> 42#include <asm/arch/regs-gpio.h>
43#include <asm/arch/regs-lcd.h> 43#include <asm/arch/regs-lcd.h>
44 44
45#include <asm/arch/h1940.h>
45#include <asm/arch/nand.h> 46#include <asm/arch/nand.h>
46#include <asm/arch/fb.h> 47#include <asm/arch/fb.h>
47 48
@@ -224,7 +225,9 @@ static void __init rx3715_init_irq(void)
224 225
225static void __init rx3715_init_machine(void) 226static void __init rx3715_init_machine(void)
226{ 227{
228 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
227 s3c2410_pm_init(); 229 s3c2410_pm_init();
230
228 s3c24xx_fb_set_platdata(&rx3715_lcdcfg); 231 s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
229} 232}
230 233
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index a0d7692cdb2b..e2eda3937ab0 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -41,6 +41,7 @@
41 41
42#include <asm/arch/regs-serial.h> 42#include <asm/arch/regs-serial.h>
43#include <asm/arch/regs-gpio.h> 43#include <asm/arch/regs-gpio.h>
44#include <asm/arch/leds-gpio.h>
44 45
45#include "clock.h" 46#include "clock.h"
46#include "devs.h" 47#include "devs.h"
@@ -313,6 +314,50 @@ static struct platform_device vr1000_dm9k1 = {
313 } 314 }
314}; 315};
315 316
317/* LEDS */
318
319static struct s3c24xx_led_platdata vr1000_led1_pdata = {
320 .name = "led1",
321 .gpio = S3C2410_GPB0,
322 .def_trigger = "",
323};
324
325static struct s3c24xx_led_platdata vr1000_led2_pdata = {
326 .name = "led2",
327 .gpio = S3C2410_GPB1,
328 .def_trigger = "",
329};
330
331static struct s3c24xx_led_platdata vr1000_led3_pdata = {
332 .name = "led3",
333 .gpio = S3C2410_GPB2,
334 .def_trigger = "",
335};
336
337static struct platform_device vr1000_led1 = {
338 .name = "s3c24xx_led",
339 .id = 1,
340 .dev = {
341 .platform_data = &vr1000_led1_pdata,
342 },
343};
344
345static struct platform_device vr1000_led2 = {
346 .name = "s3c24xx_led",
347 .id = 2,
348 .dev = {
349 .platform_data = &vr1000_led2_pdata,
350 },
351};
352
353static struct platform_device vr1000_led3 = {
354 .name = "s3c24xx_led",
355 .id = 1,
356 .dev = {
357 .platform_data = &vr1000_led3_pdata,
358 },
359};
360
316/* devices for this board */ 361/* devices for this board */
317 362
318static struct platform_device *vr1000_devices[] __initdata = { 363static struct platform_device *vr1000_devices[] __initdata = {
@@ -325,7 +370,10 @@ static struct platform_device *vr1000_devices[] __initdata = {
325 &serial_device, 370 &serial_device,
326 &vr1000_nor, 371 &vr1000_nor,
327 &vr1000_dm9k0, 372 &vr1000_dm9k0,
328 &vr1000_dm9k1 373 &vr1000_dm9k1,
374 &vr1000_led1,
375 &vr1000_led2,
376 &vr1000_led3,
329}; 377};
330 378
331static struct clk *vr1000_clocks[] = { 379static struct clk *vr1000_clocks[] = {
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c2410/pm-h1940.S
new file mode 100644
index 000000000000..7d66de7ff7db
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pm-h1940.S
@@ -0,0 +1,33 @@
1/* linux/arch/arm/mach-s3c2410/pm-h1940.S
2 *
3 * Copyright (c) 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 Suspend to RAM
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/linkage.h>
22#include <asm/assembler.h>
23#include <asm/hardware.h>
24#include <asm/arch/map.h>
25
26#include <asm/arch/regs-gpio.h>
27
28 .text
29 .global h1940_pm_return
30
31h1940_pm_return:
32 mov r0, #S3C2410_PA_GPIO
33 ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
diff --git a/arch/arm/mach-s3c2410/s3c2410-gpio.c b/arch/arm/mach-s3c2410/s3c2410-gpio.c
index a2098f692d83..ec3a276cc3cf 100644
--- a/arch/arm/mach-s3c2410/s3c2410-gpio.c
+++ b/arch/arm/mach-s3c2410/s3c2410-gpio.c
@@ -69,22 +69,3 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
69} 69}
70 70
71EXPORT_SYMBOL(s3c2410_gpio_irqfilter); 71EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
72
73int s3c2410_gpio_getirq(unsigned int pin)
74{
75 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
76 return -1; /* not valid interrupts */
77
78 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
79 return -1; /* not valid pin */
80
81 if (pin < S3C2410_GPF4)
82 return (pin - S3C2410_GPF0) + IRQ_EINT0;
83
84 if (pin < S3C2410_GPG0)
85 return (pin - S3C2410_GPF4) + IRQ_EINT4;
86
87 return (pin - S3C2410_GPG0) + IRQ_EINT8;
88}
89
90EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/mach-s3c2410/s3c2410-pm.c b/arch/arm/mach-s3c2410/s3c2410-pm.c
index e51d76669512..77c6814c0f05 100644
--- a/arch/arm/mach-s3c2410/s3c2410-pm.c
+++ b/arch/arm/mach-s3c2410/s3c2410-pm.c
@@ -32,6 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34#include <asm/arch/regs-gpio.h> 34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/h1940.h>
35 36
36#include "cpu.h" 37#include "cpu.h"
37#include "pm.h" 38#include "pm.h"
@@ -52,6 +53,35 @@ static void s3c2410_pm_prepare(void)
52 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); 53 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
53 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); 54 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
54 55
56 if (machine_is_h1940()) {
57 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
58 unsigned long ptr;
59 unsigned long calc = 0;
60
61 /* generate check for the bootloader to check on resume */
62
63 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
64 calc += __raw_readl(base+ptr);
65
66 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
67 }
68
69 /* the RX3715 uses similar code and the same H1940 and the
70 * same offsets for resume and checksum pointers */
71
72 if (machine_is_rx3715()) {
73 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
74 unsigned long ptr;
75 unsigned long calc = 0;
76
77 /* generate check for the bootloader to check on resume */
78
79 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
80 calc += __raw_readl(base+ptr);
81
82 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
83 }
84
55 if ( machine_is_aml_m5900() ) 85 if ( machine_is_aml_m5900() )
56 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 86 s3c2410_gpio_setpin(S3C2410_GPF2, 1);
57 87
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
index 7f741547658f..ffcc30b23a80 100644
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2412-irq.c
@@ -98,7 +98,7 @@ s3c2412_irq_unmask(unsigned int irqno)
98 __raw_writel(mask & ~bitval, S3C2410_INTMSK); 98 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
99} 99}
100 100
101static struct irqchip s3c2412_irq_eint0t4 = { 101static struct irq_chip s3c2412_irq_eint0t4 = {
102 .ack = s3c2412_irq_ack, 102 .ack = s3c2412_irq_ack,
103 .mask = s3c2412_irq_mask, 103 .mask = s3c2412_irq_mask,
104 .unmask = s3c2412_irq_unmask, 104 .unmask = s3c2412_irq_unmask,
@@ -112,7 +112,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
112 112
113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
114 set_irq_chip(irqno, &s3c2412_irq_eint0t4); 114 set_irq_chip(irqno, &s3c2412_irq_eint0t4);
115 set_irq_handler(irqno, do_edge_IRQ); 115 set_irq_handler(irqno, handle_edge_irq);
116 set_irq_flags(irqno, IRQF_VALID); 116 set_irq_flags(irqno, IRQF_VALID);
117 } 117 }
118 118
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 39db0752d53b..1ba19b27ab05 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -42,10 +42,10 @@
42/* WDT/AC97 */ 42/* WDT/AC97 */
43 43
44static void s3c_irq_demux_wdtac97(unsigned int irq, 44static void s3c_irq_demux_wdtac97(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -90,7 +90,7 @@ s3c_irq_wdtac97_ack(unsigned int irqno)
90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); 90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
91} 91}
92 92
93static struct irqchip s3c_irq_wdtac97 = { 93static struct irq_chip s3c_irq_wdtac97 = {
94 .mask = s3c_irq_wdtac97_mask, 94 .mask = s3c_irq_wdtac97_mask,
95 .unmask = s3c_irq_wdtac97_unmask, 95 .unmask = s3c_irq_wdtac97_unmask,
96 .ack = s3c_irq_wdtac97_ack, 96 .ack = s3c_irq_wdtac97_ack,
@@ -105,12 +105,12 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
105 /* add new chained handler for wdt, ac7 */ 105 /* add new chained handler for wdt, ac7 */
106 106
107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); 107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
108 set_irq_handler(IRQ_WDT, do_level_IRQ); 108 set_irq_handler(IRQ_WDT, handle_level_irq);
109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); 109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
110 110
111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { 111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
112 set_irq_chip(irqno, &s3c_irq_wdtac97); 112 set_irq_chip(irqno, &s3c_irq_wdtac97);
113 set_irq_handler(irqno, do_level_IRQ); 113 set_irq_handler(irqno, handle_level_irq);
114 set_irq_flags(irqno, IRQF_VALID); 114 set_irq_flags(irqno, IRQF_VALID);
115 } 115 }
116 116
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
index 146f2109dd90..ede94636a72a 100644
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -42,10 +42,10 @@
42/* camera irq */ 42/* camera irq */
43 43
44static void s3c_irq_demux_cam(unsigned int irq, 44static void s3c_irq_demux_cam(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -89,7 +89,7 @@ s3c_irq_cam_ack(unsigned int irqno)
89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); 89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
90} 90}
91 91
92static struct irqchip s3c_irq_cam = { 92static struct irq_chip s3c_irq_cam = {
93 .mask = s3c_irq_cam_mask, 93 .mask = s3c_irq_cam_mask,
94 .unmask = s3c_irq_cam_unmask, 94 .unmask = s3c_irq_cam_unmask,
95 .ack = s3c_irq_cam_ack, 95 .ack = s3c_irq_cam_ack,
@@ -100,18 +100,18 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
100 unsigned int irqno; 100 unsigned int irqno;
101 101
102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); 102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
103 set_irq_handler(IRQ_NFCON, do_level_IRQ); 103 set_irq_handler(IRQ_NFCON, handle_level_irq);
104 set_irq_flags(IRQ_NFCON, IRQF_VALID); 104 set_irq_flags(IRQ_NFCON, IRQF_VALID);
105 105
106 /* add chained handler for camera */ 106 /* add chained handler for camera */
107 107
108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); 108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
109 set_irq_handler(IRQ_CAM, do_level_IRQ); 109 set_irq_handler(IRQ_CAM, handle_level_irq);
110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); 110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
111 111
112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { 112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
113 set_irq_chip(irqno, &s3c_irq_cam); 113 set_irq_chip(irqno, &s3c_irq_cam);
114 set_irq_handler(irqno, do_level_IRQ); 114 set_irq_handler(irqno, handle_level_irq);
115 set_irq_flags(irqno, IRQF_VALID); 115 set_irq_flags(irqno, IRQF_VALID);
116 } 116 }
117 117