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-rw-r--r--arch/arm/mach-s3c2410/sleep.S6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 832fb86a03b4..73de2eaca22a 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -59,8 +59,7 @@ ENTRY(s3c2410_cpu_suspend)
59 mrc p15, 0, r5, c13, c0, 0 @ PID 59 mrc p15, 0, r5, c13, c0, 0 @ PID
60 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 60 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
61 mrc p15, 0, r7, c2, c0, 0 @ translation table base address 61 mrc p15, 0, r7, c2, c0, 0 @ translation table base address
62 mrc p15, 0, r8, c2, c0, 0 @ auxiliary control register 62 mrc p15, 0, r8, c1, c0, 0 @ control register
63 mrc p15, 0, r9, c1, c0, 0 @ control register
64 63
65 stmia r0, { r4 - r13 } 64 stmia r0, { r4 - r13 }
66 65
@@ -165,7 +164,6 @@ ENTRY(s3c2410_cpu_resume)
165 mcr p15, 0, r5, c13, c0, 0 @ PID 164 mcr p15, 0, r5, c13, c0, 0 @ PID
166 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 165 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
167 mcr p15, 0, r7, c2, c0, 0 @ translation table base 166 mcr p15, 0, r7, c2, c0, 0 @ translation table base
168 mcr p15, 0, r8, c1, c1, 0 @ auxilliary control
169 167
170#ifdef CONFIG_DEBUG_RESUME 168#ifdef CONFIG_DEBUG_RESUME
171 mov r3, #'R' 169 mov r3, #'R'
@@ -173,7 +171,7 @@ ENTRY(s3c2410_cpu_resume)
173#endif 171#endif
174 172
175 ldr r2, =resume_with_mmu 173 ldr r2, =resume_with_mmu
176 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc 174 mcr p15, 0, r8, c1, c0, 0 @ turn on MMU, etc
177 nop @ second-to-last before mmu 175 nop @ second-to-last before mmu
178 mov pc, r2 @ go back to virtual address 176 mov pc, r2 @ go back to virtual address
179 177