1 files changed, 30 insertions, 121 deletions

diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 2018c2e1dcc5..637aaba65390 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/sleep.S
+/* linux/arch/arm/mach-s3c2410/s3c2410-sleep.S
  *
  * Copyright (c) 2004 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
@@ -34,126 +34,35 @@
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-serial.h>
 
-/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
- * reset the UART configuration, only enable if you really need this!
-*/
-//#define CONFIG_DEBUG_RESUME
-
-        .text
-
-        /* s3c2410_cpu_save
-         *
-         * save enough of the CPU state to allow us to re-start
-         * pm.c code. as we store items like the sp/lr, we will
-         * end up returning from this function when the cpu resumes
-         * so the return value is set to mark this.
-         *
-         * This arangement means we avoid having to flush the cache
-         * from this code.
-         *
-         * entry:
-         *      r0 = pointer to save block
-         *
-         * exit:
-         *      r0 = 0 => we stored everything
-         *           1 => resumed from sleep
-        */
-
-ENTRY(s3c2410_cpu_save)
-        stmfd   sp!, { r4 - r12, lr }
-
-        @@ store co-processor registers
-
-        mrc     p15, 0, r4, c15, c1, 0  @ CP access register
-        mrc     p15, 0, r5, c13, c0, 0  @ PID
-        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r7, c2, c0, 0   @ translation table base address
-        mrc     p15, 0, r8, c1, c0, 0   @ control register
-
-        stmia   r0, { r4 - r13 }
-
-        mov     r0, #0
-        ldmfd   sp, { r4 - r12, pc }
-
-        @@ return to the caller, after having the MMU
-        @@ turned on, this restores the last bits from the
-        @@ stack
-resume_with_mmu:
-        mov     r0, #1
-        ldmfd   sp!, { r4 - r12, pc }
-
-        .ltorg
-
-        @@ the next bits sit in the .data segment, even though they
-        @@ happen to be code... the s3c2410_sleep_save_phys needs to be
-        @@ accessed by the resume code before it can restore the MMU.
-        @@ This means that the variable has to be close enough for the
-        @@ code to read it... since the .text segment needs to be RO,
-        @@ the data segment can be the only place to put this code.
-
-        .data
-
-        .global s3c2410_sleep_save_phys
-s3c2410_sleep_save_phys:
-        .word   0
-
-        /* s3c2410_cpu_resume
+        /* s3c2410_cpu_suspend
          *
-         * resume code entry for bootloader to call
-         *
-         * we must put this code here in the data segment as we have no
-         * other way of restoring the stack pointer after sleep, and we
-         * must not write to the code segment (code is read-only)
+         * put the cpu into sleep mode
         */
 
-ENTRY(s3c2410_cpu_resume)
-        mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
-        msr     cpsr_c, r0
-
-        @@ load UART to allow us to print the two characters for
-        @@ resume debug
-
-        mov     r2, #S3C24XX_PA_UART & 0xff000000
-        orr     r2, r2, #S3C24XX_PA_UART & 0xff000
-
-#if 0
-        /* SMDK2440 LED set */
-        mov     r14, #S3C24XX_PA_GPIO
-        ldr     r12, [ r14, #0x54 ]
-        bic     r12, r12, #3<<4
-        orr     r12, r12, #1<<7
-        str     r12, [ r14, #0x54 ]
-#endif
-
-#ifdef CONFIG_DEBUG_RESUME
-        mov     r3, #'L'
-        strb    r3, [ r2, #S3C2410_UTXH ]
-1001:
-        ldrb    r14, [ r3, #S3C2410_UTRSTAT ]
-        tst     r14, #S3C2410_UTRSTAT_TXE
-        beq     1001b
-#endif /* CONFIG_DEBUG_RESUME */
-
-        mov     r1, #0
-        mcr     p15, 0, r1, c8, c7, 0           @@ invalidate I & D TLBs
-        mcr     p15, 0, r1, c7, c7, 0           @@ invalidate I & D caches
-
-        ldr     r0, s3c2410_sleep_save_phys     @ address of restore block
-        ldmia   r0, { r4 - r13 }
-
-        mcr     p15, 0, r4, c15, c1, 0          @ CP access register
-        mcr     p15, 0, r5, c13, c0, 0          @ PID
-        mcr     p15, 0, r6, c3, c0, 0           @ Domain ID
-        mcr     p15, 0, r7, c2, c0, 0           @ translation table base
-
-#ifdef CONFIG_DEBUG_RESUME
-        mov     r3, #'R'
-        strb    r3, [ r2, #S3C2410_UTXH ]
-#endif
-
-        ldr     r2, =resume_with_mmu
-        mcr     p15, 0, r8, c1, c0, 0           @ turn on MMU, etc
-        nop                                     @ second-to-last before mmu
-        mov     pc, r2                          @ go back to virtual address
-
-        .ltorg
+ENTRY(s3c2410_cpu_suspend)
+        @@ prepare cpu to sleep
+
+        ldr     r4, =S3C2410_REFRESH
+        ldr     r5, =S3C24XX_MISCCR
+        ldr     r6, =S3C2410_CLKCON
+        ldr     r7, [ r4 ]              @ get REFRESH (and ensure in TLB)
+        ldr     r8, [ r5 ]              @ get MISCCR (and ensure in TLB)
+        ldr     r9, [ r6 ]              @ get CLKCON (and ensure in TLB)
+
+        orr     r7, r7, #S3C2410_REFRESH_SELF   @ SDRAM sleep command
+        orr     r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
+        orr     r9, r9, #S3C2410_CLKCON_POWER   @ power down command
+
+        teq     pc, #0                  @ first as a trial-run to load cache
+        bl      s3c2410_do_sleep
+        teq     r0, r0                  @ now do it for real
+        b       s3c2410_do_sleep        @
+
+        @@ align next bit of code to cache line
+        .align  5
+s3c2410_do_sleep:
+        streq   r7, [ r4 ]                      @ SDRAM sleep command
+        streq   r8, [ r5 ]                      @ SDRAM power-down config
+        streq   r9, [ r6 ]                      @ CPU sleep
+1:      beq     1b
+        mov     pc, r14