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-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c252
1 files changed, 106 insertions, 146 deletions
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index e670b1e1631b..03ea5d7b2a17 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -95,157 +95,116 @@ static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
95 95
96/* LCD driver info */ 96/* LCD driver info */
97 97
98/* Configuration for 640x480 SHARP LQ080V3DG01 */ 98static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
99static struct s3c2410fb_mach_info qt2410_biglcd_cfg __initdata = { 99 {
100 .regs = { 100 /* Configuration for 640x480 SHARP LQ080V3DG01 */
101 101 .regs = {
102 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 102
103 S3C2410_LCDCON1_TFT | 103 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
104 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ 104 S3C2410_LCDCON1_TFT |
105 105 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
106 .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */ 106
107 S3C2410_LCDCON2_LINEVAL(479) | 107 .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */
108 S3C2410_LCDCON2_VFPD(10) | /* 11 */ 108 S3C2410_LCDCON2_LINEVAL(479) |
109 S3C2410_LCDCON2_VSPW(14), /* 15 */ 109 S3C2410_LCDCON2_VFPD(10) | /* 11 */
110 110 S3C2410_LCDCON2_VSPW(14), /* 15 */
111 .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */ 111
112 S3C2410_LCDCON3_HOZVAL(639) | /* 640 */ 112 .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */
113 S3C2410_LCDCON3_HFPD(115), /* 116 */ 113 S3C2410_LCDCON3_HOZVAL(639) | /* 640 */
114 114 S3C2410_LCDCON3_HFPD(115), /* 116 */
115 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 115
116 S3C2410_LCDCON4_HSPW(95), /* 96 */ 116 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
117 117 S3C2410_LCDCON4_HSPW(95), /* 96 */
118 .lcdcon5 = S3C2410_LCDCON5_FRM565 | 118
119 S3C2410_LCDCON5_INVVLINE | 119 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
120 S3C2410_LCDCON5_INVVFRAME | 120 S3C2410_LCDCON5_INVVLINE |
121 S3C2410_LCDCON5_PWREN | 121 S3C2410_LCDCON5_INVVFRAME |
122 S3C2410_LCDCON5_HWSWP, 122 S3C2410_LCDCON5_PWREN |
123 S3C2410_LCDCON5_HWSWP,
124 },
125
126 .width = 640,
127 .height = 480,
128
129 .xres = 640,
130 .yres = 480,
131 .bpp = 16,
123 }, 132 },
124 133 {
125 .lpcsel = ((0xCE6) & ~7) | 1<<4, 134 /* Configuration for 480x640 toppoly TD028TTEC1 */
126 135 .regs = {
127 .width = 640, 136
128 .height = 480, 137 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
129 138 S3C2410_LCDCON1_TFT |
130 .xres = { 139 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
131 .min = 640, 140
132 .max = 640, 141 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
133 .defval = 640, 142 S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
134 }, 143 S3C2410_LCDCON2_VFPD(3) | /* 4 */
135 144 S3C2410_LCDCON2_VSPW(1), /* 2 */
136 .yres = { 145
137 .min = 480, 146 .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */
138 .max = 480, 147 S3C2410_LCDCON3_HOZVAL(479) | /* 479 */
139 .defval = 480, 148 S3C2410_LCDCON3_HFPD(23), /* 24 */
140 }, 149
141 150 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
142 .bpp = { 151 S3C2410_LCDCON4_HSPW(7), /* 8 */
143 .min = 16, 152
144 .max = 16, 153 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
145 .defval = 16, 154 S3C2410_LCDCON5_INVVLINE |
146 }, 155 S3C2410_LCDCON5_INVVFRAME |
147}; 156 S3C2410_LCDCON5_PWREN |
148 157 S3C2410_LCDCON5_HWSWP,
149/* Configuration for 480x640 toppoly TD028TTEC1 */ 158 },
150static struct s3c2410fb_mach_info qt2410_prodlcd_cfg __initdata = { 159
151 .regs = { 160 .width = 480,
152 161 .height = 640,
153 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 162 .xres = 480,
154 S3C2410_LCDCON1_TFT | 163 .yres = 640,
155 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ 164 .bpp = 16,
156
157 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
158 S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
159 S3C2410_LCDCON2_VFPD(3) | /* 4 */
160 S3C2410_LCDCON2_VSPW(1), /* 2 */
161
162 .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */
163 S3C2410_LCDCON3_HOZVAL(479) | /* 479 */
164 S3C2410_LCDCON3_HFPD(23), /* 24 */
165
166 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
167 S3C2410_LCDCON4_HSPW(7), /* 8 */
168
169 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
170 S3C2410_LCDCON5_INVVLINE |
171 S3C2410_LCDCON5_INVVFRAME |
172 S3C2410_LCDCON5_PWREN |
173 S3C2410_LCDCON5_HWSWP,
174 },
175
176 .lpcsel = ((0xCE6) & ~7) | 1<<4,
177
178 .width = 480,
179 .height = 640,
180
181 .xres = {
182 .min = 480,
183 .max = 480,
184 .defval = 480,
185 }, 165 },
186 166 {
187 .yres = { 167 /* Config for 240x320 LCD */
188 .min = 640, 168 .regs = {
189 .max = 640, 169
190 .defval = 640, 170 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
191 }, 171 S3C2410_LCDCON1_TFT |
192 172 S3C2410_LCDCON1_CLKVAL(0x04),
193 .bpp = { 173
194 .min = 16, 174 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
195 .max = 16, 175 S3C2410_LCDCON2_LINEVAL(319) |
196 .defval = 16, 176 S3C2410_LCDCON2_VFPD(6) |
177 S3C2410_LCDCON2_VSPW(3),
178
179 .lcdcon3 = S3C2410_LCDCON3_HBPD(12) |
180 S3C2410_LCDCON3_HOZVAL(239) |
181 S3C2410_LCDCON3_HFPD(7),
182
183 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
184 S3C2410_LCDCON4_HSPW(3),
185
186 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
187 S3C2410_LCDCON5_INVVLINE |
188 S3C2410_LCDCON5_INVVFRAME |
189 S3C2410_LCDCON5_PWREN |
190 S3C2410_LCDCON5_HWSWP,
191 },
192
193 .width = 240,
194 .height = 320,
195 .xres = 240,
196 .yres = 320,
197 .bpp = 16,
197 }, 198 },
198}; 199};
199 200
200/* Config for 240x320 LCD */
201static struct s3c2410fb_mach_info qt2410_lcd_cfg __initdata = {
202 .regs = {
203
204 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
205 S3C2410_LCDCON1_TFT |
206 S3C2410_LCDCON1_CLKVAL(0x04),
207
208 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
209 S3C2410_LCDCON2_LINEVAL(319) |
210 S3C2410_LCDCON2_VFPD(6) |
211 S3C2410_LCDCON2_VSPW(3),
212
213 .lcdcon3 = S3C2410_LCDCON3_HBPD(12) |
214 S3C2410_LCDCON3_HOZVAL(239) |
215 S3C2410_LCDCON3_HFPD(7),
216 201
217 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 202static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
218 S3C2410_LCDCON4_HSPW(3), 203 .displays = qt2410_lcd_cfg,
219 204 .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
220 .lcdcon5 = S3C2410_LCDCON5_FRM565 | 205 .default_display = 0,
221 S3C2410_LCDCON5_INVVLINE |
222 S3C2410_LCDCON5_INVVFRAME |
223 S3C2410_LCDCON5_PWREN |
224 S3C2410_LCDCON5_HWSWP,
225 },
226 206
227 .lpcsel = ((0xCE6) & ~7) | 1<<4, 207 .lpcsel = ((0xCE6) & ~7) | 1<<4,
228
229 .width = 240,
230 .height = 320,
231
232 .xres = {
233 .min = 240,
234 .max = 240,
235 .defval = 240,
236 },
237
238 .yres = {
239 .min = 320,
240 .max = 320,
241 .defval = 320,
242 },
243
244 .bpp = {
245 .min = 16,
246 .max = 16,
247 .defval = 16,
248 },
249}; 208};
250 209
251/* CS8900 */ 210/* CS8900 */
@@ -408,16 +367,17 @@ static void __init qt2410_machine_init(void)
408 367
409 switch (tft_type) { 368 switch (tft_type) {
410 case 'p': /* production */ 369 case 'p': /* production */
411 s3c24xx_fb_set_platdata(&qt2410_prodlcd_cfg); 370 qt2410_fb_info.default_display = 1;
412 break; 371 break;
413 case 'b': /* big */ 372 case 'b': /* big */
414 s3c24xx_fb_set_platdata(&qt2410_biglcd_cfg); 373 qt2410_fb_info.default_display = 0;
415 break; 374 break;
416 case 's': /* small */ 375 case 's': /* small */
417 default: 376 default:
418 s3c24xx_fb_set_platdata(&qt2410_lcd_cfg); 377 qt2410_fb_info.default_display = 2;
419 break; 378 break;
420 } 379 }
380 s3c24xx_fb_set_platdata(&qt2410_fb_info);
421 381
422 s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); 382 s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
423 s3c2410_gpio_setpin(S3C2410_GPB0, 1); 383 s3c2410_gpio_setpin(S3C2410_GPB0, 1);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-02 04:19:20 -0400