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-rw-r--r--arch/arm/mach-s3c2410/irq.c165
1 files changed, 127 insertions, 38 deletions
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index cd6139b35999..3e9f3462c61b 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -181,17 +181,19 @@ s3c_irq_unmask(unsigned int irqno)
181} 181}
182 182
183struct irqchip s3c_irq_level_chip = { 183struct irqchip s3c_irq_level_chip = {
184 .ack = s3c_irq_maskack, 184 .name = "s3c-level",
185 .mask = s3c_irq_mask, 185 .ack = s3c_irq_maskack,
186 .unmask = s3c_irq_unmask, 186 .mask = s3c_irq_mask,
187 .set_wake = s3c_irq_wake 187 .unmask = s3c_irq_unmask,
188 .set_wake = s3c_irq_wake
188}; 189};
189 190
190static struct irqchip s3c_irq_chip = { 191static struct irqchip s3c_irq_chip = {
191 .ack = s3c_irq_ack, 192 .name = "s3c",
192 .mask = s3c_irq_mask, 193 .ack = s3c_irq_ack,
193 .unmask = s3c_irq_unmask, 194 .mask = s3c_irq_mask,
194 .set_wake = s3c_irq_wake 195 .unmask = s3c_irq_unmask,
196 .set_wake = s3c_irq_wake
195}; 197};
196 198
197static void 199static void
@@ -343,19 +345,21 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
343} 345}
344 346
345static struct irqchip s3c_irqext_chip = { 347static struct irqchip s3c_irqext_chip = {
346 .mask = s3c_irqext_mask, 348 .name = "s3c-ext",
347 .unmask = s3c_irqext_unmask, 349 .mask = s3c_irqext_mask,
348 .ack = s3c_irqext_ack, 350 .unmask = s3c_irqext_unmask,
349 .set_type = s3c_irqext_type, 351 .ack = s3c_irqext_ack,
350 .set_wake = s3c_irqext_wake 352 .set_type = s3c_irqext_type,
353 .set_wake = s3c_irqext_wake
351}; 354};
352 355
353static struct irqchip s3c_irq_eint0t4 = { 356static struct irqchip s3c_irq_eint0t4 = {
354 .ack = s3c_irq_ack, 357 .name = "s3c-ext0",
355 .mask = s3c_irq_mask, 358 .ack = s3c_irq_ack,
356 .unmask = s3c_irq_unmask, 359 .mask = s3c_irq_mask,
357 .set_wake = s3c_irq_wake, 360 .unmask = s3c_irq_unmask,
358 .set_type = s3c_irqext_type, 361 .set_wake = s3c_irq_wake,
362 .set_type = s3c_irqext_type,
359}; 363};
360 364
361/* mask values for the parent registers for each of the interrupt types */ 365/* mask values for the parent registers for each of the interrupt types */
@@ -387,9 +391,10 @@ s3c_irq_uart0_ack(unsigned int irqno)
387} 391}
388 392
389static struct irqchip s3c_irq_uart0 = { 393static struct irqchip s3c_irq_uart0 = {
390 .mask = s3c_irq_uart0_mask, 394 .name = "s3c-uart0",
391 .unmask = s3c_irq_uart0_unmask, 395 .mask = s3c_irq_uart0_mask,
392 .ack = s3c_irq_uart0_ack, 396 .unmask = s3c_irq_uart0_unmask,
397 .ack = s3c_irq_uart0_ack,
393}; 398};
394 399
395/* UART1 */ 400/* UART1 */
@@ -413,9 +418,10 @@ s3c_irq_uart1_ack(unsigned int irqno)
413} 418}
414 419
415static struct irqchip s3c_irq_uart1 = { 420static struct irqchip s3c_irq_uart1 = {
416 .mask = s3c_irq_uart1_mask, 421 .name = "s3c-uart1",
417 .unmask = s3c_irq_uart1_unmask, 422 .mask = s3c_irq_uart1_mask,
418 .ack = s3c_irq_uart1_ack, 423 .unmask = s3c_irq_uart1_unmask,
424 .ack = s3c_irq_uart1_ack,
419}; 425};
420 426
421/* UART2 */ 427/* UART2 */
@@ -439,9 +445,10 @@ s3c_irq_uart2_ack(unsigned int irqno)
439} 445}
440 446
441static struct irqchip s3c_irq_uart2 = { 447static struct irqchip s3c_irq_uart2 = {
442 .mask = s3c_irq_uart2_mask, 448 .name = "s3c-uart2",
443 .unmask = s3c_irq_uart2_unmask, 449 .mask = s3c_irq_uart2_mask,
444 .ack = s3c_irq_uart2_ack, 450 .unmask = s3c_irq_uart2_unmask,
451 .ack = s3c_irq_uart2_ack,
445}; 452};
446 453
447/* ADC and Touchscreen */ 454/* ADC and Touchscreen */
@@ -465,9 +472,10 @@ s3c_irq_adc_ack(unsigned int irqno)
465} 472}
466 473
467static struct irqchip s3c_irq_adc = { 474static struct irqchip s3c_irq_adc = {
468 .mask = s3c_irq_adc_mask, 475 .name = "s3c-adc",
469 .unmask = s3c_irq_adc_unmask, 476 .mask = s3c_irq_adc_mask,
470 .ack = s3c_irq_adc_ack, 477 .unmask = s3c_irq_adc_unmask,
478 .ack = s3c_irq_adc_ack,
471}; 479};
472 480
473/* irq demux for adc */ 481/* irq demux for adc */
@@ -569,23 +577,104 @@ s3c_irq_demux_uart2(unsigned int irq,
569} 577}
570 578
571static void 579static void
572s3c_irq_demux_extint(unsigned int irq, 580s3c_irq_demux_extint8(unsigned int irq,
573 struct irqdesc *desc, 581 struct irqdesc *desc,
574 struct pt_regs *regs) 582 struct pt_regs *regs)
575{ 583{
576 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 584 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
577 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 585 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
578 586
579 eintpnd &= ~eintmsk; 587 eintpnd &= ~eintmsk;
588 eintpnd &= ~0xff; /* ignore lower irqs */
580 589
581 if (eintpnd) { 590 /* we may as well handle all the pending IRQs here */
582 irq = fls(eintpnd);
583 irq += (IRQ_EINT4 - (4 + 1));
584 591
592 while (eintpnd) {
593 irq = __ffs(eintpnd);
594 eintpnd &= ~(1<<irq);
595
596 irq += (IRQ_EINT4 - 4);
585 desc_handle_irq(irq, irq_desc + irq, regs); 597 desc_handle_irq(irq, irq_desc + irq, regs);
586 } 598 }
599
600}
601
602static void
603s3c_irq_demux_extint4t7(unsigned int irq,
604 struct irqdesc *desc,
605 struct pt_regs *regs)
606{
607 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
608 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
609
610 eintpnd &= ~eintmsk;
611 eintpnd &= 0xff; /* only lower irqs */
612
613 /* we may as well handle all the pending IRQs here */
614
615 while (eintpnd) {
616 irq = __ffs(eintpnd);
617 eintpnd &= ~(1<<irq);
618
619 irq += (IRQ_EINT4 - 4);
620
621 desc_handle_irq(irq, irq_desc + irq, regs);
622 }
623}
624
625#ifdef CONFIG_PM
626
627static struct sleep_save irq_save[] = {
628 SAVE_ITEM(S3C2410_INTMSK),
629 SAVE_ITEM(S3C2410_INTSUBMSK),
630};
631
632/* the extint values move between the s3c2410/s3c2440 and the s3c2412
633 * so we use an array to hold them, and to calculate the address of
634 * the register at run-time
635*/
636
637static unsigned long save_extint[3];
638static unsigned long save_eintflt[4];
639static unsigned long save_eintmask;
640
641int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
642{
643 unsigned int i;
644
645 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
646 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
647
648 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
649 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
650
651 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
652 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
653
654 return 0;
587} 655}
588 656
657int s3c24xx_irq_resume(struct sys_device *dev)
658{
659 unsigned int i;
660
661 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
662 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
663
664 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
665 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
666
667 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
668 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
669
670 return 0;
671}
672
673#else
674#define s3c24xx_irq_suspend NULL
675#define s3c24xx_irq_resume NULL
676#endif
677
589/* s3c24xx_init_irq 678/* s3c24xx_init_irq
590 * 679 *
591 * Initialise S3C2410 IRQ system 680 * Initialise S3C2410 IRQ system
@@ -674,8 +763,8 @@ void __init s3c24xx_init_irq(void)
674 763
675 /* setup the cascade irq handlers */ 764 /* setup the cascade irq handlers */
676 765
677 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint); 766 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
678 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint); 767 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
679 768
680 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); 769 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
681 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); 770 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);