diff options
Diffstat (limited to 'arch/arm/mach-s3c2410/irq.c')
-rw-r--r-- | arch/arm/mach-s3c2410/irq.c | 63 |
1 files changed, 24 insertions, 39 deletions
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 683b3491ba3c..3c0ed7871c55 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c | |||
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno) | |||
180 | __raw_writel(mask, S3C2410_INTMSK); | 180 | __raw_writel(mask, S3C2410_INTMSK); |
181 | } | 181 | } |
182 | 182 | ||
183 | struct irqchip s3c_irq_level_chip = { | 183 | struct irq_chip s3c_irq_level_chip = { |
184 | .name = "s3c-level", | 184 | .name = "s3c-level", |
185 | .ack = s3c_irq_maskack, | 185 | .ack = s3c_irq_maskack, |
186 | .mask = s3c_irq_mask, | 186 | .mask = s3c_irq_mask, |
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = { | |||
188 | .set_wake = s3c_irq_wake | 188 | .set_wake = s3c_irq_wake |
189 | }; | 189 | }; |
190 | 190 | ||
191 | static struct irqchip s3c_irq_chip = { | 191 | static struct irq_chip s3c_irq_chip = { |
192 | .name = "s3c", | 192 | .name = "s3c", |
193 | .ack = s3c_irq_ack, | 193 | .ack = s3c_irq_ack, |
194 | .mask = s3c_irq_mask, | 194 | .mask = s3c_irq_mask, |
@@ -206,18 +206,6 @@ s3c_irqext_mask(unsigned int irqno) | |||
206 | mask = __raw_readl(S3C24XX_EINTMASK); | 206 | mask = __raw_readl(S3C24XX_EINTMASK); |
207 | mask |= ( 1UL << irqno); | 207 | mask |= ( 1UL << irqno); |
208 | __raw_writel(mask, S3C24XX_EINTMASK); | 208 | __raw_writel(mask, S3C24XX_EINTMASK); |
209 | |||
210 | if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) { | ||
211 | /* check to see if all need masking */ | ||
212 | |||
213 | if ((mask & (0xf << 4)) == (0xf << 4)) { | ||
214 | /* all masked, mask the parent */ | ||
215 | s3c_irq_mask(IRQ_EINT4t7); | ||
216 | } | ||
217 | } else { | ||
218 | /* todo: the same check as above for the rest of the irq regs...*/ | ||
219 | |||
220 | } | ||
221 | } | 209 | } |
222 | 210 | ||
223 | static void | 211 | static void |
@@ -229,7 +217,6 @@ s3c_irqext_ack(unsigned int irqno) | |||
229 | 217 | ||
230 | bit = 1UL << (irqno - EXTINT_OFF); | 218 | bit = 1UL << (irqno - EXTINT_OFF); |
231 | 219 | ||
232 | |||
233 | mask = __raw_readl(S3C24XX_EINTMASK); | 220 | mask = __raw_readl(S3C24XX_EINTMASK); |
234 | 221 | ||
235 | __raw_writel(bit, S3C24XX_EINTPEND); | 222 | __raw_writel(bit, S3C24XX_EINTPEND); |
@@ -258,8 +245,6 @@ s3c_irqext_unmask(unsigned int irqno) | |||
258 | mask = __raw_readl(S3C24XX_EINTMASK); | 245 | mask = __raw_readl(S3C24XX_EINTMASK); |
259 | mask &= ~( 1UL << irqno); | 246 | mask &= ~( 1UL << irqno); |
260 | __raw_writel(mask, S3C24XX_EINTMASK); | 247 | __raw_writel(mask, S3C24XX_EINTMASK); |
261 | |||
262 | s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23); | ||
263 | } | 248 | } |
264 | 249 | ||
265 | int | 250 | int |
@@ -344,7 +329,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type) | |||
344 | return 0; | 329 | return 0; |
345 | } | 330 | } |
346 | 331 | ||
347 | static struct irqchip s3c_irqext_chip = { | 332 | static struct irq_chip s3c_irqext_chip = { |
348 | .name = "s3c-ext", | 333 | .name = "s3c-ext", |
349 | .mask = s3c_irqext_mask, | 334 | .mask = s3c_irqext_mask, |
350 | .unmask = s3c_irqext_unmask, | 335 | .unmask = s3c_irqext_unmask, |
@@ -353,7 +338,7 @@ static struct irqchip s3c_irqext_chip = { | |||
353 | .set_wake = s3c_irqext_wake | 338 | .set_wake = s3c_irqext_wake |
354 | }; | 339 | }; |
355 | 340 | ||
356 | static struct irqchip s3c_irq_eint0t4 = { | 341 | static struct irq_chip s3c_irq_eint0t4 = { |
357 | .name = "s3c-ext0", | 342 | .name = "s3c-ext0", |
358 | .ack = s3c_irq_ack, | 343 | .ack = s3c_irq_ack, |
359 | .mask = s3c_irq_mask, | 344 | .mask = s3c_irq_mask, |
@@ -390,7 +375,7 @@ s3c_irq_uart0_ack(unsigned int irqno) | |||
390 | s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); | 375 | s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); |
391 | } | 376 | } |
392 | 377 | ||
393 | static struct irqchip s3c_irq_uart0 = { | 378 | static struct irq_chip s3c_irq_uart0 = { |
394 | .name = "s3c-uart0", | 379 | .name = "s3c-uart0", |
395 | .mask = s3c_irq_uart0_mask, | 380 | .mask = s3c_irq_uart0_mask, |
396 | .unmask = s3c_irq_uart0_unmask, | 381 | .unmask = s3c_irq_uart0_unmask, |
@@ -417,7 +402,7 @@ s3c_irq_uart1_ack(unsigned int irqno) | |||
417 | s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); | 402 | s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); |
418 | } | 403 | } |
419 | 404 | ||
420 | static struct irqchip s3c_irq_uart1 = { | 405 | static struct irq_chip s3c_irq_uart1 = { |
421 | .name = "s3c-uart1", | 406 | .name = "s3c-uart1", |
422 | .mask = s3c_irq_uart1_mask, | 407 | .mask = s3c_irq_uart1_mask, |
423 | .unmask = s3c_irq_uart1_unmask, | 408 | .unmask = s3c_irq_uart1_unmask, |
@@ -444,7 +429,7 @@ s3c_irq_uart2_ack(unsigned int irqno) | |||
444 | s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); | 429 | s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); |
445 | } | 430 | } |
446 | 431 | ||
447 | static struct irqchip s3c_irq_uart2 = { | 432 | static struct irq_chip s3c_irq_uart2 = { |
448 | .name = "s3c-uart2", | 433 | .name = "s3c-uart2", |
449 | .mask = s3c_irq_uart2_mask, | 434 | .mask = s3c_irq_uart2_mask, |
450 | .unmask = s3c_irq_uart2_unmask, | 435 | .unmask = s3c_irq_uart2_unmask, |
@@ -471,7 +456,7 @@ s3c_irq_adc_ack(unsigned int irqno) | |||
471 | s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); | 456 | s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); |
472 | } | 457 | } |
473 | 458 | ||
474 | static struct irqchip s3c_irq_adc = { | 459 | static struct irq_chip s3c_irq_adc = { |
475 | .name = "s3c-adc", | 460 | .name = "s3c-adc", |
476 | .mask = s3c_irq_adc_mask, | 461 | .mask = s3c_irq_adc_mask, |
477 | .unmask = s3c_irq_adc_unmask, | 462 | .unmask = s3c_irq_adc_unmask, |
@@ -480,11 +465,11 @@ static struct irqchip s3c_irq_adc = { | |||
480 | 465 | ||
481 | /* irq demux for adc */ | 466 | /* irq demux for adc */ |
482 | static void s3c_irq_demux_adc(unsigned int irq, | 467 | static void s3c_irq_demux_adc(unsigned int irq, |
483 | struct irqdesc *desc) | 468 | struct irq_desc *desc) |
484 | { | 469 | { |
485 | unsigned int subsrc, submsk; | 470 | unsigned int subsrc, submsk; |
486 | unsigned int offset = 9; | 471 | unsigned int offset = 9; |
487 | struct irqdesc *mydesc; | 472 | struct irq_desc *mydesc; |
488 | 473 | ||
489 | /* read the current pending interrupts, and the mask | 474 | /* read the current pending interrupts, and the mask |
490 | * for what it is available */ | 475 | * for what it is available */ |
@@ -512,7 +497,7 @@ static void s3c_irq_demux_uart(unsigned int start) | |||
512 | { | 497 | { |
513 | unsigned int subsrc, submsk; | 498 | unsigned int subsrc, submsk; |
514 | unsigned int offset = start - IRQ_S3CUART_RX0; | 499 | unsigned int offset = start - IRQ_S3CUART_RX0; |
515 | struct irqdesc *desc; | 500 | struct irq_desc *desc; |
516 | 501 | ||
517 | /* read the current pending interrupts, and the mask | 502 | /* read the current pending interrupts, and the mask |
518 | * for what it is available */ | 503 | * for what it is available */ |
@@ -549,7 +534,7 @@ static void s3c_irq_demux_uart(unsigned int start) | |||
549 | 534 | ||
550 | static void | 535 | static void |
551 | s3c_irq_demux_uart0(unsigned int irq, | 536 | s3c_irq_demux_uart0(unsigned int irq, |
552 | struct irqdesc *desc) | 537 | struct irq_desc *desc) |
553 | { | 538 | { |
554 | irq = irq; | 539 | irq = irq; |
555 | s3c_irq_demux_uart(IRQ_S3CUART_RX0); | 540 | s3c_irq_demux_uart(IRQ_S3CUART_RX0); |
@@ -557,7 +542,7 @@ s3c_irq_demux_uart0(unsigned int irq, | |||
557 | 542 | ||
558 | static void | 543 | static void |
559 | s3c_irq_demux_uart1(unsigned int irq, | 544 | s3c_irq_demux_uart1(unsigned int irq, |
560 | struct irqdesc *desc) | 545 | struct irq_desc *desc) |
561 | { | 546 | { |
562 | irq = irq; | 547 | irq = irq; |
563 | s3c_irq_demux_uart(IRQ_S3CUART_RX1); | 548 | s3c_irq_demux_uart(IRQ_S3CUART_RX1); |
@@ -565,7 +550,7 @@ s3c_irq_demux_uart1(unsigned int irq, | |||
565 | 550 | ||
566 | static void | 551 | static void |
567 | s3c_irq_demux_uart2(unsigned int irq, | 552 | s3c_irq_demux_uart2(unsigned int irq, |
568 | struct irqdesc *desc) | 553 | struct irq_desc *desc) |
569 | { | 554 | { |
570 | irq = irq; | 555 | irq = irq; |
571 | s3c_irq_demux_uart(IRQ_S3CUART_RX2); | 556 | s3c_irq_demux_uart(IRQ_S3CUART_RX2); |
@@ -573,7 +558,7 @@ s3c_irq_demux_uart2(unsigned int irq, | |||
573 | 558 | ||
574 | static void | 559 | static void |
575 | s3c_irq_demux_extint8(unsigned int irq, | 560 | s3c_irq_demux_extint8(unsigned int irq, |
576 | struct irqdesc *desc) | 561 | struct irq_desc *desc) |
577 | { | 562 | { |
578 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); | 563 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); |
579 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); | 564 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); |
@@ -595,7 +580,7 @@ s3c_irq_demux_extint8(unsigned int irq, | |||
595 | 580 | ||
596 | static void | 581 | static void |
597 | s3c_irq_demux_extint4t7(unsigned int irq, | 582 | s3c_irq_demux_extint4t7(unsigned int irq, |
598 | struct irqdesc *desc) | 583 | struct irq_desc *desc) |
599 | { | 584 | { |
600 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); | 585 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); |
601 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); | 586 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); |
@@ -738,7 +723,7 @@ void __init s3c24xx_init_irq(void) | |||
738 | case IRQ_UART2: | 723 | case IRQ_UART2: |
739 | case IRQ_ADCPARENT: | 724 | case IRQ_ADCPARENT: |
740 | set_irq_chip(irqno, &s3c_irq_level_chip); | 725 | set_irq_chip(irqno, &s3c_irq_level_chip); |
741 | set_irq_handler(irqno, do_level_IRQ); | 726 | set_irq_handler(irqno, handle_level_irq); |
742 | break; | 727 | break; |
743 | 728 | ||
744 | case IRQ_RESERVED6: | 729 | case IRQ_RESERVED6: |
@@ -749,7 +734,7 @@ void __init s3c24xx_init_irq(void) | |||
749 | default: | 734 | default: |
750 | //irqdbf("registering irq %d (s3c irq)\n", irqno); | 735 | //irqdbf("registering irq %d (s3c irq)\n", irqno); |
751 | set_irq_chip(irqno, &s3c_irq_chip); | 736 | set_irq_chip(irqno, &s3c_irq_chip); |
752 | set_irq_handler(irqno, do_edge_IRQ); | 737 | set_irq_handler(irqno, handle_edge_irq); |
753 | set_irq_flags(irqno, IRQF_VALID); | 738 | set_irq_flags(irqno, IRQF_VALID); |
754 | } | 739 | } |
755 | } | 740 | } |
@@ -769,14 +754,14 @@ void __init s3c24xx_init_irq(void) | |||
769 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 754 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
770 | irqdbf("registering irq %d (ext int)\n", irqno); | 755 | irqdbf("registering irq %d (ext int)\n", irqno); |
771 | set_irq_chip(irqno, &s3c_irq_eint0t4); | 756 | set_irq_chip(irqno, &s3c_irq_eint0t4); |
772 | set_irq_handler(irqno, do_edge_IRQ); | 757 | set_irq_handler(irqno, handle_edge_irq); |
773 | set_irq_flags(irqno, IRQF_VALID); | 758 | set_irq_flags(irqno, IRQF_VALID); |
774 | } | 759 | } |
775 | 760 | ||
776 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { | 761 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { |
777 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); | 762 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); |
778 | set_irq_chip(irqno, &s3c_irqext_chip); | 763 | set_irq_chip(irqno, &s3c_irqext_chip); |
779 | set_irq_handler(irqno, do_edge_IRQ); | 764 | set_irq_handler(irqno, handle_edge_irq); |
780 | set_irq_flags(irqno, IRQF_VALID); | 765 | set_irq_flags(irqno, IRQF_VALID); |
781 | } | 766 | } |
782 | 767 | ||
@@ -787,28 +772,28 @@ void __init s3c24xx_init_irq(void) | |||
787 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { | 772 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { |
788 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); | 773 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); |
789 | set_irq_chip(irqno, &s3c_irq_uart0); | 774 | set_irq_chip(irqno, &s3c_irq_uart0); |
790 | set_irq_handler(irqno, do_level_IRQ); | 775 | set_irq_handler(irqno, handle_level_irq); |
791 | set_irq_flags(irqno, IRQF_VALID); | 776 | set_irq_flags(irqno, IRQF_VALID); |
792 | } | 777 | } |
793 | 778 | ||
794 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { | 779 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { |
795 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); | 780 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); |
796 | set_irq_chip(irqno, &s3c_irq_uart1); | 781 | set_irq_chip(irqno, &s3c_irq_uart1); |
797 | set_irq_handler(irqno, do_level_IRQ); | 782 | set_irq_handler(irqno, handle_level_irq); |
798 | set_irq_flags(irqno, IRQF_VALID); | 783 | set_irq_flags(irqno, IRQF_VALID); |
799 | } | 784 | } |
800 | 785 | ||
801 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { | 786 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { |
802 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); | 787 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); |
803 | set_irq_chip(irqno, &s3c_irq_uart2); | 788 | set_irq_chip(irqno, &s3c_irq_uart2); |
804 | set_irq_handler(irqno, do_level_IRQ); | 789 | set_irq_handler(irqno, handle_level_irq); |
805 | set_irq_flags(irqno, IRQF_VALID); | 790 | set_irq_flags(irqno, IRQF_VALID); |
806 | } | 791 | } |
807 | 792 | ||
808 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { | 793 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { |
809 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); | 794 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); |
810 | set_irq_chip(irqno, &s3c_irq_adc); | 795 | set_irq_chip(irqno, &s3c_irq_adc); |
811 | set_irq_handler(irqno, do_edge_IRQ); | 796 | set_irq_handler(irqno, handle_edge_irq); |
812 | set_irq_flags(irqno, IRQF_VALID); | 797 | set_irq_flags(irqno, IRQF_VALID); |
813 | } | 798 | } |
814 | 799 | ||