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-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/system-reset.h36
2 files changed, 3 insertions, 35 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 255fdfeaf957..e99b212cb1ca 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -84,7 +84,6 @@
84 84
85#define S3C24XX_PA_IRQ S3C2410_PA_IRQ 85#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
86#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL 86#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
87#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
88#define S3C24XX_PA_DMA S3C2410_PA_DMA 87#define S3C24XX_PA_DMA S3C2410_PA_DMA
89#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR 88#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
90#define S3C24XX_PA_LCD S3C2410_PA_LCD 89#define S3C24XX_PA_LCD S3C2410_PA_LCD
@@ -102,6 +101,7 @@
102 101
103#define S3C_PA_IIC S3C2410_PA_IIC 102#define S3C_PA_IIC S3C2410_PA_IIC
104#define S3C_PA_UART S3C24XX_PA_UART 103#define S3C_PA_UART S3C24XX_PA_UART
104#define S3C_PA_USBHOST S3C2410_PA_USBHOST
105#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC 105#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
106 106
107#endif /* __ASM_ARCH_MAP_H */ 107#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index b8687f71c304..6faadcee7729 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -11,21 +11,13 @@
11*/ 11*/
12 12
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14#include <linux/io.h> 14#include <plat/watchdog-reset.h>
15
16#include <plat/regs-watchdog.h>
17#include <mach/regs-clock.h>
18
19#include <linux/clk.h>
20#include <linux/err.h>
21 15
22extern void (*s3c24xx_reset_hook)(void); 16extern void (*s3c24xx_reset_hook)(void);
23 17
24static void 18static void
25arch_reset(char mode, const char *cmd) 19arch_reset(char mode, const char *cmd)
26{ 20{
27 struct clk *wdtclk;
28
29 if (mode == 's') { 21 if (mode == 's') {
30 cpu_reset(0); 22 cpu_reset(0);
31 } 23 }
@@ -33,31 +25,7 @@ arch_reset(char mode, const char *cmd)
33 if (s3c24xx_reset_hook) 25 if (s3c24xx_reset_hook)
34 s3c24xx_reset_hook(); 26 s3c24xx_reset_hook();
35 27
36 printk("arch_reset: attempting watchdog reset\n"); 28 arch_wdt_reset();
37
38 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
39
40 wdtclk = clk_get(NULL, "watchdog");
41 if (!IS_ERR(wdtclk)) {
42 clk_enable(wdtclk);
43 } else
44 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
45
46 /* put initial values into count and data */
47 __raw_writel(0x80, S3C2410_WTCNT);
48 __raw_writel(0x80, S3C2410_WTDAT);
49
50 /* set the watchdog to go and reset... */
51 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
52 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
53
54 /* wait for reset to assert... */
55 mdelay(500);
56
57 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
58
59 /* delay to allow the serial port to show the message */
60 mdelay(50);
61 29
62 /* we'll take a jump through zero as a poor second */ 30 /* we'll take a jump through zero as a poor second */
63 cpu_reset(0); 31 cpu_reset(0);