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Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h')
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 44494a56e68b..5e06c7265835 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -37,6 +37,10 @@
37#define S3C2443_SYSID S3C2443_CLKREG(0x5C) 37#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
38#define S3C2443_PWRCFG S3C2443_CLKREG(0x60) 38#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
39#define S3C2443_RSTCON S3C2443_CLKREG(0x64) 39#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
40#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
41#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
42#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
43#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
40 44
41#define S3C2443_SWRST_RESET (0x533c2443) 45#define S3C2443_SWRST_RESET (0x533c2443)
42 46
@@ -121,6 +125,27 @@
121 125
122#define S3C2443_PWRCFG_SLEEP (1<<15) 126#define S3C2443_PWRCFG_SLEEP (1<<15)
123 127
128#define S3C2443_PWRCFG_USBPHY (1 << 4)
129
130#define S3C2443_URSTCON_FUNCRST (1 << 2)
131#define S3C2443_URSTCON_PHYRST (1 << 0)
132
133#define S3C2443_PHYCTRL_CLKSEL (1 << 3)
134#define S3C2443_PHYCTRL_EXTCLK (1 << 2)
135#define S3C2443_PHYCTRL_PLLSEL (1 << 1)
136#define S3C2443_PHYCTRL_DSPORT (1 << 0)
137
138#define S3C2443_PHYPWR_COMMON_ON (1 << 31)
139#define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
140#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
141#define S3C2443_PHYPWR_XO_ON (1 << 2)
142#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
143#define S3C2443_PHYPWR_FSUSPEND (1 << 0)
144
145#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
146#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
147#define S3C2443_UCLKCON_TCLKEN (1 << 0)
148
124#include <asm/div64.h> 149#include <asm/div64.h>
125 150
126static inline unsigned int 151static inline unsigned int