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Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-gpio.h')
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h22
1 files changed, 2 insertions, 20 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index a6384239eddf..a0a89d429296 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -17,29 +17,11 @@
17#include <mach/gpio-nrs.h> 17#include <mach/gpio-nrs.h>
18 18
19#ifdef CONFIG_CPU_S3C2400 19#ifdef CONFIG_CPU_S3C2400
20#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) 20#define S3C24XX_MISCCR S3C2400_MISCCR
21#define S3C24XX_MISCCR S3C2400_MISCCR
22#else 21#else
23#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) 22#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
24#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
25#endif /* CONFIG_CPU_S3C2400 */ 23#endif /* CONFIG_CPU_S3C2400 */
26 24
27
28/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
29
30#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)
31#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))
32#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \
33 (2 * (S3C2400_BANKNUM(pin)-2)))
34
35#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \
36 S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
37 S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
38
39
40#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
41#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
42
43/* general configuration options */ 25/* general configuration options */
44 26
45#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 27#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)