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-rw-r--r--arch/arm/mach-realview/Kconfig15
-rw-r--r--arch/arm/mach-realview/Makefile2
-rw-r--r--arch/arm/mach-realview/core.c53
-rw-r--r--arch/arm/mach-realview/core.h5
-rw-r--r--arch/arm/mach-realview/platsmp.c56
-rw-r--r--arch/arm/mach-realview/realview_eb.c149
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c292
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c342
8 files changed, 819 insertions, 95 deletions
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 39b3bb7f1020..5ccde7cf39e8 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -10,7 +10,6 @@ config MACH_REALVIEW_EB
10config REALVIEW_EB_ARM11MP 10config REALVIEW_EB_ARM11MP
11 bool "Support ARM11MPCore tile" 11 bool "Support ARM11MPCore tile"
12 depends on MACH_REALVIEW_EB 12 depends on MACH_REALVIEW_EB
13 select CACHE_L2X0
14 help 13 help
15 Enable support for the ARM11MPCore tile on the Realview platform. 14 Enable support for the ARM11MPCore tile on the Realview platform.
16 15
@@ -24,4 +23,18 @@ config REALVIEW_EB_ARM11MP_REVB
24 kernel built with this option enabled is not compatible with 23 kernel built with this option enabled is not compatible with
25 other revisions of the ARM11MPCore tile. 24 other revisions of the ARM11MPCore tile.
26 25
26config MACH_REALVIEW_PB11MP
27 bool "Support RealView/PB11MPCore platform"
28 select ARM_GIC
29 help
30 Include support for the ARM(R) RealView MPCore Platform Baseboard.
31 PB11MPCore is a platform with an on-board ARM11MPCore and has
32 support for PCI-E and Compact Flash.
33
34config MACH_REALVIEW_PB1176
35 bool "Support RealView/PB1176 platform"
36 select ARM_GIC
37 help
38 Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
39
27endmenu 40endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index ca1e390c3c28..d2ae077431dd 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -4,5 +4,7 @@
4 4
5obj-y := core.o clock.o 5obj-y := core.o clock.o
6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o 6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
7obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
8obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
7obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o 9obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 10obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 98aefc9f4df3..131990d196f5 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -109,22 +109,21 @@ static struct flash_platform_data realview_flash_data = {
109 .set_vpp = realview_flash_set_vpp, 109 .set_vpp = realview_flash_set_vpp,
110}; 110};
111 111
112static struct resource realview_flash_resource = {
113 .start = REALVIEW_FLASH_BASE,
114 .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
115 .flags = IORESOURCE_MEM,
116};
117
118struct platform_device realview_flash_device = { 112struct platform_device realview_flash_device = {
119 .name = "armflash", 113 .name = "armflash",
120 .id = 0, 114 .id = 0,
121 .dev = { 115 .dev = {
122 .platform_data = &realview_flash_data, 116 .platform_data = &realview_flash_data,
123 }, 117 },
124 .num_resources = 1,
125 .resource = &realview_flash_resource,
126}; 118};
127 119
120int realview_flash_register(struct resource *res, u32 num)
121{
122 realview_flash_device.resource = res;
123 realview_flash_device.num_resources = num;
124 return platform_device_register(&realview_flash_device);
125}
126
128static struct resource realview_i2c_resource = { 127static struct resource realview_i2c_resource = {
129 .start = REALVIEW_I2C_BASE, 128 .start = REALVIEW_I2C_BASE,
130 .end = REALVIEW_I2C_BASE + SZ_4K - 1, 129 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
@@ -445,10 +444,10 @@ void realview_leds_event(led_event_t ledevt)
445/* 444/*
446 * Where is the timer (VA)? 445 * Where is the timer (VA)?
447 */ 446 */
448#define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE) 447void __iomem *timer0_va_base;
449#define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20) 448void __iomem *timer1_va_base;
450#define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE) 449void __iomem *timer2_va_base;
451#define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20) 450void __iomem *timer3_va_base;
452 451
453/* 452/*
454 * How long is the timer interval? 453 * How long is the timer interval?
@@ -475,7 +474,7 @@ static void timer_set_mode(enum clock_event_mode mode,
475 474
476 switch(mode) { 475 switch(mode) {
477 case CLOCK_EVT_MODE_PERIODIC: 476 case CLOCK_EVT_MODE_PERIODIC:
478 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); 477 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
479 478
480 ctrl = TIMER_CTRL_PERIODIC; 479 ctrl = TIMER_CTRL_PERIODIC;
481 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; 480 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
@@ -491,16 +490,16 @@ static void timer_set_mode(enum clock_event_mode mode,
491 ctrl = 0; 490 ctrl = 0;
492 } 491 }
493 492
494 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); 493 writel(ctrl, timer0_va_base + TIMER_CTRL);
495} 494}
496 495
497static int timer_set_next_event(unsigned long evt, 496static int timer_set_next_event(unsigned long evt,
498 struct clock_event_device *unused) 497 struct clock_event_device *unused)
499{ 498{
500 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); 499 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
501 500
502 writel(evt, TIMER0_VA_BASE + TIMER_LOAD); 501 writel(evt, timer0_va_base + TIMER_LOAD);
503 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); 502 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
504 503
505 return 0; 504 return 0;
506} 505}
@@ -536,7 +535,7 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
536 struct clock_event_device *evt = &timer0_clockevent; 535 struct clock_event_device *evt = &timer0_clockevent;
537 536
538 /* clear the interrupt */ 537 /* clear the interrupt */
539 writel(1, TIMER0_VA_BASE + TIMER_INTCLR); 538 writel(1, timer0_va_base + TIMER_INTCLR);
540 539
541 evt->event_handler(evt); 540 evt->event_handler(evt);
542 541
@@ -551,7 +550,7 @@ static struct irqaction realview_timer_irq = {
551 550
552static cycle_t realview_get_cycles(void) 551static cycle_t realview_get_cycles(void)
553{ 552{
554 return ~readl(TIMER3_VA_BASE + TIMER_VALUE); 553 return ~readl(timer3_va_base + TIMER_VALUE);
555} 554}
556 555
557static struct clocksource clocksource_realview = { 556static struct clocksource clocksource_realview = {
@@ -566,11 +565,11 @@ static struct clocksource clocksource_realview = {
566static void __init realview_clocksource_init(void) 565static void __init realview_clocksource_init(void)
567{ 566{
568 /* setup timer 0 as free-running clocksource */ 567 /* setup timer 0 as free-running clocksource */
569 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 568 writel(0, timer3_va_base + TIMER_CTRL);
570 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); 569 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
571 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); 570 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
572 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, 571 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
573 TIMER3_VA_BASE + TIMER_CTRL); 572 timer3_va_base + TIMER_CTRL);
574 573
575 clocksource_realview.mult = 574 clocksource_realview.mult =
576 clocksource_khz2mult(1000, clocksource_realview.shift); 575 clocksource_khz2mult(1000, clocksource_realview.shift);
@@ -607,10 +606,10 @@ void __init realview_timer_init(unsigned int timer_irq)
607 /* 606 /*
608 * Initialise to a known state (all timers off) 607 * Initialise to a known state (all timers off)
609 */ 608 */
610 writel(0, TIMER0_VA_BASE + TIMER_CTRL); 609 writel(0, timer0_va_base + TIMER_CTRL);
611 writel(0, TIMER1_VA_BASE + TIMER_CTRL); 610 writel(0, timer1_va_base + TIMER_CTRL);
612 writel(0, TIMER2_VA_BASE + TIMER_CTRL); 611 writel(0, timer2_va_base + TIMER_CTRL);
613 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 612 writel(0, timer3_va_base + TIMER_CTRL);
614 613
615 /* 614 /*
616 * Make irqs happen for the system timer 615 * Make irqs happen for the system timer
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 492a14c0d604..33dbbb41a663 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -55,8 +55,13 @@ extern void __iomem *gic_cpu_base_addr;
55extern void __iomem *twd_base_addr; 55extern void __iomem *twd_base_addr;
56extern unsigned int twd_size; 56extern unsigned int twd_size;
57#endif 57#endif
58extern void __iomem *timer0_va_base;
59extern void __iomem *timer1_va_base;
60extern void __iomem *timer2_va_base;
61extern void __iomem *timer3_va_base;
58 62
59extern void realview_leds_event(led_event_t ledevt); 63extern void realview_leds_event(led_event_t ledevt);
60extern void realview_timer_init(unsigned int timer_irq); 64extern void realview_timer_init(unsigned int timer_irq);
65extern int realview_flash_register(struct resource *res, u32 num);
61 66
62#endif 67#endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index de2b7159557d..3e57428affee 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -15,11 +15,14 @@
15#include <linux/smp.h> 15#include <linux/smp.h>
16 16
17#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
18#include <asm/hardware/arm_scu.h>
19#include <asm/hardware.h> 18#include <asm/hardware.h>
20#include <asm/io.h> 19#include <asm/io.h>
21#include <asm/mach-types.h> 20#include <asm/mach-types.h>
22 21
22#include <asm/arch/board-eb.h>
23#include <asm/arch/board-pb11mp.h>
24#include <asm/arch/scu.h>
25
23extern void realview_secondary_startup(void); 26extern void realview_secondary_startup(void);
24 27
25/* 28/*
@@ -31,9 +34,15 @@ volatile int __cpuinitdata pen_release = -1;
31static unsigned int __init get_core_count(void) 34static unsigned int __init get_core_count(void)
32{ 35{
33 unsigned int ncores; 36 unsigned int ncores;
37 void __iomem *scu_base = 0;
38
39 if (machine_is_realview_eb() && core_tile_eb11mp())
40 scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
41 else if (machine_is_realview_pb11mp())
42 scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
34 43
35 if (machine_is_realview_eb() && core_tile_eb11mp()) { 44 if (scu_base) {
36 ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); 45 ncores = __raw_readl(scu_base + SCU_CONFIG);
37 ncores = (ncores & 0x03) + 1; 46 ncores = (ncores & 0x03) + 1;
38 } else 47 } else
39 ncores = 1; 48 ncores = 1;
@@ -41,6 +50,26 @@ static unsigned int __init get_core_count(void)
41 return ncores; 50 return ncores;
42} 51}
43 52
53/*
54 * Setup the SCU
55 */
56static void scu_enable(void)
57{
58 u32 scu_ctrl;
59 void __iomem *scu_base;
60
61 if (machine_is_realview_eb() && core_tile_eb11mp())
62 scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
63 else if (machine_is_realview_pb11mp())
64 scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
65 else
66 BUG();
67
68 scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
69 scu_ctrl |= 1;
70 __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
71}
72
44static DEFINE_SPINLOCK(boot_lock); 73static DEFINE_SPINLOCK(boot_lock);
45 74
46void __cpuinit platform_secondary_init(unsigned int cpu) 75void __cpuinit platform_secondary_init(unsigned int cpu)
@@ -57,7 +86,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
57 * core (e.g. timer irq), then they will not have been enabled 86 * core (e.g. timer irq), then they will not have been enabled
58 * for us: do so 87 * for us: do so
59 */ 88 */
60 gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); 89 if (machine_is_realview_eb() && core_tile_eb11mp())
90 gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
91 else if (machine_is_realview_pb11mp())
92 gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
61 93
62 /* 94 /*
63 * let the primary processor know we're out of the 95 * let the primary processor know we're out of the
@@ -198,7 +230,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
198 * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in 230 * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
199 * realview_timer_init 231 * realview_timer_init
200 */ 232 */
201 if (machine_is_realview_eb() && core_tile_eb11mp()) 233 if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
234 machine_is_realview_pb11mp())
202 local_timer_setup(cpu); 235 local_timer_setup(cpu);
203#endif 236#endif
204 237
@@ -210,11 +243,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
210 cpu_set(i, cpu_present_map); 243 cpu_set(i, cpu_present_map);
211 244
212 /* 245 /*
213 * Do we need any more CPUs? If so, then let them know where 246 * Initialise the SCU if there are more than one CPU and let
214 * to start. Note that, on modern versions of MILO, the "poke" 247 * them know where to start. Note that, on modern versions of
215 * doesn't actually do anything until each individual core is 248 * MILO, the "poke" doesn't actually do anything until each
216 * sent a soft interrupt to get it out of WFI 249 * individual core is sent a soft interrupt to get it out of
250 * WFI
217 */ 251 */
218 if (max_cpus > 1) 252 if (max_cpus > 1) {
253 scu_enable();
219 poke_milo(); 254 poke_milo();
255 }
220} 256}
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 60d9eb810246..5782d83fd886 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -51,13 +51,13 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
51 .length = SZ_4K, 51 .length = SZ_4K,
52 .type = MT_DEVICE, 52 .type = MT_DEVICE,
53 }, { 53 }, {
54 .virtual = IO_ADDRESS(REALVIEW_GIC_CPU_BASE), 54 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
55 .pfn = __phys_to_pfn(REALVIEW_GIC_CPU_BASE), 55 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
56 .length = SZ_4K, 56 .length = SZ_4K,
57 .type = MT_DEVICE, 57 .type = MT_DEVICE,
58 }, { 58 }, {
59 .virtual = IO_ADDRESS(REALVIEW_GIC_DIST_BASE), 59 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
60 .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), 60 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
61 .length = SZ_4K, 61 .length = SZ_4K,
62 .type = MT_DEVICE, 62 .type = MT_DEVICE,
63 }, { 63 }, {
@@ -66,20 +66,20 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
66 .length = SZ_4K, 66 .length = SZ_4K,
67 .type = MT_DEVICE, 67 .type = MT_DEVICE,
68 }, { 68 }, {
69 .virtual = IO_ADDRESS(REALVIEW_TIMER0_1_BASE), 69 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
70 .pfn = __phys_to_pfn(REALVIEW_TIMER0_1_BASE), 70 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
71 .length = SZ_4K, 71 .length = SZ_4K,
72 .type = MT_DEVICE, 72 .type = MT_DEVICE,
73 }, { 73 }, {
74 .virtual = IO_ADDRESS(REALVIEW_TIMER2_3_BASE), 74 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
75 .pfn = __phys_to_pfn(REALVIEW_TIMER2_3_BASE), 75 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
76 .length = SZ_4K, 76 .length = SZ_4K,
77 .type = MT_DEVICE, 77 .type = MT_DEVICE,
78 }, 78 },
79#ifdef CONFIG_DEBUG_LL 79#ifdef CONFIG_DEBUG_LL
80 { 80 {
81 .virtual = IO_ADDRESS(REALVIEW_UART0_BASE), 81 .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
82 .pfn = __phys_to_pfn(REALVIEW_UART0_BASE), 82 .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
83 .length = SZ_4K, 83 .length = SZ_4K,
84 .type = MT_DEVICE, 84 .type = MT_DEVICE,
85 } 85 }
@@ -136,12 +136,12 @@ static void __init realview_eb_map_io(void)
136/* 136/*
137 * These devices are connected directly to the multi-layer AHB switch 137 * These devices are connected directly to the multi-layer AHB switch
138 */ 138 */
139#define SMC_IRQ { NO_IRQ, NO_IRQ } 139#define EB_SMC_IRQ { NO_IRQ, NO_IRQ }
140#define SMC_DMA { 0, 0 } 140#define EB_SMC_DMA { 0, 0 }
141#define MPMC_IRQ { NO_IRQ, NO_IRQ } 141#define MPMC_IRQ { NO_IRQ, NO_IRQ }
142#define MPMC_DMA { 0, 0 } 142#define MPMC_DMA { 0, 0 }
143#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } 143#define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
144#define CLCD_DMA { 0, 0 } 144#define EB_CLCD_DMA { 0, 0 }
145#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } 145#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
146#define DMAC_DMA { 0, 0 } 146#define DMAC_DMA { 0, 0 }
147 147
@@ -150,53 +150,53 @@ static void __init realview_eb_map_io(void)
150 */ 150 */
151#define SCTL_IRQ { NO_IRQ, NO_IRQ } 151#define SCTL_IRQ { NO_IRQ, NO_IRQ }
152#define SCTL_DMA { 0, 0 } 152#define SCTL_DMA { 0, 0 }
153#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } 153#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
154#define WATCHDOG_DMA { 0, 0 } 154#define EB_WATCHDOG_DMA { 0, 0 }
155#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } 155#define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
156#define GPIO0_DMA { 0, 0 } 156#define EB_GPIO0_DMA { 0, 0 }
157#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } 157#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
158#define GPIO1_DMA { 0, 0 } 158#define GPIO1_DMA { 0, 0 }
159#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ } 159#define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
160#define RTC_DMA { 0, 0 } 160#define EB_RTC_DMA { 0, 0 }
161 161
162/* 162/*
163 * These devices are connected via the DMA APB bridge 163 * These devices are connected via the DMA APB bridge
164 */ 164 */
165#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } 165#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
166#define SCI_DMA { 7, 6 } 166#define SCI_DMA { 7, 6 }
167#define UART0_IRQ { IRQ_EB_UART0, NO_IRQ } 167#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
168#define UART0_DMA { 15, 14 } 168#define EB_UART0_DMA { 15, 14 }
169#define UART1_IRQ { IRQ_EB_UART1, NO_IRQ } 169#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
170#define UART1_DMA { 13, 12 } 170#define EB_UART1_DMA { 13, 12 }
171#define UART2_IRQ { IRQ_EB_UART2, NO_IRQ } 171#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
172#define UART2_DMA { 11, 10 } 172#define EB_UART2_DMA { 11, 10 }
173#define UART3_IRQ { IRQ_EB_UART3, NO_IRQ } 173#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
174#define UART3_DMA { 0x86, 0x87 } 174#define EB_UART3_DMA { 0x86, 0x87 }
175#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ } 175#define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
176#define SSP_DMA { 9, 8 } 176#define EB_SSP_DMA { 9, 8 }
177 177
178/* FPGA Primecells */ 178/* FPGA Primecells */
179AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); 179AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
180AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); 180AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
181AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); 181AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
182AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); 182AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
183AMBA_DEVICE(uart3, "fpga:09", UART3, NULL); 183AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL);
184 184
185/* DevChip Primecells */ 185/* DevChip Primecells */
186AMBA_DEVICE(smc, "dev:00", SMC, NULL); 186AMBA_DEVICE(smc, "dev:00", EB_SMC, NULL);
187AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); 187AMBA_DEVICE(clcd, "dev:20", EB_CLCD, &clcd_plat_data);
188AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); 188AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
189AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); 189AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
190AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); 190AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL);
191AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL); 191AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, NULL);
192AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); 192AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
193AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); 193AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
194AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); 194AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL);
195AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); 195AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
196AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); 196AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL);
197AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); 197AMBA_DEVICE(uart1, "dev:f2", EB_UART1, NULL);
198AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); 198AMBA_DEVICE(uart2, "dev:f3", EB_UART2, NULL);
199AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL); 199AMBA_DEVICE(ssp0, "dev:f4", EB_SSP, NULL);
200 200
201static struct amba_device *amba_devs[] __initdata = { 201static struct amba_device *amba_devs[] __initdata = {
202 &dmac_device, 202 &dmac_device,
@@ -223,11 +223,16 @@ static struct amba_device *amba_devs[] __initdata = {
223/* 223/*
224 * RealView EB platform devices 224 * RealView EB platform devices
225 */ 225 */
226static struct resource realview_eb_flash_resource = {
227 .start = REALVIEW_EB_FLASH_BASE,
228 .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
229 .flags = IORESOURCE_MEM,
230};
226 231
227static struct resource realview_eb_smc91x_resources[] = { 232static struct resource realview_eb_eth_resources[] = {
228 [0] = { 233 [0] = {
229 .start = REALVIEW_ETH_BASE, 234 .start = REALVIEW_EB_ETH_BASE,
230 .end = REALVIEW_ETH_BASE + SZ_64K - 1, 235 .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
231 .flags = IORESOURCE_MEM, 236 .flags = IORESOURCE_MEM,
232 }, 237 },
233 [1] = { 238 [1] = {
@@ -237,13 +242,36 @@ static struct resource realview_eb_smc91x_resources[] = {
237 }, 242 },
238}; 243};
239 244
240static struct platform_device realview_eb_smc91x_device = { 245static struct platform_device realview_eb_eth_device = {
241 .name = "smc91x",
242 .id = 0, 246 .id = 0,
243 .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources), 247 .num_resources = ARRAY_SIZE(realview_eb_eth_resources),
244 .resource = realview_eb_smc91x_resources, 248 .resource = realview_eb_eth_resources,
245}; 249};
246 250
251/*
252 * Detect and register the correct Ethernet device. RealView/EB rev D
253 * platforms use the newer SMSC LAN9118 Ethernet chip
254 */
255static int eth_device_register(void)
256{
257 void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
258 u32 idrev;
259
260 if (!eth_addr)
261 return -ENOMEM;
262
263 idrev = readl(eth_addr + 0x50);
264 if ((idrev & 0xFFFF0000) == 0x01180000)
265 /* SMSC LAN9118 chip present */
266 realview_eb_eth_device.name = "smc911x";
267 else
268 /* SMSC 91C111 chip present */
269 realview_eb_eth_device.name = "smc91x";
270
271 iounmap(eth_addr);
272 return platform_device_register(&realview_eb_eth_device);
273}
274
247static void __init gic_init_irq(void) 275static void __init gic_init_irq(void)
248{ 276{
249 if (core_tile_eb11mp()) { 277 if (core_tile_eb11mp()) {
@@ -263,14 +291,14 @@ static void __init gic_init_irq(void)
263 291
264#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB 292#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
265 /* board GIC, secondary */ 293 /* board GIC, secondary */
266 gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64); 294 gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
267 gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE)); 295 gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
268 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); 296 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
269#endif 297#endif
270 } else { 298 } else {
271 /* board GIC, primary */ 299 /* board GIC, primary */
272 gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE); 300 gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
273 gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); 301 gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
274 gic_cpu_init(0, gic_cpu_base_addr); 302 gic_cpu_init(0, gic_cpu_base_addr);
275 } 303 }
276} 304}
@@ -301,14 +329,19 @@ static void realview_eb11mp_fixup(void)
301 kmi1_device.irq[0] = IRQ_EB11MP_KMI1; 329 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
302 330
303 /* platform devices */ 331 /* platform devices */
304 realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH; 332 realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
305 realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; 333 realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
306} 334}
307 335
308static void __init realview_eb_timer_init(void) 336static void __init realview_eb_timer_init(void)
309{ 337{
310 unsigned int timer_irq; 338 unsigned int timer_irq;
311 339
340 timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
341 timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
342 timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
343 timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
344
312 if (core_tile_eb11mp()) { 345 if (core_tile_eb11mp()) {
313#ifdef CONFIG_LOCAL_TIMERS 346#ifdef CONFIG_LOCAL_TIMERS
314 twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); 347 twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
@@ -332,16 +365,18 @@ static void __init realview_eb_init(void)
332 if (core_tile_eb11mp()) { 365 if (core_tile_eb11mp()) {
333 realview_eb11mp_fixup(); 366 realview_eb11mp_fixup();
334 367
368#ifdef CONFIG_CACHE_L2X0
335 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled 369 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
336 * Bits: .... ...0 0111 1001 0000 .... .... .... */ 370 * Bits: .... ...0 0111 1001 0000 .... .... .... */
337 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); 371 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
372#endif
338 } 373 }
339 374
340 clk_register(&realview_clcd_clk); 375 clk_register(&realview_clcd_clk);
341 376
342 platform_device_register(&realview_flash_device); 377 realview_flash_register(&realview_eb_flash_resource, 1);
343 platform_device_register(&realview_eb_smc91x_device);
344 platform_device_register(&realview_i2c_device); 378 platform_device_register(&realview_i2c_device);
379 eth_device_register();
345 380
346 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 381 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
347 struct amba_device *d = amba_devs[i]; 382 struct amba_device *d = amba_devs[i];
@@ -355,8 +390,8 @@ static void __init realview_eb_init(void)
355 390
356MACHINE_START(REALVIEW_EB, "ARM-RealView EB") 391MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
357 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 392 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
358 .phys_io = REALVIEW_UART0_BASE, 393 .phys_io = REALVIEW_EB_UART0_BASE,
359 .io_pg_offst = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc, 394 .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
360 .boot_params = 0x00000100, 395 .boot_params = 0x00000100,
361 .map_io = realview_eb_map_io, 396 .map_io = realview_eb_map_io,
362 .init_irq = gic_init_irq, 397 .init_irq = gic_init_irq,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
new file mode 100644
index 000000000000..cf7f576a5860
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -0,0 +1,292 @@
1/*
2 * linux/arch/arm/mach-realview/realview_pb1176.c
3 *
4 * Copyright (C) 2008 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/sysdev.h>
25#include <linux/amba/bus.h>
26
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/leds.h>
31#include <asm/mach-types.h>
32#include <asm/hardware/gic.h>
33#include <asm/hardware/icst307.h>
34#include <asm/hardware/cache-l2x0.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/flash.h>
38#include <asm/mach/map.h>
39#include <asm/mach/mmc.h>
40#include <asm/mach/time.h>
41
42#include <asm/arch/board-pb1176.h>
43#include <asm/arch/irqs.h>
44
45#include "core.h"
46#include "clock.h"
47
48static struct map_desc realview_pb1176_io_desc[] __initdata = {
49 {
50 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
51 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
52 .length = SZ_4K,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
56 .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE),
57 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
61 .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE),
62 .length = SZ_4K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
66 .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
67 .length = SZ_4K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
71 .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE),
72 .length = SZ_4K,
73 .type = MT_DEVICE,
74 }, {
75 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
76 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
77 .length = SZ_4K,
78 .type = MT_DEVICE,
79 }, {
80 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
81 .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE),
82 .length = SZ_4K,
83 .type = MT_DEVICE,
84 }, {
85 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
86 .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
91 .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE),
92 .length = SZ_8K,
93 .type = MT_DEVICE,
94 },
95#ifdef CONFIG_DEBUG_LL
96 {
97 .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
98 .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE),
99 .length = SZ_4K,
100 .type = MT_DEVICE,
101 },
102#endif
103};
104
105static void __init realview_pb1176_map_io(void)
106{
107 iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
108}
109
110/*
111 * RealView PB1176 AMBA devices
112 */
113#define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ }
114#define GPIO2_DMA { 0, 0 }
115#define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ }
116#define GPIO3_DMA { 0, 0 }
117#define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ }
118#define AACI_DMA { 0x80, 0x81 }
119#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
120#define MMCI0_DMA { 0x84, 0 }
121#define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ }
122#define KMI0_DMA { 0, 0 }
123#define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ }
124#define KMI1_DMA { 0, 0 }
125#define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ }
126#define PB1176_SMC_DMA { 0, 0 }
127#define MPMC_IRQ { NO_IRQ, NO_IRQ }
128#define MPMC_DMA { 0, 0 }
129#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
130#define PB1176_CLCD_DMA { 0, 0 }
131#define DMAC_IRQ { IRQ_PB1176_DMAC, NO_IRQ }
132#define DMAC_DMA { 0, 0 }
133#define SCTL_IRQ { NO_IRQ, NO_IRQ }
134#define SCTL_DMA { 0, 0 }
135#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ }
136#define PB1176_WATCHDOG_DMA { 0, 0 }
137#define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ }
138#define PB1176_GPIO0_DMA { 0, 0 }
139#define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ }
140#define GPIO1_DMA { 0, 0 }
141#define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ }
142#define PB1176_RTC_DMA { 0, 0 }
143#define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ }
144#define SCI_DMA { 7, 6 }
145#define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ }
146#define PB1176_UART0_DMA { 15, 14 }
147#define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ }
148#define PB1176_UART1_DMA { 13, 12 }
149#define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ }
150#define PB1176_UART2_DMA { 11, 10 }
151#define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ }
152#define PB1176_UART3_DMA { 0x86, 0x87 }
153#define PB1176_SSP_IRQ { IRQ_PB1176_SSP, NO_IRQ }
154#define PB1176_SSP_DMA { 9, 8 }
155
156/* FPGA Primecells */
157AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
158AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
159AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
160AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
161AMBA_DEVICE(uart3, "fpga:09", PB1176_UART3, NULL);
162
163/* DevChip Primecells */
164AMBA_DEVICE(smc, "dev:00", PB1176_SMC, NULL);
165AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
166AMBA_DEVICE(wdog, "dev:e1", PB1176_WATCHDOG, NULL);
167AMBA_DEVICE(gpio0, "dev:e4", PB1176_GPIO0, NULL);
168AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
169AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
170AMBA_DEVICE(rtc, "dev:e8", PB1176_RTC, NULL);
171AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
172AMBA_DEVICE(uart0, "dev:f1", PB1176_UART0, NULL);
173AMBA_DEVICE(uart1, "dev:f2", PB1176_UART1, NULL);
174AMBA_DEVICE(uart2, "dev:f3", PB1176_UART2, NULL);
175AMBA_DEVICE(ssp0, "dev:f4", PB1176_SSP, NULL);
176
177/* Primecells on the NEC ISSP chip */
178AMBA_DEVICE(clcd, "issp:20", PB1176_CLCD, &clcd_plat_data);
179//AMBA_DEVICE(dmac, "issp:30", PB1176_DMAC, NULL);
180
181static struct amba_device *amba_devs[] __initdata = {
182// &dmac_device,
183 &uart0_device,
184 &uart1_device,
185 &uart2_device,
186 &uart3_device,
187 &smc_device,
188 &clcd_device,
189 &sctl_device,
190 &wdog_device,
191 &gpio0_device,
192 &gpio1_device,
193 &gpio2_device,
194 &rtc_device,
195 &sci0_device,
196 &ssp0_device,
197 &aaci_device,
198 &mmc0_device,
199 &kmi0_device,
200 &kmi1_device,
201};
202
203/*
204 * RealView PB1176 platform devices
205 */
206static struct resource realview_pb1176_flash_resource = {
207 .start = REALVIEW_PB1176_FLASH_BASE,
208 .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
209 .flags = IORESOURCE_MEM,
210};
211
212static struct resource realview_pb1176_smsc911x_resources[] = {
213 [0] = {
214 .start = REALVIEW_PB1176_ETH_BASE,
215 .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = IRQ_PB1176_ETH,
220 .end = IRQ_PB1176_ETH,
221 .flags = IORESOURCE_IRQ,
222 },
223};
224
225static struct platform_device realview_pb1176_smsc911x_device = {
226 .name = "smc911x",
227 .id = 0,
228 .num_resources = ARRAY_SIZE(realview_pb1176_smsc911x_resources),
229 .resource = realview_pb1176_smsc911x_resources,
230};
231
232static void __init gic_init_irq(void)
233{
234 /* ARM1176 DevChip GIC, primary */
235 gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
236 gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
237 gic_cpu_init(0, gic_cpu_base_addr);
238
239 /* board GIC, secondary */
240 gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
241 gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
242 gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
243}
244
245static void __init realview_pb1176_timer_init(void)
246{
247 timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE);
248 timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20;
249 timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
250 timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
251
252 realview_timer_init(IRQ_DC1176_TIMER0);
253}
254
255static struct sys_timer realview_pb1176_timer = {
256 .init = realview_pb1176_timer_init,
257};
258
259static void __init realview_pb1176_init(void)
260{
261 int i;
262
263#ifdef CONFIG_CACHE_L2X0
264 /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
265 l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
266#endif
267
268 clk_register(&realview_clcd_clk);
269
270 realview_flash_register(&realview_pb1176_flash_resource, 1);
271 platform_device_register(&realview_pb1176_smsc911x_device);
272
273 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
274 struct amba_device *d = amba_devs[i];
275 amba_device_register(d, &iomem_resource);
276 }
277
278#ifdef CONFIG_LEDS
279 leds_event = realview_leds_event;
280#endif
281}
282
283MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
284 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
285 .phys_io = REALVIEW_PB1176_UART0_BASE,
286 .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
287 .boot_params = 0x00000100,
288 .map_io = realview_pb1176_map_io,
289 .init_irq = gic_init_irq,
290 .timer = &realview_pb1176_timer,
291 .init_machine = realview_pb1176_init,
292MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
new file mode 100644
index 000000000000..f7ce1c5a178a
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -0,0 +1,342 @@
1/*
2 * linux/arch/arm/mach-realview/realview_pb11mp.c
3 *
4 * Copyright (C) 2008 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/sysdev.h>
25#include <linux/amba/bus.h>
26
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/leds.h>
31#include <asm/mach-types.h>
32#include <asm/hardware/gic.h>
33#include <asm/hardware/icst307.h>
34#include <asm/hardware/cache-l2x0.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/flash.h>
38#include <asm/mach/map.h>
39#include <asm/mach/mmc.h>
40#include <asm/mach/time.h>
41
42#include <asm/arch/board-pb11mp.h>
43#include <asm/arch/irqs.h>
44
45#include "core.h"
46#include "clock.h"
47
48static struct map_desc realview_pb11mp_io_desc[] __initdata = {
49 {
50 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
51 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
52 .length = SZ_4K,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
56 .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
57 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
61 .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
62 .length = SZ_4K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
66 .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
67 .length = SZ_4K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
71 .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
72 .length = SZ_4K,
73 .type = MT_DEVICE,
74 }, {
75 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
76 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
77 .length = SZ_4K,
78 .type = MT_DEVICE,
79 }, {
80 .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
81 .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
82 .length = SZ_4K,
83 .type = MT_DEVICE,
84 }, {
85 .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
86 .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
91 .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
92 .length = SZ_8K,
93 .type = MT_DEVICE,
94 },
95#ifdef CONFIG_DEBUG_LL
96 {
97 .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
98 .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
99 .length = SZ_4K,
100 .type = MT_DEVICE,
101 },
102#endif
103};
104
105static void __init realview_pb11mp_map_io(void)
106{
107 iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
108}
109
110/*
111 * RealView PB11MPCore AMBA devices
112 */
113
114#define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ }
115#define GPIO2_DMA { 0, 0 }
116#define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ }
117#define GPIO3_DMA { 0, 0 }
118#define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ }
119#define AACI_DMA { 0x80, 0x81 }
120#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
121#define MMCI0_DMA { 0x84, 0 }
122#define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ }
123#define KMI0_DMA { 0, 0 }
124#define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ }
125#define KMI1_DMA { 0, 0 }
126#define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ }
127#define PB11MP_SMC_DMA { 0, 0 }
128#define MPMC_IRQ { NO_IRQ, NO_IRQ }
129#define MPMC_DMA { 0, 0 }
130#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ }
131#define PB11MP_CLCD_DMA { 0, 0 }
132#define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ }
133#define DMAC_DMA { 0, 0 }
134#define SCTL_IRQ { NO_IRQ, NO_IRQ }
135#define SCTL_DMA { 0, 0 }
136#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ }
137#define PB11MP_WATCHDOG_DMA { 0, 0 }
138#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ }
139#define PB11MP_GPIO0_DMA { 0, 0 }
140#define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ }
141#define GPIO1_DMA { 0, 0 }
142#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ }
143#define PB11MP_RTC_DMA { 0, 0 }
144#define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ }
145#define SCI_DMA { 7, 6 }
146#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ }
147#define PB11MP_UART0_DMA { 15, 14 }
148#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ }
149#define PB11MP_UART1_DMA { 13, 12 }
150#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ }
151#define PB11MP_UART2_DMA { 11, 10 }
152#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ }
153#define PB11MP_UART3_DMA { 0x86, 0x87 }
154#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ }
155#define PB11MP_SSP_DMA { 9, 8 }
156
157/* FPGA Primecells */
158AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
159AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
160AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
161AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
162AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL);
163
164/* DevChip Primecells */
165AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL);
166AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
167AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL);
168AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL);
169AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
170AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
171AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL);
172AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
173AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL);
174AMBA_DEVICE(uart1, "dev:f2", PB11MP_UART1, NULL);
175AMBA_DEVICE(uart2, "dev:f3", PB11MP_UART2, NULL);
176AMBA_DEVICE(ssp0, "dev:f4", PB11MP_SSP, NULL);
177
178/* Primecells on the NEC ISSP chip */
179AMBA_DEVICE(clcd, "issp:20", PB11MP_CLCD, &clcd_plat_data);
180AMBA_DEVICE(dmac, "issp:30", DMAC, NULL);
181
182static struct amba_device *amba_devs[] __initdata = {
183 &dmac_device,
184 &uart0_device,
185 &uart1_device,
186 &uart2_device,
187 &uart3_device,
188 &smc_device,
189 &clcd_device,
190 &sctl_device,
191 &wdog_device,
192 &gpio0_device,
193 &gpio1_device,
194 &gpio2_device,
195 &rtc_device,
196 &sci0_device,
197 &ssp0_device,
198 &aaci_device,
199 &mmc0_device,
200 &kmi0_device,
201 &kmi1_device,
202};
203
204/*
205 * RealView PB11MPCore platform devices
206 */
207static struct resource realview_pb11mp_flash_resource[] = {
208 [0] = {
209 .start = REALVIEW_PB11MP_FLASH0_BASE,
210 .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
211 .flags = IORESOURCE_MEM,
212 },
213 [1] = {
214 .start = REALVIEW_PB11MP_FLASH1_BASE,
215 .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
216 .flags = IORESOURCE_MEM,
217 },
218};
219
220static struct resource realview_pb11mp_smsc911x_resources[] = {
221 [0] = {
222 .start = REALVIEW_PB11MP_ETH_BASE,
223 .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = IRQ_TC11MP_ETH,
228 .end = IRQ_TC11MP_ETH,
229 .flags = IORESOURCE_IRQ,
230 },
231};
232
233static struct platform_device realview_pb11mp_smsc911x_device = {
234 .name = "smc911x",
235 .id = 0,
236 .num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources),
237 .resource = realview_pb11mp_smsc911x_resources,
238};
239
240struct resource realview_pb11mp_cf_resources[] = {
241 [0] = {
242 .start = REALVIEW_PB11MP_CF_BASE,
243 .end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1,
244 .flags = IORESOURCE_MEM,
245 },
246 [1] = {
247 .start = REALVIEW_PB11MP_CF_MEM_BASE,
248 .end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1,
249 .flags = IORESOURCE_MEM,
250 },
251 [2] = {
252 .start = -1, /* FIXME: Find correct irq */
253 .end = -1,
254 .flags = IORESOURCE_IRQ,
255 },
256};
257
258struct platform_device realview_pb11mp_cf_device = {
259 .name = "compactflash",
260 .id = 0,
261 .num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources),
262 .resource = realview_pb11mp_cf_resources,
263};
264
265static void __init gic_init_irq(void)
266{
267 unsigned int pldctrl;
268
269 /* new irq mode with no DCC */
270 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
271 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
272 pldctrl |= 2 << 22;
273 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
274 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
275
276 /* ARM11MPCore test chip GIC, primary */
277 gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
278 gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
279 gic_cpu_init(0, gic_cpu_base_addr);
280
281 /* board GIC, secondary */
282 gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
283 gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
284 gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
285}
286
287static void __init realview_pb11mp_timer_init(void)
288{
289 timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
290 timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
291 timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
292 timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
293
294#ifdef CONFIG_LOCAL_TIMERS
295 twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE);
296 twd_size = REALVIEW_TC11MP_TWD_SIZE;
297#endif
298 realview_timer_init(IRQ_TC11MP_TIMER0_1);
299}
300
301static struct sys_timer realview_pb11mp_timer = {
302 .init = realview_pb11mp_timer_init,
303};
304
305static void __init realview_pb11mp_init(void)
306{
307 int i;
308
309#ifdef CONFIG_CACHE_L2X0
310 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
311 * Bits: .... ...0 0111 1001 0000 .... .... .... */
312 l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
313#endif
314
315 clk_register(&realview_clcd_clk);
316
317 realview_flash_register(realview_pb11mp_flash_resource,
318 ARRAY_SIZE(realview_pb11mp_flash_resource));
319 platform_device_register(&realview_pb11mp_smsc911x_device);
320 platform_device_register(&realview_i2c_device);
321 platform_device_register(&realview_pb11mp_cf_device);
322
323 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
324 struct amba_device *d = amba_devs[i];
325 amba_device_register(d, &iomem_resource);
326 }
327
328#ifdef CONFIG_LEDS
329 leds_event = realview_leds_event;
330#endif
331}
332
333MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
334 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
335 .phys_io = REALVIEW_PB11MP_UART0_BASE,
336 .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
337 .boot_params = 0x00000100,
338 .map_io = realview_pb11mp_map_io,
339 .init_irq = gic_init_irq,
340 .timer = &realview_pb11mp_timer,
341 .init_machine = realview_pb11mp_init,
342MACHINE_END
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