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-rw-r--r--arch/arm/mach-realview/platsmp.c98
1 files changed, 3 insertions, 95 deletions
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 6959d13d908a..23919229e12d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -10,44 +10,21 @@
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/jiffies.h>
16#include <linux/smp.h> 13#include <linux/smp.h>
17#include <linux/io.h> 14#include <linux/io.h>
18 15
19#include <asm/cacheflush.h>
20#include <mach/hardware.h> 16#include <mach/hardware.h>
21#include <asm/mach-types.h> 17#include <asm/mach-types.h>
18#include <asm/smp_scu.h>
22#include <asm/unified.h> 19#include <asm/unified.h>
23 20
24#include <mach/board-eb.h> 21#include <mach/board-eb.h>
25#include <mach/board-pb11mp.h> 22#include <mach/board-pb11mp.h>
26#include <mach/board-pbx.h> 23#include <mach/board-pbx.h>
27#include <asm/smp_scu.h>
28 24
29#include "core.h" 25#include "core.h"
30 26
31extern void realview_secondary_startup(void); 27extern void versatile_secondary_startup(void);
32
33/*
34 * control for which core is the next to come out of the secondary
35 * boot "holding pen"
36 */
37volatile int __cpuinitdata pen_release = -1;
38
39/*
40 * Write pen_release in a way that is guaranteed to be visible to all
41 * observers, irrespective of whether they're taking part in coherency
42 * or not. This is necessary for the hotplug code to work reliably.
43 */
44static void __cpuinit write_pen_release(int val)
45{
46 pen_release = val;
47 smp_wmb();
48 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
49 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
50}
51 28
52static void __iomem *scu_base_addr(void) 29static void __iomem *scu_base_addr(void)
53{ 30{
@@ -62,75 +39,6 @@ static void __iomem *scu_base_addr(void)
62 return (void __iomem *)0; 39 return (void __iomem *)0;
63} 40}
64 41
65static DEFINE_SPINLOCK(boot_lock);
66
67void __cpuinit platform_secondary_init(unsigned int cpu)
68{
69 /*
70 * if any interrupts are already enabled for the primary
71 * core (e.g. timer irq), then they will not have been enabled
72 * for us: do so
73 */
74 gic_secondary_init(0);
75
76 /*
77 * let the primary processor know we're out of the
78 * pen, then head off into the C entry point
79 */
80 write_pen_release(-1);
81
82 /*
83 * Synchronise with the boot thread.
84 */
85 spin_lock(&boot_lock);
86 spin_unlock(&boot_lock);
87}
88
89int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
90{
91 unsigned long timeout;
92
93 /*
94 * set synchronisation state between this boot processor
95 * and the secondary one
96 */
97 spin_lock(&boot_lock);
98
99 /*
100 * The secondary processor is waiting to be released from
101 * the holding pen - release it, then wait for it to flag
102 * that it has been released by resetting pen_release.
103 *
104 * Note that "pen_release" is the hardware CPU ID, whereas
105 * "cpu" is Linux's internal ID.
106 */
107 write_pen_release(cpu);
108
109 /*
110 * Send the secondary CPU a soft interrupt, thereby causing
111 * the boot monitor to read the system wide flags register,
112 * and branch to the address found there.
113 */
114 smp_cross_call(cpumask_of(cpu), 1);
115
116 timeout = jiffies + (1 * HZ);
117 while (time_before(jiffies, timeout)) {
118 smp_rmb();
119 if (pen_release == -1)
120 break;
121
122 udelay(10);
123 }
124
125 /*
126 * now the secondary core is starting up let it run its
127 * calibrations, then wait for it to finish
128 */
129 spin_unlock(&boot_lock);
130
131 return pen_release != -1 ? -ENOSYS : 0;
132}
133
134/* 42/*
135 * Initialise the CPU possible map early - this describes the CPUs 43 * Initialise the CPU possible map early - this describes the CPUs
136 * which may be present or become present in the system. 44 * which may be present or become present in the system.
@@ -174,6 +82,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
174 * until it receives a soft interrupt, and then the 82 * until it receives a soft interrupt, and then the
175 * secondary CPU branches to this address. 83 * secondary CPU branches to this address.
176 */ 84 */
177 __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)), 85 __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
178 __io_address(REALVIEW_SYS_FLAGSSET)); 86 __io_address(REALVIEW_SYS_FLAGSSET));
179} 87}