diff options
Diffstat (limited to 'arch/arm/mach-pxa')
-rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-lcd.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h index f817878d256b..c15df557fa8a 100644 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h | |||
@@ -12,13 +12,19 @@ | |||
12 | #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ | 12 | #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ |
13 | #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ | 13 | #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ |
14 | #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ | 14 | #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ |
15 | #define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ | ||
16 | #define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ | ||
17 | #define LCSR (0x038) /* LCD Controller Status Register */ | 15 | #define LCSR (0x038) /* LCD Controller Status Register */ |
18 | #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ | 16 | #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ |
19 | #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ | 17 | #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ |
20 | #define TMEDCR (0x044) /* TMED Control Register */ | 18 | #define TMEDCR (0x044) /* TMED Control Register */ |
21 | 19 | ||
20 | #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ | ||
21 | #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ | ||
22 | #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ | ||
23 | #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ | ||
24 | #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ | ||
25 | #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ | ||
26 | #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ | ||
27 | |||
22 | #define CMDCR (0x100) /* Command Control Register */ | 28 | #define CMDCR (0x100) /* Command Control Register */ |
23 | #define PRSR (0x104) /* Panel Read Status Register */ | 29 | #define PRSR (0x104) /* Panel Read Status Register */ |
24 | 30 | ||