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-rw-r--r--arch/arm/mach-pxa/Kconfig8
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/corgi_lcd.c289
-rw-r--r--arch/arm/mach-pxa/corgi_ssp.c276
-rw-r--r--arch/arm/mach-pxa/include/mach/corgi.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/spitz.h1
-rw-r--r--arch/arm/mach-pxa/sharpsl_pm.c17
7 files changed, 591 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index f781873431f3..a062235e83a8 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -71,6 +71,14 @@ config PXA_SHARPSL
71 SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) 71 SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
72 handheld computer. 72 handheld computer.
73 73
74config CORGI_SSP_DEPRECATED
75 bool
76 select PXA_SSP
77 help
78 This option will include corgi_ssp.c and corgi_lcd.c
79 that corgi_ts.c and other legacy drivers (corgi_bl.c
80 and sharpsl_pm.c) may depend on.
81
74config MACH_POODLE 82config MACH_POODLE
75 bool "Enable Sharp SL-5600 (Poodle) Support" 83 bool "Enable Sharp SL-5600 (Poodle) Support"
76 depends on PXA_SHARPSL 84 depends on PXA_SHARPSL
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index d31c9979cfa3..d64c68b232e3 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
37obj-$(CONFIG_MACH_COLIBRI) += colibri.o 37obj-$(CONFIG_MACH_COLIBRI) += colibri.o
38obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o 38obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o
39obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o 39obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
40obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o
40obj-$(CONFIG_MACH_POODLE) += poodle.o 41obj-$(CONFIG_MACH_POODLE) += poodle.o
41obj-$(CONFIG_MACH_PCM027) += pcm027.o 42obj-$(CONFIG_MACH_PCM027) += pcm027.o
42obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o 43obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
new file mode 100644
index 000000000000..411607bc1fc2
--- /dev/null
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -0,0 +1,289 @@
1/*
2 * linux/arch/arm/mach-pxa/corgi_lcd.c
3 *
4 * Corgi/Spitz LCD Specific Code
5 *
6 * Copyright (C) 2005 Richard Purdie
7 *
8 * Connectivity:
9 * Corgi - LCD to ATI Imageon w100 (Wallaby)
10 * Spitz - LCD to PXA Framebuffer
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/delay.h>
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21#include <linux/module.h>
22#include <linux/string.h>
23#include <mach/corgi.h>
24#include <mach/hardware.h>
25#include <mach/pxa-regs.h>
26#include <mach/sharpsl.h>
27#include <mach/spitz.h>
28#include <asm/hardware/scoop.h>
29#include <asm/mach/sharpsl_param.h>
30#include "generic.h"
31
32/* Register Addresses */
33#define RESCTL_ADRS 0x00
34#define PHACTRL_ADRS 0x01
35#define DUTYCTRL_ADRS 0x02
36#define POWERREG0_ADRS 0x03
37#define POWERREG1_ADRS 0x04
38#define GPOR3_ADRS 0x05
39#define PICTRL_ADRS 0x06
40#define POLCTRL_ADRS 0x07
41
42/* Register Bit Definitions */
43#define RESCTL_QVGA 0x01
44#define RESCTL_VGA 0x00
45
46#define POWER1_VW_ON 0x01 /* VW Supply FET ON */
47#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
48#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
49
50#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */
51#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
52#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
53
54#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
55#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
56#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
57#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
58#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
59
60#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
61#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
62#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
63
64#define PICTRL_INIT_STATE 0x01
65#define PICTRL_INIOFF 0x02
66#define PICTRL_POWER_DOWN 0x04
67#define PICTRL_COM_SIGNAL_OFF 0x08
68#define PICTRL_DAC_SIGNAL_OFF 0x10
69
70#define POLCTRL_SYNC_POL_FALL 0x01
71#define POLCTRL_EN_POL_FALL 0x02
72#define POLCTRL_DATA_POL_FALL 0x04
73#define POLCTRL_SYNC_ACT_H 0x08
74#define POLCTRL_EN_ACT_L 0x10
75
76#define POLCTRL_SYNC_POL_RISE 0x00
77#define POLCTRL_EN_POL_RISE 0x00
78#define POLCTRL_DATA_POL_RISE 0x00
79#define POLCTRL_SYNC_ACT_L 0x00
80#define POLCTRL_EN_ACT_H 0x00
81
82#define PHACTRL_PHASE_MANUAL 0x01
83#define DEFAULT_PHAD_QVGA (9)
84#define DEFAULT_COMADJ (125)
85
86/*
87 * This is only a psuedo I2C interface. We can't use the standard kernel
88 * routines as the interface is write only. We just assume the data is acked...
89 */
90static void lcdtg_ssp_i2c_send(u8 data)
91{
92 corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
93 udelay(10);
94}
95
96static void lcdtg_i2c_send_bit(u8 data)
97{
98 lcdtg_ssp_i2c_send(data);
99 lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
100 lcdtg_ssp_i2c_send(data);
101}
102
103static void lcdtg_i2c_send_start(u8 base)
104{
105 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
106 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
107 lcdtg_ssp_i2c_send(base);
108}
109
110static void lcdtg_i2c_send_stop(u8 base)
111{
112 lcdtg_ssp_i2c_send(base);
113 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
114 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
115}
116
117static void lcdtg_i2c_send_byte(u8 base, u8 data)
118{
119 int i;
120 for (i = 0; i < 8; i++) {
121 if (data & 0x80)
122 lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
123 else
124 lcdtg_i2c_send_bit(base);
125 data <<= 1;
126 }
127}
128
129static void lcdtg_i2c_wait_ack(u8 base)
130{
131 lcdtg_i2c_send_bit(base);
132}
133
134static void lcdtg_set_common_voltage(u8 base_data, u8 data)
135{
136 /* Set Common Voltage to M62332FP via I2C */
137 lcdtg_i2c_send_start(base_data);
138 lcdtg_i2c_send_byte(base_data, 0x9c);
139 lcdtg_i2c_wait_ack(base_data);
140 lcdtg_i2c_send_byte(base_data, 0x00);
141 lcdtg_i2c_wait_ack(base_data);
142 lcdtg_i2c_send_byte(base_data, data);
143 lcdtg_i2c_wait_ack(base_data);
144 lcdtg_i2c_send_stop(base_data);
145}
146
147/* Set Phase Adjust */
148static void lcdtg_set_phadadj(int mode)
149{
150 int adj;
151 switch(mode) {
152 case 480:
153 case 640:
154 /* Setting for VGA */
155 adj = sharpsl_param.phadadj;
156 if (adj < 0) {
157 adj = PHACTRL_PHASE_MANUAL;
158 } else {
159 adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
160 }
161 break;
162 case 240:
163 case 320:
164 default:
165 /* Setting for QVGA */
166 adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
167 break;
168 }
169
170 corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
171}
172
173static int lcd_inited;
174
175void corgi_lcdtg_hw_init(int mode)
176{
177 if (!lcd_inited) {
178 int comadj;
179
180 /* Initialize Internal Logic & Port */
181 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
182 | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
183
184 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
185 | POWER0_COM_OFF | POWER0_VCC5_OFF);
186
187 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
188
189 /* VDD(+8V), SVSS(-4V) ON */
190 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
191 mdelay(3);
192
193 /* DAC ON */
194 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
195 | POWER0_COM_OFF | POWER0_VCC5_OFF);
196
197 /* INIB = H, INI = L */
198 /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
199 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
200
201 /* Set Common Voltage */
202 comadj = sharpsl_param.comadj;
203 if (comadj < 0)
204 comadj = DEFAULT_COMADJ;
205 lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
206
207 /* VCC5 ON, DAC ON */
208 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
209 POWER0_COM_OFF | POWER0_VCC5_ON);
210
211 /* GVSS(-8V) ON, VDD ON */
212 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
213 mdelay(2);
214
215 /* COM SIGNAL ON (PICTL[3] = L) */
216 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
217
218 /* COM ON, DAC ON, VCC5_ON */
219 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
220 | POWER0_COM_ON | POWER0_VCC5_ON);
221
222 /* VW ON, GVSS ON, VDD ON */
223 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
224
225 /* Signals output enable */
226 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
227
228 /* Set Phase Adjust */
229 lcdtg_set_phadadj(mode);
230
231 /* Initialize for Input Signals from ATI */
232 corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
233 | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
234 udelay(1000);
235
236 lcd_inited=1;
237 } else {
238 lcdtg_set_phadadj(mode);
239 }
240
241 switch(mode) {
242 case 480:
243 case 640:
244 /* Set Lcd Resolution (VGA) */
245 corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
246 break;
247 case 240:
248 case 320:
249 default:
250 /* Set Lcd Resolution (QVGA) */
251 corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
252 break;
253 }
254}
255
256void corgi_lcdtg_suspend(void)
257{
258 /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
259 mdelay(34);
260
261 /* (1)VW OFF */
262 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
263
264 /* (2)COM OFF */
265 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
266 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
267
268 /* (3)Set Common Voltage Bias 0V */
269 lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
270
271 /* (4)GVSS OFF */
272 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
273
274 /* (5)VCC5 OFF */
275 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
276
277 /* (6)Set PDWN, INIOFF, DACOFF */
278 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
279 PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
280
281 /* (7)DAC OFF */
282 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
283
284 /* (8)VDD OFF */
285 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
286
287 lcd_inited = 0;
288}
289
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
new file mode 100644
index 000000000000..8e2f2215c4ba
--- /dev/null
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -0,0 +1,276 @@
1/*
2 * SSP control code for Sharp Corgi devices
3 *
4 * Copyright (c) 2004-2005 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <mach/hardware.h>
20#include <asm/mach-types.h>
21
22#include <mach/ssp.h>
23#include <mach/pxa-regs.h>
24#include <mach/pxa2xx-gpio.h>
25#include <mach/regs-ssp.h>
26#include "sharpsl.h"
27
28static DEFINE_SPINLOCK(corgi_ssp_lock);
29static struct ssp_dev corgi_ssp_dev;
30static struct ssp_state corgi_ssp_state;
31static struct corgissp_machinfo *ssp_machinfo;
32
33/*
34 * There are three devices connected to the SSP interface:
35 * 1. A touchscreen controller (TI ADS7846 compatible)
36 * 2. An LCD controller (with some Backlight functionality)
37 * 3. A battery monitoring IC (Maxim MAX1111)
38 *
39 * Each device uses a different speed/mode of communication.
40 *
41 * The touchscreen is very sensitive and the most frequently used
42 * so the port is left configured for this.
43 *
44 * Devices are selected using Chip Selects on GPIOs.
45 */
46
47/*
48 * ADS7846 Routines
49 */
50unsigned long corgi_ssp_ads7846_putget(ulong data)
51{
52 unsigned long flag;
53 u32 ret = 0;
54
55 spin_lock_irqsave(&corgi_ssp_lock, flag);
56 if (ssp_machinfo->cs_ads7846 >= 0)
57 GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
58
59 ssp_write_word(&corgi_ssp_dev,data);
60 ssp_read_word(&corgi_ssp_dev, &ret);
61
62 if (ssp_machinfo->cs_ads7846 >= 0)
63 GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
64 spin_unlock_irqrestore(&corgi_ssp_lock, flag);
65
66 return ret;
67}
68
69/*
70 * NOTE: These functions should always be called in interrupt context
71 * and use the _lock and _unlock functions. They are very time sensitive.
72 */
73void corgi_ssp_ads7846_lock(void)
74{
75 spin_lock(&corgi_ssp_lock);
76 if (ssp_machinfo->cs_ads7846 >= 0)
77 GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
78}
79
80void corgi_ssp_ads7846_unlock(void)
81{
82 if (ssp_machinfo->cs_ads7846 >= 0)
83 GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
84 spin_unlock(&corgi_ssp_lock);
85}
86
87void corgi_ssp_ads7846_put(ulong data)
88{
89 ssp_write_word(&corgi_ssp_dev,data);
90}
91
92unsigned long corgi_ssp_ads7846_get(void)
93{
94 u32 ret = 0;
95 ssp_read_word(&corgi_ssp_dev, &ret);
96 return ret;
97}
98
99EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
100EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
101EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
102EXPORT_SYMBOL(corgi_ssp_ads7846_put);
103EXPORT_SYMBOL(corgi_ssp_ads7846_get);
104
105
106/*
107 * LCD/Backlight Routines
108 */
109unsigned long corgi_ssp_dac_put(ulong data)
110{
111 unsigned long flag, sscr1 = SSCR1_SPH;
112 u32 tmp;
113
114 spin_lock_irqsave(&corgi_ssp_lock, flag);
115
116 if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
117 sscr1 = 0;
118
119 ssp_disable(&corgi_ssp_dev);
120 ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
121 ssp_enable(&corgi_ssp_dev);
122
123 if (ssp_machinfo->cs_lcdcon >= 0)
124 GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
125 ssp_write_word(&corgi_ssp_dev,data);
126 /* Read null data back from device to prevent SSP overflow */
127 ssp_read_word(&corgi_ssp_dev, &tmp);
128 if (ssp_machinfo->cs_lcdcon >= 0)
129 GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
130
131 ssp_disable(&corgi_ssp_dev);
132 ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
133 ssp_enable(&corgi_ssp_dev);
134
135 spin_unlock_irqrestore(&corgi_ssp_lock, flag);
136
137 return 0;
138}
139
140void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
141{
142 corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
143}
144
145void corgi_ssp_blduty_set(int duty)
146{
147 corgi_ssp_lcdtg_send(0x02,duty);
148}
149
150EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
151EXPORT_SYMBOL(corgi_ssp_blduty_set);
152
153/*
154 * Max1111 Routines
155 */
156int corgi_ssp_max1111_get(ulong data)
157{
158 unsigned long flag;
159 long voltage = 0, voltage1 = 0, voltage2 = 0;
160
161 spin_lock_irqsave(&corgi_ssp_lock, flag);
162 if (ssp_machinfo->cs_max1111 >= 0)
163 GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
164 ssp_disable(&corgi_ssp_dev);
165 ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
166 ssp_enable(&corgi_ssp_dev);
167
168 udelay(1);
169
170 /* TB1/RB1 */
171 ssp_write_word(&corgi_ssp_dev,data);
172 ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
173
174 /* TB12/RB2 */
175 ssp_write_word(&corgi_ssp_dev,0);
176 ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
177
178 /* TB13/RB3*/
179 ssp_write_word(&corgi_ssp_dev,0);
180 ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
181
182 ssp_disable(&corgi_ssp_dev);
183 ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
184 ssp_enable(&corgi_ssp_dev);
185 if (ssp_machinfo->cs_max1111 >= 0)
186 GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
187 spin_unlock_irqrestore(&corgi_ssp_lock, flag);
188
189 if (voltage1 & 0xc0 || voltage2 & 0x3f)
190 voltage = -1;
191 else
192 voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
193
194 return voltage;
195}
196
197EXPORT_SYMBOL(corgi_ssp_max1111_get);
198
199/*
200 * Support Routines
201 */
202
203void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
204{
205 ssp_machinfo = machinfo;
206}
207
208static int __init corgi_ssp_probe(struct platform_device *dev)
209{
210 int ret;
211
212 /* Chip Select - Disable All */
213 if (ssp_machinfo->cs_lcdcon >= 0)
214 pxa_gpio_mode(ssp_machinfo->cs_lcdcon | GPIO_OUT | GPIO_DFLT_HIGH);
215 if (ssp_machinfo->cs_max1111 >= 0)
216 pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
217 if (ssp_machinfo->cs_ads7846 >= 0)
218 pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
219
220 ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
221
222 if (ret)
223 printk(KERN_ERR "Unable to register SSP handler!\n");
224 else {
225 ssp_disable(&corgi_ssp_dev);
226 ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
227 ssp_enable(&corgi_ssp_dev);
228 }
229
230 return ret;
231}
232
233static int corgi_ssp_remove(struct platform_device *dev)
234{
235 ssp_exit(&corgi_ssp_dev);
236 return 0;
237}
238
239static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
240{
241 ssp_flush(&corgi_ssp_dev);
242 ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
243
244 return 0;
245}
246
247static int corgi_ssp_resume(struct platform_device *dev)
248{
249 if (ssp_machinfo->cs_lcdcon >= 0)
250 GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); /* High - Disable LCD Control/Timing Gen */
251 if (ssp_machinfo->cs_max1111 >= 0)
252 GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
253 if (ssp_machinfo->cs_ads7846 >= 0)
254 GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
255 ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
256 ssp_enable(&corgi_ssp_dev);
257
258 return 0;
259}
260
261static struct platform_driver corgissp_driver = {
262 .probe = corgi_ssp_probe,
263 .remove = corgi_ssp_remove,
264 .suspend = corgi_ssp_suspend,
265 .resume = corgi_ssp_resume,
266 .driver = {
267 .name = "corgi-ssp",
268 },
269};
270
271int __init corgi_ssp_init(void)
272{
273 return platform_driver_register(&corgissp_driver);
274}
275
276arch_initcall(corgi_ssp_init);
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index 585970ef08ce..7239281788de 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -113,6 +113,7 @@
113 * Shared data structures 113 * Shared data structures
114 */ 114 */
115extern struct platform_device corgiscoop_device; 115extern struct platform_device corgiscoop_device;
116extern struct platform_device corgissp_device;
116 117
117#endif /* __ASM_ARCH_CORGI_H */ 118#endif /* __ASM_ARCH_CORGI_H */
118 119
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index e8488dfb7e91..fa1998caa78e 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -187,4 +187,5 @@
187 */ 187 */
188extern struct platform_device spitzscoop_device; 188extern struct platform_device spitzscoop_device;
189extern struct platform_device spitzscoop2_device; 189extern struct platform_device spitzscoop2_device;
190extern struct platform_device spitzssp_device;
190extern struct sharpsl_charger_machinfo spitz_pm_machinfo; 191extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 15c2f1a8623b..f0845c1b001c 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -116,20 +116,33 @@ struct battery_thresh spitz_battery_levels_noac[] = {
116 { 0, 0}, 116 { 0, 0},
117}; 117};
118 118
119/* MAX1111 Commands */
120#define MAXCTRL_PD0 1u << 0
121#define MAXCTRL_PD1 1u << 1
122#define MAXCTRL_SGL 1u << 2
123#define MAXCTRL_UNI 1u << 3
124#define MAXCTRL_SEL_SH 4
125#define MAXCTRL_STR 1u << 7
126
119/* 127/*
120 * Read MAX1111 ADC 128 * Read MAX1111 ADC
121 */ 129 */
122extern int max1111_read_channel(int);
123
124int sharpsl_pm_pxa_read_max1111(int channel) 130int sharpsl_pm_pxa_read_max1111(int channel)
125{ 131{
126 if (machine_is_tosa()) // Ugly, better move this function into another module 132 if (machine_is_tosa()) // Ugly, better move this function into another module
127 return 0; 133 return 0;
128 134
135#ifdef CONFIG_CORGI_SSP_DEPRECATED
136 return corgi_ssp_max1111_get((channel << MAXCTRL_SEL_SH) | MAXCTRL_PD0 | MAXCTRL_PD1
137 | MAXCTRL_SGL | MAXCTRL_UNI | MAXCTRL_STR);
138#else
139 extern int max1111_read_channel(int);
140
129 /* max1111 accepts channels from 0-3, however, 141 /* max1111 accepts channels from 0-3, however,
130 * it is encoded from 0-7 here in the code. 142 * it is encoded from 0-7 here in the code.
131 */ 143 */
132 return max1111_read_channel(channel >> 1); 144 return max1111_read_channel(channel >> 1);
145#endif
133} 146}
134 147
135void sharpsl_pm_pxa_init(void) 148void sharpsl_pm_pxa_init(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 21:47:12 -0500