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-rw-r--r--arch/arm/mach-pxa/Makefile2
-rw-r--r--arch/arm/mach-pxa/dma.c144
-rw-r--r--arch/arm/mach-pxa/include/mach/dma.h83
3 files changed, 2 insertions, 227 deletions
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index fc96e7d454b1..70b46570c5cf 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o devices.o generic.o irq.o dma.o \ 6obj-y += clock.o devices.o generic.o irq.o \
7 time.o gpio.o reset.o 7 time.o gpio.o reset.o
8obj-$(CONFIG_PM) += pm.o sleep.o standby.o 8obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9 9
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c
deleted file mode 100644
index 01217e01f7d2..000000000000
--- a/arch/arm/mach-pxa/dma.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * linux/arch/arm/mach-pxa/dma.c
3 *
4 * PXA DMA registration and IRQ dispatching
5 *
6 * Author: Nicolas Pitre
7 * Created: Nov 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/errno.h>
20
21#include <asm/system.h>
22#include <asm/irq.h>
23#include <mach/hardware.h>
24#include <mach/dma.h>
25
26struct dma_channel {
27 char *name;
28 pxa_dma_prio prio;
29 void (*irq_handler)(int, void *);
30 void *data;
31};
32
33static struct dma_channel *dma_channels;
34static int num_dma_channels;
35
36int pxa_request_dma (char *name, pxa_dma_prio prio,
37 void (*irq_handler)(int, void *),
38 void *data)
39{
40 unsigned long flags;
41 int i, found = 0;
42
43 /* basic sanity checks */
44 if (!name || !irq_handler)
45 return -EINVAL;
46
47 local_irq_save(flags);
48
49 do {
50 /* try grabbing a DMA channel with the requested priority */
51 for (i = 0; i < num_dma_channels; i++) {
52 if ((dma_channels[i].prio == prio) &&
53 !dma_channels[i].name) {
54 found = 1;
55 break;
56 }
57 }
58 /* if requested prio group is full, try a hier priority */
59 } while (!found && prio--);
60
61 if (found) {
62 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
63 dma_channels[i].name = name;
64 dma_channels[i].irq_handler = irq_handler;
65 dma_channels[i].data = data;
66 } else {
67 printk (KERN_WARNING "No more available DMA channels for %s\n", name);
68 i = -ENODEV;
69 }
70
71 local_irq_restore(flags);
72 return i;
73}
74
75void pxa_free_dma (int dma_ch)
76{
77 unsigned long flags;
78
79 if (!dma_channels[dma_ch].name) {
80 printk (KERN_CRIT
81 "%s: trying to free channel %d which is already freed\n",
82 __func__, dma_ch);
83 return;
84 }
85
86 local_irq_save(flags);
87 DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
88 dma_channels[dma_ch].name = NULL;
89 local_irq_restore(flags);
90}
91
92static irqreturn_t dma_irq_handler(int irq, void *dev_id)
93{
94 int i, dint = DINT;
95
96 for (i = 0; i < num_dma_channels; i++) {
97 if (dint & (1 << i)) {
98 struct dma_channel *channel = &dma_channels[i];
99 if (channel->name && channel->irq_handler) {
100 channel->irq_handler(i, channel->data);
101 } else {
102 /*
103 * IRQ for an unregistered DMA channel:
104 * let's clear the interrupts and disable it.
105 */
106 printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i);
107 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
108 }
109 }
110 }
111 return IRQ_HANDLED;
112}
113
114int __init pxa_init_dma(int irq, int num_ch)
115{
116 int i, ret;
117
118 dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL);
119 if (dma_channels == NULL)
120 return -ENOMEM;
121
122 /* dma channel priorities on pxa2xx processors:
123 * ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
124 * ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
125 * ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
126 */
127 for (i = 0; i < num_ch; i++) {
128 DCSR(i) = 0;
129 dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
130 }
131
132 ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
133 if (ret) {
134 printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
135 kfree(dma_channels);
136 return ret;
137 }
138
139 num_dma_channels = num_ch;
140 return 0;
141}
142
143EXPORT_SYMBOL(pxa_request_dma);
144EXPORT_SYMBOL(pxa_free_dma);
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index b0812f59d3f8..5bd55894a48d 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -16,87 +16,6 @@
16 16
17/* DMA Controller Registers Definitions */ 17/* DMA Controller Registers Definitions */
18#define DMAC_REGS_VIRT io_p2v(0x40000000) 18#define DMAC_REGS_VIRT io_p2v(0x40000000)
19#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
20
21#define DCSR(n) DMAC_REG((n) << 2)
22#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
23#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
24#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
25#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
26#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
27#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
28#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
29 (((n) & 0x3f) << 2))
30
31#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
32#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
33#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
34#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
35#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
36#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
37#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
38#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
39
40#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
41#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
42#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
43#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
44#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
45#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
46#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
47#define DCSR_EORINTR (1 << 9) /* The end of Receive */
48#endif
49
50#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
51#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
52
53#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
54#define DDADR_STOP (1 << 0) /* Stop (read / write) */
55
56#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
57#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
58#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
59#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
60#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
61#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
62#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
63#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
64#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
65#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
66#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
67#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
68#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
69#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
70
71/*
72 * Descriptor structure for PXA's DMA engine
73 * Note: this structure must always be aligned to a 16-byte boundary.
74 */
75
76typedef struct pxa_dma_desc {
77 volatile u32 ddadr; /* Points to the next descriptor + flags */
78 volatile u32 dsadr; /* DSADR value for the current transfer */
79 volatile u32 dtadr; /* DTADR value for the current transfer */
80 volatile u32 dcmd; /* DCMD value for the current transfer */
81} pxa_dma_desc;
82
83typedef enum {
84 DMA_PRIO_HIGH = 0,
85 DMA_PRIO_MEDIUM = 1,
86 DMA_PRIO_LOW = 2
87} pxa_dma_prio;
88
89/*
90 * DMA registration
91 */
92
93int __init pxa_init_dma(int irq, int num_ch);
94
95int pxa_request_dma (char *name,
96 pxa_dma_prio prio,
97 void (*irq_handler)(int, void *),
98 void *data);
99
100void pxa_free_dma (int dma_ch);
101 19
20#include <plat/dma.h>
102#endif /* _ASM_ARCH_DMA_H */ 21#endif /* _ASM_ARCH_DMA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 06:13:15 -0500