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-rw-r--r--arch/arm/mach-pxa/lubbock.c30
-rw-r--r--arch/arm/mach-pxa/mainstone.c40
-rw-r--r--arch/arm/mach-pxa/pm.c32
-rw-r--r--arch/arm/mach-pxa/pxa25x.c33
-rw-r--r--arch/arm/mach-pxa/pxa27x.c36
5 files changed, 156 insertions, 15 deletions
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index dd012d6e2f5c..f2c9e0d2b24b 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -15,6 +15,7 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/sysdev.h>
18#include <linux/major.h> 19#include <linux/major.h>
19#include <linux/fb.h> 20#include <linux/fb.h>
20#include <linux/interrupt.h> 21#include <linux/interrupt.h>
@@ -106,6 +107,35 @@ static void __init lubbock_init_irq(void)
106 set_irq_type(IRQ_GPIO(0), IRQT_FALLING); 107 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
107} 108}
108 109
110#ifdef CONFIG_PM
111
112static int lubbock_irq_resume(struct sys_device *dev)
113{
114 LUB_IRQ_MASK_EN = lubbock_irq_enabled;
115 return 0;
116}
117
118static struct sysdev_class lubbock_irq_sysclass = {
119 set_kset_name("cpld_irq"),
120 .resume = lubbock_irq_resume,
121};
122
123static struct sys_device lubbock_irq_device = {
124 .cls = &lubbock_irq_sysclass,
125};
126
127static int __init lubbock_irq_device_init(void)
128{
129 int ret = sysdev_class_register(&lubbock_irq_sysclass);
130 if (ret == 0)
131 ret = sysdev_register(&lubbock_irq_device);
132 return ret;
133}
134
135device_initcall(lubbock_irq_device_init);
136
137#endif
138
109static int lubbock_udc_is_connected(void) 139static int lubbock_udc_is_connected(void)
110{ 140{
111 return (LUB_MISC_RD & (1 << 9)) == 0; 141 return (LUB_MISC_RD & (1 << 9)) == 0;
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 3f952237ae3d..9896afca751f 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -15,6 +15,7 @@
15 15
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/sysdev.h>
18#include <linux/interrupt.h> 19#include <linux/interrupt.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/bitops.h> 21#include <linux/bitops.h>
@@ -62,7 +63,6 @@ static struct irqchip mainstone_irq_chip = {
62 .unmask = mainstone_unmask_irq, 63 .unmask = mainstone_unmask_irq,
63}; 64};
64 65
65
66static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc, 66static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
67 struct pt_regs *regs) 67 struct pt_regs *regs)
68{ 68{
@@ -100,6 +100,35 @@ static void __init mainstone_init_irq(void)
100 set_irq_type(IRQ_GPIO(0), IRQT_FALLING); 100 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
101} 101}
102 102
103#ifdef CONFIG_PM
104
105static int mainstone_irq_resume(struct sys_device *dev)
106{
107 MST_INTMSKENA = mainstone_irq_enabled;
108 return 0;
109}
110
111static struct sysdev_class mainstone_irq_sysclass = {
112 set_kset_name("cpld_irq"),
113 .resume = mainstone_irq_resume,
114};
115
116static struct sys_device mainstone_irq_device = {
117 .cls = &mainstone_irq_sysclass,
118};
119
120static int __init mainstone_irq_device_init(void)
121{
122 int ret = sysdev_class_register(&mainstone_irq_sysclass);
123 if (ret == 0)
124 ret = sysdev_register(&mainstone_irq_device);
125 return ret;
126}
127
128device_initcall(mainstone_irq_device_init);
129
130#endif
131
103 132
104static struct resource smc91x_resources[] = { 133static struct resource smc91x_resources[] = {
105 [0] = { 134 [0] = {
@@ -304,6 +333,15 @@ static void __init mainstone_map_io(void)
304 PWER = 0xC0000002; 333 PWER = 0xC0000002;
305 PRER = 0x00000002; 334 PRER = 0x00000002;
306 PFER = 0x00000002; 335 PFER = 0x00000002;
336 /* for use I SRAM as framebuffer. */
337 PSLR |= 0xF04;
338 PCFR = 0x66;
339 /* For Keypad wakeup. */
340 KPC &=~KPC_ASACT;
341 KPC |=KPC_AS;
342 PKWR = 0x000FD000;
343 /* Need read PKWR back after set it. */
344 PKWR;
307} 345}
308 346
309MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") 347MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 82a4bf34c251..9799fe80df23 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -29,9 +29,6 @@
29 */ 29 */
30#undef DEBUG 30#undef DEBUG
31 31
32extern void pxa_cpu_suspend(void);
33extern void pxa_cpu_resume(void);
34
35#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 32#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
36#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 33#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
37 34
@@ -63,6 +60,12 @@ enum { SLEEP_SAVE_START = 0,
63 SLEEP_SAVE_ICMR, 60 SLEEP_SAVE_ICMR,
64 SLEEP_SAVE_CKEN, 61 SLEEP_SAVE_CKEN,
65 62
63#ifdef CONFIG_PXA27x
64 SLEEP_SAVE_MDREFR,
65 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
66 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
67#endif
68
66 SLEEP_SAVE_CKSUM, 69 SLEEP_SAVE_CKSUM,
67 70
68 SLEEP_SAVE_SIZE 71 SLEEP_SAVE_SIZE
@@ -75,9 +78,7 @@ static int pxa_pm_enter(suspend_state_t state)
75 unsigned long checksum = 0; 78 unsigned long checksum = 0;
76 struct timespec delta, rtc; 79 struct timespec delta, rtc;
77 int i; 80 int i;
78 81 extern void pxa_cpu_pm_enter(suspend_state_t state);
79 if (state != PM_SUSPEND_MEM)
80 return -EINVAL;
81 82
82#ifdef CONFIG_IWMMXT 83#ifdef CONFIG_IWMMXT
83 /* force any iWMMXt context to ram **/ 84 /* force any iWMMXt context to ram **/
@@ -100,16 +101,17 @@ static int pxa_pm_enter(suspend_state_t state)
100 SAVE(GAFR2_L); SAVE(GAFR2_U); 101 SAVE(GAFR2_L); SAVE(GAFR2_U);
101 102
102#ifdef CONFIG_PXA27x 103#ifdef CONFIG_PXA27x
104 SAVE(MDREFR);
103 SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3); 105 SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
104 SAVE(GAFR3_L); SAVE(GAFR3_U); 106 SAVE(GAFR3_L); SAVE(GAFR3_U);
107 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
108 SAVE(PFER); SAVE(PKWR);
105#endif 109#endif
106 110
107 SAVE(ICMR); 111 SAVE(ICMR);
108 ICMR = 0; 112 ICMR = 0;
109 113
110 SAVE(CKEN); 114 SAVE(CKEN);
111 CKEN = 0;
112
113 SAVE(PSTR); 115 SAVE(PSTR);
114 116
115 /* Note: wake up source are set up in each machine specific files */ 117 /* Note: wake up source are set up in each machine specific files */
@@ -123,16 +125,13 @@ static int pxa_pm_enter(suspend_state_t state)
123 /* Clear sleep reset status */ 125 /* Clear sleep reset status */
124 RCSR = RCSR_SMR; 126 RCSR = RCSR_SMR;
125 127
126 /* set resume return address */
127 PSPR = virt_to_phys(pxa_cpu_resume);
128
129 /* before sleeping, calculate and save a checksum */ 128 /* before sleeping, calculate and save a checksum */
130 for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) 129 for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
131 checksum += sleep_save[i]; 130 checksum += sleep_save[i];
132 sleep_save[SLEEP_SAVE_CKSUM] = checksum; 131 sleep_save[SLEEP_SAVE_CKSUM] = checksum;
133 132
134 /* *** go zzz *** */ 133 /* *** go zzz *** */
135 pxa_cpu_suspend(); 134 pxa_cpu_pm_enter(state);
136 135
137 /* after sleeping, validate the checksum */ 136 /* after sleeping, validate the checksum */
138 checksum = 0; 137 checksum = 0;
@@ -145,7 +144,7 @@ static int pxa_pm_enter(suspend_state_t state)
145 LUB_HEXLED = 0xbadbadc5; 144 LUB_HEXLED = 0xbadbadc5;
146#endif 145#endif
147 while (1) 146 while (1)
148 pxa_cpu_suspend(); 147 pxa_cpu_pm_enter(state);
149 } 148 }
150 149
151 /* ensure not to come back here if it wasn't intended */ 150 /* ensure not to come back here if it wasn't intended */
@@ -162,8 +161,11 @@ static int pxa_pm_enter(suspend_state_t state)
162 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 161 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
163 162
164#ifdef CONFIG_PXA27x 163#ifdef CONFIG_PXA27x
164 RESTORE(MDREFR);
165 RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3); 165 RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3);
166 RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3); 166 RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
167 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
168 RESTORE(PFER); RESTORE(PKWR);
167#endif 169#endif
168 170
169 PSSR = PSSR_RDH | PSSR_PH; 171 PSSR = PSSR_RDH | PSSR_PH;
@@ -197,7 +199,9 @@ unsigned long sleep_phys_sp(void *sp)
197 */ 199 */
198static int pxa_pm_prepare(suspend_state_t state) 200static int pxa_pm_prepare(suspend_state_t state)
199{ 201{
200 return 0; 202 extern int pxa_cpu_pm_prepare(suspend_state_t state);
203
204 return pxa_cpu_pm_prepare(state);
201} 205}
202 206
203/* 207/*
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index e887b7175ef3..7869c3b4e62f 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -16,6 +16,7 @@
16 * initialization stuff for PXA machines which can be overridden later if 16 * initialization stuff for PXA machines which can be overridden later if
17 * need be. 17 * need be.
18 */ 18 */
19#include <linux/config.h>
19#include <linux/module.h> 20#include <linux/module.h>
20#include <linux/kernel.h> 21#include <linux/kernel.h>
21#include <linux/init.h> 22#include <linux/init.h>
@@ -102,3 +103,35 @@ unsigned int get_lcdclk_frequency_10khz(void)
102} 103}
103 104
104EXPORT_SYMBOL(get_lcdclk_frequency_10khz); 105EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
106
107#ifdef CONFIG_PM
108
109int pxa_cpu_pm_prepare(suspend_state_t state)
110{
111 switch (state) {
112 case PM_SUSPEND_MEM:
113 break;
114 default:
115 return -EINVAL;
116 }
117
118 return 0;
119}
120
121void pxa_cpu_pm_enter(suspend_state_t state)
122{
123 extern void pxa_cpu_suspend(unsigned int);
124 extern void pxa_cpu_resume(void);
125
126 CKEN = 0;
127
128 switch (state) {
129 case PM_SUSPEND_MEM:
130 /* set resume return address */
131 PSPR = virt_to_phys(pxa_cpu_resume);
132 pxa_cpu_suspend(3);
133 break;
134 }
135}
136
137#endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7e863afefb53..893964fb9659 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -120,6 +120,42 @@ EXPORT_SYMBOL(get_clk_frequency_khz);
120EXPORT_SYMBOL(get_memclk_frequency_10khz); 120EXPORT_SYMBOL(get_memclk_frequency_10khz);
121EXPORT_SYMBOL(get_lcdclk_frequency_10khz); 121EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
122 122
123#ifdef CONFIG_PM
124
125int pxa_cpu_pm_prepare(suspend_state_t state)
126{
127 switch (state) {
128 case PM_SUSPEND_MEM:
129 return 0;
130 default:
131 return -EINVAL;
132 }
133}
134
135void pxa_cpu_pm_enter(suspend_state_t state)
136{
137 extern void pxa_cpu_standby(void);
138 extern void pxa_cpu_suspend(unsigned int);
139 extern void pxa_cpu_resume(void);
140
141 CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
142
143 /* ensure voltage-change sequencer not initiated, which hangs */
144 PCFR &= ~PCFR_FVC;
145
146 /* Clear edge-detect status register. */
147 PEDR = 0xDF12FE1B;
148
149 switch (state) {
150 case PM_SUSPEND_MEM:
151 /* set resume return address */
152 PSPR = virt_to_phys(pxa_cpu_resume);
153 pxa_cpu_suspend(3);
154 break;
155 }
156}
157
158#endif
123 159
124/* 160/*
125 * device registration specific to PXA27x. 161 * device registration specific to PXA27x.