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-rw-r--r--arch/arm/mach-pxa/time.c76
1 files changed, 34 insertions, 42 deletions
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 4bc47d63698b..8f1ee92aea30 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -89,48 +89,10 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
89 } 89 }
90} 90}
91 91
92static struct clock_event_device ckevt_pxa_osmr0 = {
93 .name = "osmr0",
94 .features = CLOCK_EVT_FEAT_ONESHOT,
95 .rating = 200,
96 .set_next_event = pxa_osmr0_set_next_event,
97 .set_mode = pxa_osmr0_set_mode,
98};
99
100static struct irqaction pxa_ost0_irq = {
101 .name = "ost0",
102 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
103 .handler = pxa_ost0_interrupt,
104 .dev_id = &ckevt_pxa_osmr0,
105};
106
107static void __init pxa_timer_init(void)
108{
109 unsigned long clock_tick_rate = get_clock_tick_rate();
110
111 writel_relaxed(0, OIER);
112 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
113
114 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
115
116 clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
117 ckevt_pxa_osmr0.max_delta_ns =
118 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
119 ckevt_pxa_osmr0.min_delta_ns =
120 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
121 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
122
123 setup_irq(IRQ_OST0, &pxa_ost0_irq);
124
125 clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
126 clocksource_mmio_readl_up);
127 clockevents_register_device(&ckevt_pxa_osmr0);
128}
129
130#ifdef CONFIG_PM 92#ifdef CONFIG_PM
131static unsigned long osmr[4], oier, oscr; 93static unsigned long osmr[4], oier, oscr;
132 94
133static void pxa_timer_suspend(void) 95static void pxa_timer_suspend(struct clock_event_device *cedev)
134{ 96{
135 osmr[0] = readl_relaxed(OSMR0); 97 osmr[0] = readl_relaxed(OSMR0);
136 osmr[1] = readl_relaxed(OSMR1); 98 osmr[1] = readl_relaxed(OSMR1);
@@ -140,7 +102,7 @@ static void pxa_timer_suspend(void)
140 oscr = readl_relaxed(OSCR); 102 oscr = readl_relaxed(OSCR);
141} 103}
142 104
143static void pxa_timer_resume(void) 105static void pxa_timer_resume(struct clock_event_device *cedev)
144{ 106{
145 /* 107 /*
146 * Ensure that we have at least MIN_OSCR_DELTA between match 108 * Ensure that we have at least MIN_OSCR_DELTA between match
@@ -163,8 +125,38 @@ static void pxa_timer_resume(void)
163#define pxa_timer_resume NULL 125#define pxa_timer_resume NULL
164#endif 126#endif
165 127
166struct sys_timer pxa_timer = { 128static struct clock_event_device ckevt_pxa_osmr0 = {
167 .init = pxa_timer_init, 129 .name = "osmr0",
130 .features = CLOCK_EVT_FEAT_ONESHOT,
131 .rating = 200,
132 .set_next_event = pxa_osmr0_set_next_event,
133 .set_mode = pxa_osmr0_set_mode,
168 .suspend = pxa_timer_suspend, 134 .suspend = pxa_timer_suspend,
169 .resume = pxa_timer_resume, 135 .resume = pxa_timer_resume,
170}; 136};
137
138static struct irqaction pxa_ost0_irq = {
139 .name = "ost0",
140 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
141 .handler = pxa_ost0_interrupt,
142 .dev_id = &ckevt_pxa_osmr0,
143};
144
145void __init pxa_timer_init(void)
146{
147 unsigned long clock_tick_rate = get_clock_tick_rate();
148
149 writel_relaxed(0, OIER);
150 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
151
152 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
153
154 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
155
156 setup_irq(IRQ_OST0, &pxa_ost0_irq);
157
158 clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
159 clocksource_mmio_readl_up);
160 clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
161 MIN_OSCR_DELTA * 2, 0x7fffffff);
162}