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-rw-r--r--arch/arm/mach-pxa/time.c76
1 files changed, 38 insertions, 38 deletions
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 4bc47d63698b..ce58bc9acb14 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -89,12 +89,50 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
89 } 89 }
90} 90}
91 91
92#ifdef CONFIG_PM
93static unsigned long osmr[4], oier, oscr;
94
95static void pxa_timer_suspend(struct clock_event_device *cedev)
96{
97 osmr[0] = readl_relaxed(OSMR0);
98 osmr[1] = readl_relaxed(OSMR1);
99 osmr[2] = readl_relaxed(OSMR2);
100 osmr[3] = readl_relaxed(OSMR3);
101 oier = readl_relaxed(OIER);
102 oscr = readl_relaxed(OSCR);
103}
104
105static void pxa_timer_resume(struct clock_event_device *cedev)
106{
107 /*
108 * Ensure that we have at least MIN_OSCR_DELTA between match
109 * register 0 and the OSCR, to guarantee that we will receive
110 * the one-shot timer interrupt. We adjust OSMR0 in preference
111 * to OSCR to guarantee that OSCR is monotonically incrementing.
112 */
113 if (osmr[0] - oscr < MIN_OSCR_DELTA)
114 osmr[0] += MIN_OSCR_DELTA;
115
116 writel_relaxed(osmr[0], OSMR0);
117 writel_relaxed(osmr[1], OSMR1);
118 writel_relaxed(osmr[2], OSMR2);
119 writel_relaxed(osmr[3], OSMR3);
120 writel_relaxed(oier, OIER);
121 writel_relaxed(oscr, OSCR);
122}
123#else
124#define pxa_timer_suspend NULL
125#define pxa_timer_resume NULL
126#endif
127
92static struct clock_event_device ckevt_pxa_osmr0 = { 128static struct clock_event_device ckevt_pxa_osmr0 = {
93 .name = "osmr0", 129 .name = "osmr0",
94 .features = CLOCK_EVT_FEAT_ONESHOT, 130 .features = CLOCK_EVT_FEAT_ONESHOT,
95 .rating = 200, 131 .rating = 200,
96 .set_next_event = pxa_osmr0_set_next_event, 132 .set_next_event = pxa_osmr0_set_next_event,
97 .set_mode = pxa_osmr0_set_mode, 133 .set_mode = pxa_osmr0_set_mode,
134 .suspend = pxa_timer_suspend,
135 .resume = pxa_timer_resume,
98}; 136};
99 137
100static struct irqaction pxa_ost0_irq = { 138static struct irqaction pxa_ost0_irq = {
@@ -127,44 +165,6 @@ static void __init pxa_timer_init(void)
127 clockevents_register_device(&ckevt_pxa_osmr0); 165 clockevents_register_device(&ckevt_pxa_osmr0);
128} 166}
129 167
130#ifdef CONFIG_PM
131static unsigned long osmr[4], oier, oscr;
132
133static void pxa_timer_suspend(void)
134{
135 osmr[0] = readl_relaxed(OSMR0);
136 osmr[1] = readl_relaxed(OSMR1);
137 osmr[2] = readl_relaxed(OSMR2);
138 osmr[3] = readl_relaxed(OSMR3);
139 oier = readl_relaxed(OIER);
140 oscr = readl_relaxed(OSCR);
141}
142
143static void pxa_timer_resume(void)
144{
145 /*
146 * Ensure that we have at least MIN_OSCR_DELTA between match
147 * register 0 and the OSCR, to guarantee that we will receive
148 * the one-shot timer interrupt. We adjust OSMR0 in preference
149 * to OSCR to guarantee that OSCR is monotonically incrementing.
150 */
151 if (osmr[0] - oscr < MIN_OSCR_DELTA)
152 osmr[0] += MIN_OSCR_DELTA;
153
154 writel_relaxed(osmr[0], OSMR0);
155 writel_relaxed(osmr[1], OSMR1);
156 writel_relaxed(osmr[2], OSMR2);
157 writel_relaxed(osmr[3], OSMR3);
158 writel_relaxed(oier, OIER);
159 writel_relaxed(oscr, OSCR);
160}
161#else
162#define pxa_timer_suspend NULL
163#define pxa_timer_resume NULL
164#endif
165
166struct sys_timer pxa_timer = { 168struct sys_timer pxa_timer = {
167 .init = pxa_timer_init, 169 .init = pxa_timer_init,
168 .suspend = pxa_timer_suspend,
169 .resume = pxa_timer_resume,
170}; 170};