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-rw-r--r--arch/arm/mach-pxa/mainstone.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 07892f4012d8..277498ae5b6c 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -43,6 +43,7 @@
43#include <asm/arch/pxafb.h> 43#include <asm/arch/pxafb.h>
44#include <asm/arch/mmc.h> 44#include <asm/arch/mmc.h>
45#include <asm/arch/irda.h> 45#include <asm/arch/irda.h>
46#include <asm/arch/ohci.h>
46 47
47#include "generic.h" 48#include "generic.h"
48 49
@@ -393,6 +394,25 @@ static struct platform_device *platform_devices[] __initdata = {
393 &mst_flash_device[1], 394 &mst_flash_device[1],
394}; 395};
395 396
397static int mainstone_ohci_init(struct device *dev)
398{
399 /* setup Port1 GPIO pin. */
400 pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
401 pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
402
403 /* Set the Power Control Polarity Low and Power Sense
404 Polarity Low to active low. */
405 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
406 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
407
408 return 0;
409}
410
411static struct pxaohci_platform_data mainstone_ohci_platform_data = {
412 .port_mode = PMM_PERPORT_MODE,
413 .init = mainstone_ohci_init,
414};
415
396static void __init mainstone_init(void) 416static void __init mainstone_init(void)
397{ 417{
398 int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */ 418 int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
@@ -424,6 +444,7 @@ static void __init mainstone_init(void)
424 444
425 pxa_set_mci_info(&mainstone_mci_platform_data); 445 pxa_set_mci_info(&mainstone_mci_platform_data);
426 pxa_set_ficp_info(&mainstone_ficp_platform_data); 446 pxa_set_ficp_info(&mainstone_ficp_platform_data);
447 pxa_set_ohci_info(&mainstone_ohci_platform_data);
427} 448}
428 449
429 450